Revision cd1a3f68 hw/sh7750_regs.h

b/hw/sh7750_regs.h
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					   year counters are stopped
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					   1 - sec, min, hr, day-of-week, month,
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					   year counters operate normally */
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/*
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 * Timer Unit (TMU)
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 */
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/* Timer Output Control Register (byte) - TOCR */
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#define SH7750_TOCR_REGOFS    0xD80000	/* offset */
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#define SH7750_TOCR           SH7750_P4_REG32(SH7750_TOCR_REGOFS)
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#define SH7750_TOCR_A7        SH7750_A7_REG32(SH7750_TOCR_REGOFS)
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#define SH7750_TOCR_TCOE      0x01	/* Timer Clock Pin Control:
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					   0 - TCLK is used as external clock
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					   input or input capture control
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					   1 - TCLK is used as on-chip RTC
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					   output clock pin */
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/* Timer Start Register (byte) - TSTR */
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#define SH7750_TSTR_REGOFS    0xD80004	/* offset */
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#define SH7750_TSTR           SH7750_P4_REG32(SH7750_TSTR_REGOFS)
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#define SH7750_TSTR_A7        SH7750_A7_REG32(SH7750_TSTR_REGOFS)
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#define SH7750_TSTR_STR2      0x04	/* TCNT2 performs count operations */
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#define SH7750_TSTR_STR1      0x02	/* TCNT1 performs count operations */
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#define SH7750_TSTR_STR0      0x01	/* TCNT0 performs count operations */
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#define SH7750_TSTR_STR(n)    (1 << (n))
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/* Timer Constant Register - TCOR0, TCOR1, TCOR2 */
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#define SH7750_TCOR_REGOFS(n) (0xD80008 + ((n)*12))	/* offset */
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#define SH7750_TCOR(n)        SH7750_P4_REG32(SH7750_TCOR_REGOFS(n))
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#define SH7750_TCOR_A7(n)     SH7750_A7_REG32(SH7750_TCOR_REGOFS(n))
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#define SH7750_TCOR0          SH7750_TCOR(0)
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#define SH7750_TCOR1          SH7750_TCOR(1)
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#define SH7750_TCOR2          SH7750_TCOR(2)
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#define SH7750_TCOR0_A7       SH7750_TCOR_A7(0)
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#define SH7750_TCOR1_A7       SH7750_TCOR_A7(1)
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#define SH7750_TCOR2_A7       SH7750_TCOR_A7(2)
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/* Timer Counter Register - TCNT0, TCNT1, TCNT2 */
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#define SH7750_TCNT_REGOFS(n) (0xD8000C + ((n)*12))	/* offset */
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#define SH7750_TCNT(n)        SH7750_P4_REG32(SH7750_TCNT_REGOFS(n))
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#define SH7750_TCNT_A7(n)     SH7750_A7_REG32(SH7750_TCNT_REGOFS(n))
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#define SH7750_TCNT0          SH7750_TCNT(0)
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#define SH7750_TCNT1          SH7750_TCNT(1)
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#define SH7750_TCNT2          SH7750_TCNT(2)
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#define SH7750_TCNT0_A7       SH7750_TCNT_A7(0)
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#define SH7750_TCNT1_A7       SH7750_TCNT_A7(1)
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#define SH7750_TCNT2_A7       SH7750_TCNT_A7(2)
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/* Timer Control Register (half) - TCR0, TCR1, TCR2 */
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#define SH7750_TCR_REGOFS(n)  (0xD80010 + ((n)*12))	/* offset */
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#define SH7750_TCR(n)         SH7750_P4_REG32(SH7750_TCR_REGOFS(n))
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#define SH7750_TCR_A7(n)      SH7750_A7_REG32(SH7750_TCR_REGOFS(n))
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#define SH7750_TCR0           SH7750_TCR(0)
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#define SH7750_TCR1           SH7750_TCR(1)
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#define SH7750_TCR2           SH7750_TCR(2)
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#define SH7750_TCR0_A7        SH7750_TCR_A7(0)
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#define SH7750_TCR1_A7        SH7750_TCR_A7(1)
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#define SH7750_TCR2_A7        SH7750_TCR_A7(2)
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#define SH7750_TCR2_ICPF       0x200	/* Input Capture Interrupt Flag
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					   (1 - input capture has occured) */
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#define SH7750_TCR_UNF         0x100	/* Underflow flag */
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#define SH7750_TCR2_ICPE       0x0C0	/* Input Capture Control: */
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#define SH7750_TCR2_ICPE_DIS   0x000	/*   Input Capture function is not used */
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#define SH7750_TCR2_ICPE_NOINT 0x080	/*   Input Capture function is used, but
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					   input capture interrupt is not
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					   enabled */
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#define SH7750_TCR2_ICPE_INT   0x0C0	/*   Input Capture function is used,
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					   input capture interrupt enabled */
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#define SH7750_TCR_UNIE        0x020	/* Underflow Interrupt Control
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					   (1 - underflow interrupt enabled) */
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#define SH7750_TCR_CKEG        0x018	/* Clock Edge selection: */
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#define SH7750_TCR_CKEG_RAISE  0x000	/*   Count/capture on rising edge */
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#define SH7750_TCR_CKEG_FALL   0x008	/*   Count/capture on falling edge */
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#define SH7750_TCR_CKEG_BOTH   0x018	/*   Count/capture on both rising and
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					   falling edges */
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#define SH7750_TCR_TPSC         0x007	/* Timer prescaler */
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#define SH7750_TCR_TPSC_DIV4    0x000	/*   Counts on peripheral clock/4 */
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#define SH7750_TCR_TPSC_DIV16   0x001	/*   Counts on peripheral clock/16 */
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#define SH7750_TCR_TPSC_DIV64   0x002	/*   Counts on peripheral clock/64 */
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#define SH7750_TCR_TPSC_DIV256  0x003	/*   Counts on peripheral clock/256 */
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#define SH7750_TCR_TPSC_DIV1024 0x004	/*   Counts on peripheral clock/1024 */
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#define SH7750_TCR_TPSC_RTC     0x006	/*   Counts on on-chip RTC output clk */
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#define SH7750_TCR_TPSC_EXT     0x007	/*   Counts on external clock */
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/* Input Capture Register (read-only) - TCPR2 */
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#define SH7750_TCPR2_REGOFS   0xD8002C	/* offset */
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#define SH7750_TCPR2          SH7750_P4_REG32(SH7750_TCPR2_REGOFS)
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#define SH7750_TCPR2_A7       SH7750_A7_REG32(SH7750_TCPR2_REGOFS)
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/*
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 * Bus State Controller - BSC
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 */

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