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1
/*
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 * SH7750 device
3
 *
4
 * Copyright (c) 2005 Samuel Tardieu
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
23
 */
24
#include <stdio.h>
25
#include <assert.h>
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#include "vl.h"
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#include "sh7750_regs.h"
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#include "sh7750_regnames.h"
29

    
30
typedef struct {
31
    uint8_t data[16];
32
    uint8_t length;                /* Number of characters in the FIFO */
33
    uint8_t write_idx;                /* Index of first character to write */
34
    uint8_t read_idx;                /* Index of first character to read */
35
} fifo;
36

    
37
#define NB_DEVICES 4
38

    
39
typedef struct SH7750State {
40
    /* CPU */
41
    CPUSH4State *cpu;
42
    /* Peripheral frequency in Hz */
43
    uint32_t periph_freq;
44
    /* SDRAM controller */
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    uint16_t rfcr;
46
    /* First serial port */
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    CharDriverState *serial1;
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    uint8_t scscr1;
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    uint8_t scsmr1;
50
    uint8_t scbrr1;
51
    uint8_t scssr1;
52
    uint8_t scssr1_read;
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    uint8_t sctsr1;
54
    uint8_t sctsr1_loaded;
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    uint8_t sctdr1;
56
    uint8_t scrdr1;
57
    /* Second serial port */
58
    CharDriverState *serial2;
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    uint16_t sclsr2;
60
    uint16_t scscr2;
61
    uint16_t scfcr2;
62
    uint16_t scfsr2;
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    uint16_t scsmr2;
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    uint8_t scbrr2;
65
    fifo serial2_receive_fifo;
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    fifo serial2_transmit_fifo;
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    /* IO ports */
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    uint16_t gpioic;
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    uint32_t pctra;
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    uint32_t pctrb;
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    uint16_t portdira;                /* Cached */
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    uint16_t portpullupa;        /* Cached */
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    uint16_t portdirb;                /* Cached */
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    uint16_t portpullupb;        /* Cached */
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    uint16_t pdtra;
76
    uint16_t pdtrb;
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    uint16_t periph_pdtra;        /* Imposed by the peripherals */
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    uint16_t periph_portdira;        /* Direction seen from the peripherals */
79
    uint16_t periph_pdtrb;        /* Imposed by the peripherals */
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    uint16_t periph_portdirb;        /* Direction seen from the peripherals */
81
    sh7750_io_device *devices[NB_DEVICES];        /* External peripherals */
82
    /* Cache */
83
    uint32_t ccr;
84

    
85
} SH7750State;
86

    
87
/**********************************************************************
88
 First serial port
89
**********************************************************************/
90

    
91
static int serial1_can_receive(void *opaque)
92
{
93
    SH7750State *s = opaque;
94

    
95
    return s->scscr1 & SH7750_SCSCR_RE;
96
}
97

    
98
static void serial1_receive_char(SH7750State * s, uint8_t c)
99
{
100
    if (s->scssr1 & SH7750_SCSSR1_RDRF) {
101
        s->scssr1 |= SH7750_SCSSR1_ORER;
102
        return;
103
    }
104

    
105
    s->scrdr1 = c;
106
    s->scssr1 |= SH7750_SCSSR1_RDRF;
107
}
108

    
109
static void serial1_receive(void *opaque, const uint8_t * buf, int size)
110
{
111
    SH7750State *s = opaque;
112
    int i;
113

    
114
    for (i = 0; i < size; i++) {
115
        serial1_receive_char(s, buf[i]);
116
    }
117
}
118

    
119
static void serial1_event(void *opaque, int event)
120
{
121
    assert(0);
122
}
123

    
124
static void serial1_maybe_send(SH7750State * s)
125
{
126
    uint8_t c;
127

    
128
    if (s->scssr1 & SH7750_SCSSR1_TDRE)
129
        return;
130
    c = s->sctdr1;
131
    s->scssr1 |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND;
132
    if (s->scscr1 & SH7750_SCSCR_TIE) {
133
        fprintf(stderr, "interrupts for serial port 1 not implemented\n");
134
        assert(0);
135
    }
136
    /* XXXXX Check for errors in write */
137
    qemu_chr_write(s->serial1, &c, 1);
138
}
139

    
140
static void serial1_change_scssr1(SH7750State * s, uint8_t mem_value)
141
{
142
    uint8_t new_flags;
143

    
144
    /* If transmit disable, TDRE and TEND stays up */
145
    if ((s->scscr1 & SH7750_SCSCR_TE) == 0) {
146
        mem_value |= SH7750_SCSSR1_TDRE | SH7750_SCSSR1_TEND;
147
    }
148

    
149
    /* Only clear bits which have been read before and do not set any bit
150
       in the flags */
151
    new_flags = s->scssr1 & ~s->scssr1_read;        /* Preserve unread flags */
152
    new_flags &= mem_value | ~s->scssr1_read;        /* Clear read flags */
153

    
154
    s->scssr1 = (new_flags & 0xf8) | (mem_value & 1);
155
    s->scssr1_read &= mem_value;
156

    
157
    /* If TDRE has been cleared, TEND will also be cleared */
158
    if ((s->scssr1 & SH7750_SCSSR1_TDRE) == 0) {
159
        s->scssr1 &= ~SH7750_SCSSR1_TEND;
160
    }
161

    
162
    /* Check for transmission to start */
163
    serial1_maybe_send(s);
164
}
165

    
166
static void serial1_update_parameters(SH7750State * s)
167
{
168
    QEMUSerialSetParams ssp;
169

    
170
    if (s->scsmr1 & SH7750_SCSMR_CHR_7)
171
        ssp.data_bits = 7;
172
    else
173
        ssp.data_bits = 8;
174
    if (s->scsmr1 & SH7750_SCSMR_PE) {
175
        if (s->scsmr1 & SH7750_SCSMR_PM_ODD)
176
            ssp.parity = 'O';
177
        else
178
            ssp.parity = 'E';
179
    } else
180
        ssp.parity = 'N';
181
    if (s->scsmr1 & SH7750_SCSMR_STOP_2)
182
        ssp.stop_bits = 2;
183
    else
184
        ssp.stop_bits = 1;
185
    fprintf(stderr, "SCSMR1=%04x SCBRR1=%02x\n", s->scsmr1, s->scbrr1);
186
    ssp.speed = s->periph_freq /
187
        (32 * s->scbrr1 * (1 << (2 * (s->scsmr1 & 3)))) - 1;
188
    fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n",
189
            ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed);
190
    qemu_chr_ioctl(s->serial1, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
191
}
192

    
193
static void scscr1_changed(SH7750State * s)
194
{
195
    if (s->scscr1 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) {
196
        if (!s->serial1) {
197
            fprintf(stderr, "serial port 1 not bound to anything\n");
198
            assert(0);
199
        }
200
        serial1_update_parameters(s);
201
    }
202
    if ((s->scscr1 & SH7750_SCSCR_RE) == 0) {
203
        s->scssr1 |= SH7750_SCSSR1_TDRE;
204
    }
205
}
206

    
207
static void init_serial1(SH7750State * s, int serial_nb)
208
{
209
    CharDriverState *chr;
210

    
211
    s->scssr1 = 0x84;
212
    chr = serial_hds[serial_nb];
213
    if (!chr) {
214
        fprintf(stderr,
215
                "no serial port associated to SH7750 first serial port\n");
216
        return;
217
    }
218

    
219
    s->serial1 = chr;
220
    qemu_chr_add_handlers(chr, serial1_can_receive,
221
                          serial1_receive, serial1_event, s);
222
}
223

    
224
/**********************************************************************
225
 Second serial port
226
**********************************************************************/
227

    
228
static int serial2_can_receive(void *opaque)
229
{
230
    SH7750State *s = opaque;
231
    static uint8_t max_fifo_size[] = { 15, 1, 4, 6, 8, 10, 12, 14 };
232

    
233
    return s->serial2_receive_fifo.length <
234
        max_fifo_size[(s->scfcr2 >> 9) & 7];
235
}
236

    
237
static void serial2_adjust_receive_flags(SH7750State * s)
238
{
239
    static uint8_t max_fifo_size[] = { 1, 4, 8, 14 };
240

    
241
    /* XXXXX Add interrupt generation */
242
    if (s->serial2_receive_fifo.length >=
243
        max_fifo_size[(s->scfcr2 >> 7) & 3]) {
244
        s->scfsr2 |= SH7750_SCFSR2_RDF;
245
        s->scfsr2 &= ~SH7750_SCFSR2_DR;
246
    } else {
247
        s->scfsr2 &= ~SH7750_SCFSR2_RDF;
248
        if (s->serial2_receive_fifo.length > 0)
249
            s->scfsr2 |= SH7750_SCFSR2_DR;
250
        else
251
            s->scfsr2 &= ~SH7750_SCFSR2_DR;
252
    }
253
}
254

    
255
static void serial2_append_char(SH7750State * s, uint8_t c)
256
{
257
    if (s->serial2_receive_fifo.length == 16) {
258
        /* Overflow */
259
        s->sclsr2 |= SH7750_SCLSR2_ORER;
260
        return;
261
    }
262

    
263
    s->serial2_receive_fifo.data[s->serial2_receive_fifo.write_idx++] = c;
264
    s->serial2_receive_fifo.length++;
265
    serial2_adjust_receive_flags(s);
266
}
267

    
268
static void serial2_receive(void *opaque, const uint8_t * buf, int size)
269
{
270
    SH7750State *s = opaque;
271
    int i;
272

    
273
    for (i = 0; i < size; i++)
274
        serial2_append_char(s, buf[i]);
275
}
276

    
277
static void serial2_event(void *opaque, int event)
278
{
279
    /* XXXXX */
280
    assert(0);
281
}
282

    
283
static void serial2_update_parameters(SH7750State * s)
284
{
285
    QEMUSerialSetParams ssp;
286

    
287
    if (s->scsmr2 & SH7750_SCSMR_CHR_7)
288
        ssp.data_bits = 7;
289
    else
290
        ssp.data_bits = 8;
291
    if (s->scsmr2 & SH7750_SCSMR_PE) {
292
        if (s->scsmr2 & SH7750_SCSMR_PM_ODD)
293
            ssp.parity = 'O';
294
        else
295
            ssp.parity = 'E';
296
    } else
297
        ssp.parity = 'N';
298
    if (s->scsmr2 & SH7750_SCSMR_STOP_2)
299
        ssp.stop_bits = 2;
300
    else
301
        ssp.stop_bits = 1;
302
    fprintf(stderr, "SCSMR2=%04x SCBRR2=%02x\n", s->scsmr2, s->scbrr2);
303
    ssp.speed = s->periph_freq /
304
        (32 * s->scbrr2 * (1 << (2 * (s->scsmr2 & 3)))) - 1;
305
    fprintf(stderr, "data bits=%d, stop bits=%d, parity=%c, speed=%d\n",
306
            ssp.data_bits, ssp.stop_bits, ssp.parity, ssp.speed);
307
    qemu_chr_ioctl(s->serial2, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
308
}
309

    
310
static void scscr2_changed(SH7750State * s)
311
{
312
    if (s->scscr2 & (SH7750_SCSCR_TE | SH7750_SCSCR_RE)) {
313
        if (!s->serial2) {
314
            fprintf(stderr, "serial port 2 not bound to anything\n");
315
            assert(0);
316
        }
317
        serial2_update_parameters(s);
318
    }
319
}
320

    
321
static void init_serial2(SH7750State * s, int serial_nb)
322
{
323
    CharDriverState *chr;
324

    
325
    s->scfsr2 = 0x0060;
326

    
327
    chr = serial_hds[serial_nb];
328
    if (!chr) {
329
        fprintf(stderr,
330
                "no serial port associated to SH7750 second serial port\n");
331
        return;
332
    }
333

    
334
    s->serial2 = chr;
335
    qemu_chr_add_handlers(chr, serial2_can_receive,
336
                          serial2_receive, serial1_event, s);
337
}
338

    
339
static void init_serial_ports(SH7750State * s)
340
{
341
    init_serial1(s, 0);
342
    init_serial2(s, 1);
343
}
344

    
345
/**********************************************************************
346
 I/O ports
347
**********************************************************************/
348

    
349
int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
350
{
351
    int i;
352

    
353
    for (i = 0; i < NB_DEVICES; i++) {
354
        if (s->devices[i] == NULL) {
355
            s->devices[i] = device;
356
            return 0;
357
        }
358
    }
359
    return -1;
360
}
361

    
362
static uint16_t portdir(uint32_t v)
363
{
364
#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
365
    return
366
        EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
367
        EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
368
        EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
369
        EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
370
        EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
371
        EVENPORTMASK(0);
372
}
373

    
374
static uint16_t portpullup(uint32_t v)
375
{
376
#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
377
    return
378
        ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
379
        ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
380
        ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
381
        ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
382
        ODDPORTMASK(1) | ODDPORTMASK(0);
383
}
384

    
385
static uint16_t porta_lines(SH7750State * s)
386
{
387
    return (s->portdira & s->pdtra) |        /* CPU */
388
        (s->periph_portdira & s->periph_pdtra) |        /* Peripherals */
389
        (~(s->portdira | s->periph_portdira) & s->portpullupa);        /* Pullups */
390
}
391

    
392
static uint16_t portb_lines(SH7750State * s)
393
{
394
    return (s->portdirb & s->pdtrb) |        /* CPU */
395
        (s->periph_portdirb & s->periph_pdtrb) |        /* Peripherals */
396
        (~(s->portdirb | s->periph_portdirb) & s->portpullupb);        /* Pullups */
397
}
398

    
399
static void gen_port_interrupts(SH7750State * s)
400
{
401
    /* XXXXX interrupts not generated */
402
}
403

    
404
static void porta_changed(SH7750State * s, uint16_t prev)
405
{
406
    uint16_t currenta, changes;
407
    int i, r = 0;
408

    
409
#if 0
410
    fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
411
            prev, porta_lines(s));
412
    fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
413
#endif
414
    currenta = porta_lines(s);
415
    if (currenta == prev)
416
        return;
417
    changes = currenta ^ prev;
418

    
419
    for (i = 0; i < NB_DEVICES; i++) {
420
        if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
421
            r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
422
                                               &s->periph_pdtra,
423
                                               &s->periph_portdira,
424
                                               &s->periph_pdtrb,
425
                                               &s->periph_portdirb);
426
        }
427
    }
428

    
429
    if (r)
430
        gen_port_interrupts(s);
431
}
432

    
433
static void portb_changed(SH7750State * s, uint16_t prev)
434
{
435
    uint16_t currentb, changes;
436
    int i, r = 0;
437

    
438
    currentb = portb_lines(s);
439
    if (currentb == prev)
440
        return;
441
    changes = currentb ^ prev;
442

    
443
    for (i = 0; i < NB_DEVICES; i++) {
444
        if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
445
            r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
446
                                               &s->periph_pdtra,
447
                                               &s->periph_portdira,
448
                                               &s->periph_pdtrb,
449
                                               &s->periph_portdirb);
450
        }
451
    }
452

    
453
    if (r)
454
        gen_port_interrupts(s);
455
}
456

    
457
/**********************************************************************
458
 Memory
459
**********************************************************************/
460

    
461
static void error_access(const char *kind, target_phys_addr_t addr)
462
{
463
    fprintf(stderr, "%s to %s (0x%08x) not supported\n",
464
            kind, regname(addr), addr);
465
}
466

    
467
static void ignore_access(const char *kind, target_phys_addr_t addr)
468
{
469
    fprintf(stderr, "%s to %s (0x%08x) ignored\n",
470
            kind, regname(addr), addr);
471
}
472

    
473
static uint32_t sh7750_mem_readb(void *opaque, target_phys_addr_t addr)
474
{
475
    SH7750State *s = opaque;
476
    uint8_t r;
477

    
478
    switch (addr) {
479
    case SH7750_SCSSR1_A7:
480
        r = s->scssr1;
481
        s->scssr1_read |= r;
482
        return s->scssr1;
483
    case SH7750_SCRDR1_A7:
484
        s->scssr1 &= ~SH7750_SCSSR1_RDRF;
485
        return s->scrdr1;
486
    default:
487
        error_access("byte read", addr);
488
        assert(0);
489
    }
490
}
491

    
492
static uint32_t sh7750_mem_readw(void *opaque, target_phys_addr_t addr)
493
{
494
    SH7750State *s = opaque;
495
    uint16_t r;
496

    
497
    switch (addr) {
498
    case SH7750_RFCR_A7:
499
        fprintf(stderr,
500
                "Read access to refresh count register, incrementing\n");
501
        return s->rfcr++;
502
    case SH7750_SCLSR2_A7:
503
        /* Read and clear overflow bit */
504
        r = s->sclsr2;
505
        s->sclsr2 = 0;
506
        return r;
507
    case SH7750_SCSFR2_A7:
508
        return s->scfsr2;
509
    case SH7750_PDTRA_A7:
510
        return porta_lines(s);
511
    case SH7750_PDTRB_A7:
512
        return portb_lines(s);
513
    default:
514
        error_access("word read", addr);
515
        assert(0);
516
    }
517
}
518

    
519
static uint32_t sh7750_mem_readl(void *opaque, target_phys_addr_t addr)
520
{
521
    SH7750State *s = opaque;
522

    
523
    switch (addr) {
524
    case SH7750_MMUCR_A7:
525
        return s->cpu->mmucr;
526
    case SH7750_PTEH_A7:
527
        return s->cpu->pteh;
528
    case SH7750_PTEL_A7:
529
        return s->cpu->ptel;
530
    case SH7750_TTB_A7:
531
        return s->cpu->ttb;
532
    case SH7750_TEA_A7:
533
        return s->cpu->tea;
534
    case SH7750_TRA_A7:
535
        return s->cpu->tra;
536
    case SH7750_EXPEVT_A7:
537
        return s->cpu->expevt;
538
    case SH7750_INTEVT_A7:
539
        return s->cpu->intevt;
540
    case SH7750_CCR_A7:
541
        return s->ccr;
542
    case 0x1f000030:                /* Processor version PVR */
543
        return 0x00050000;        /* SH7750R */
544
    case 0x1f000040:                /* Processor version CVR */
545
        return 0x00110000;        /* Minimum caches */
546
    case 0x1f000044:                /* Processor version PRR */
547
        return 0x00000100;        /* SH7750R */
548
    default:
549
        error_access("long read", addr);
550
        assert(0);
551
    }
552
}
553

    
554
static void sh7750_mem_writeb(void *opaque, target_phys_addr_t addr,
555
                              uint32_t mem_value)
556
{
557
    SH7750State *s = opaque;
558

    
559
    switch (addr) {
560
        /* PRECHARGE ? XXXXX */
561
    case SH7750_PRECHARGE0_A7:
562
    case SH7750_PRECHARGE1_A7:
563
        ignore_access("byte write", addr);
564
        return;
565
    case SH7750_SCBRR2_A7:
566
        s->scbrr2 = mem_value;
567
        return;
568
    case SH7750_SCSCR1_A7:
569
        s->scscr1 = mem_value;
570
        scscr1_changed(s);
571
        return;
572
    case SH7750_SCSMR1_A7:
573
        s->scsmr1 = mem_value;
574
        return;
575
    case SH7750_SCBRR1_A7:
576
        s->scbrr1 = mem_value;
577
        return;
578
    case SH7750_SCTDR1_A7:
579
        s->scssr1 &= ~SH7750_SCSSR1_TEND;
580
        s->sctdr1 = mem_value;
581
        return;
582
    case SH7750_SCSSR1_A7:
583
        serial1_change_scssr1(s, mem_value);
584
        return;
585
    default:
586
        error_access("byte write", addr);
587
        assert(0);
588
    }
589
}
590

    
591
static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
592
                              uint32_t mem_value)
593
{
594
    SH7750State *s = opaque;
595
    uint16_t temp;
596

    
597
    switch (addr) {
598
        /* SDRAM controller */
599
    case SH7750_SCBRR1_A7:
600
    case SH7750_SCBRR2_A7:
601
    case SH7750_BCR2_A7:
602
    case SH7750_BCR3_A7:
603
    case SH7750_RTCOR_A7:
604
    case SH7750_RTCNT_A7:
605
    case SH7750_RTCSR_A7:
606
        ignore_access("word write", addr);
607
        return;
608
        /* IO ports */
609
    case SH7750_PDTRA_A7:
610
        temp = porta_lines(s);
611
        s->pdtra = mem_value;
612
        porta_changed(s, temp);
613
        return;
614
    case SH7750_PDTRB_A7:
615
        temp = portb_lines(s);
616
        s->pdtrb = mem_value;
617
        portb_changed(s, temp);
618
        return;
619
    case SH7750_RFCR_A7:
620
        fprintf(stderr, "Write access to refresh count register\n");
621
        s->rfcr = mem_value;
622
        return;
623
    case SH7750_SCLSR2_A7:
624
        s->sclsr2 = mem_value;
625
        return;
626
    case SH7750_SCSCR2_A7:
627
        s->scscr2 = mem_value;
628
        scscr2_changed(s);
629
        return;
630
    case SH7750_SCFCR2_A7:
631
        s->scfcr2 = mem_value;
632
        return;
633
    case SH7750_SCSMR2_A7:
634
        s->scsmr2 = mem_value;
635
        return;
636
    case SH7750_GPIOIC_A7:
637
        s->gpioic = mem_value;
638
        if (mem_value != 0) {
639
            fprintf(stderr, "I/O interrupts not implemented\n");
640
            assert(0);
641
        }
642
        return;
643
    default:
644
        error_access("word write", addr);
645
        assert(0);
646
    }
647
}
648

    
649
static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
650
                              uint32_t mem_value)
651
{
652
    SH7750State *s = opaque;
653
    uint16_t temp;
654

    
655
    switch (addr) {
656
        /* SDRAM controller */
657
    case SH7750_BCR1_A7:
658
    case SH7750_BCR4_A7:
659
    case SH7750_WCR1_A7:
660
    case SH7750_WCR2_A7:
661
    case SH7750_WCR3_A7:
662
    case SH7750_MCR_A7:
663
        ignore_access("long write", addr);
664
        return;
665
        /* IO ports */
666
    case SH7750_PCTRA_A7:
667
        temp = porta_lines(s);
668
        s->pctra = mem_value;
669
        s->portdira = portdir(mem_value);
670
        s->portpullupa = portpullup(mem_value);
671
        porta_changed(s, temp);
672
        return;
673
    case SH7750_PCTRB_A7:
674
        temp = portb_lines(s);
675
        s->pctrb = mem_value;
676
        s->portdirb = portdir(mem_value);
677
        s->portpullupb = portpullup(mem_value);
678
        portb_changed(s, temp);
679
        return;
680
    case SH7750_MMUCR_A7:
681
        s->cpu->mmucr = mem_value;
682
        return;
683
    case SH7750_PTEH_A7:
684
        s->cpu->pteh = mem_value;
685
        return;
686
    case SH7750_PTEL_A7:
687
        s->cpu->ptel = mem_value;
688
        return;
689
    case SH7750_TTB_A7:
690
        s->cpu->ttb = mem_value;
691
        return;
692
    case SH7750_TEA_A7:
693
        s->cpu->tea = mem_value;
694
        return;
695
    case SH7750_TRA_A7:
696
        s->cpu->tra = mem_value & 0x000007ff;
697
        return;
698
    case SH7750_EXPEVT_A7:
699
        s->cpu->expevt = mem_value & 0x000007ff;
700
        return;
701
    case SH7750_INTEVT_A7:
702
        s->cpu->intevt = mem_value & 0x000007ff;
703
        return;
704
    case SH7750_CCR_A7:
705
        s->ccr = mem_value;
706
        return;
707
    default:
708
        error_access("long write", addr);
709
        assert(0);
710
    }
711
}
712

    
713
static CPUReadMemoryFunc *sh7750_mem_read[] = {
714
    sh7750_mem_readb,
715
    sh7750_mem_readw,
716
    sh7750_mem_readl
717
};
718

    
719
static CPUWriteMemoryFunc *sh7750_mem_write[] = {
720
    sh7750_mem_writeb,
721
    sh7750_mem_writew,
722
    sh7750_mem_writel
723
};
724

    
725
SH7750State *sh7750_init(CPUSH4State * cpu)
726
{
727
    SH7750State *s;
728
    int sh7750_io_memory;
729

    
730
    s = qemu_mallocz(sizeof(SH7750State));
731
    s->cpu = cpu;
732
    s->periph_freq = 60000000;        /* 60MHz */
733
    sh7750_io_memory = cpu_register_io_memory(0,
734
                                              sh7750_mem_read,
735
                                              sh7750_mem_write, s);
736
    cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
737
    init_serial_ports(s);
738

    
739
    tmu012_init(0x1fd80000,
740
                TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
741
                s->periph_freq);
742
    tmu012_init(0x1e100000, 0, s->periph_freq);
743
    return s;
744
}