MIPS: remove a few warnings
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5944 c046a42c-6fe2-441c-8c8c-71466251a162
Parallel port reset
Attached patch adds a reset handler to parallel port, so it gets correctregister values after a reset.
(Hervé Poussineau)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5942 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: kill a few warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5941 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: SCI improvement
This patch simply implement one register of SH4's SCI := Serial Communication Interface.
R2D evaluation board uses SCI for SPI connection. So, Linux kernel for R2D withdefault configuration causes a QEMU assertion failure when it initializes SPI driver....
SH4: kill a few warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5938 c046a42c-6fe2-441c-8c8c-71466251a162
SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).
Main purpose of this is to delete *physical = address & 0x1fffffff;at target-sh4/helper.c:449, using new mmio rule introduced by #5849This masking is a nice trick to realize P4/A7 duality of SH registers....
SH: improve the way sh7750 registers io memory (Takashi YOSHII).
Fixes to be needed for commit #5849 "Change MMIO callbacks..." hw/sh7750.c: - Divide region of CPU control registers to avoid overlapping to peripheral modules. - Delete unused var "icr", which had moved to hw/sh_intc.c....
Fix some new warnings introduced after r5022
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5933 c046a42c-6fe2-441c-8c8c-71466251a162
SH: r2d pci support (Takashi YOSHII).
This patch adds pci support to sh/r2d board.This is the first user of PCIC support I formerly sent.
PCIC actually is inside of chip with CPU core on SH7751.But, this code is written as if SH7750 and PCIC are on board....
SH: Don't subtract bases from access addresses in PCIC.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5928 c046a42c-6fe2-441c-8c8c-71466251a162
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