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1
/*
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 * QEMU NE2000 emulation
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 *
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 * Copyright (c) 2003-2004 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "pci.h"
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#include "pc.h"
27
#include "net.h"
28

    
29
/* debug NE2000 card */
30
//#define DEBUG_NE2000
31

    
32
#define MAX_ETH_FRAME_SIZE 1514
33

    
34
#define E8390_CMD        0x00  /* The command register (for all pages) */
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/* Page 0 register offsets. */
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#define EN0_CLDALO        0x01        /* Low byte of current local dma addr  RD */
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#define EN0_STARTPG        0x01        /* Starting page of ring bfr WR */
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#define EN0_CLDAHI        0x02        /* High byte of current local dma addr  RD */
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#define EN0_STOPPG        0x02        /* Ending page +1 of ring bfr WR */
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#define EN0_BOUNDARY        0x03        /* Boundary page of ring bfr RD WR */
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#define EN0_TSR                0x04        /* Transmit status reg RD */
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#define EN0_TPSR        0x04        /* Transmit starting page WR */
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#define EN0_NCR                0x05        /* Number of collision reg RD */
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#define EN0_TCNTLO        0x05        /* Low  byte of tx byte count WR */
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#define EN0_FIFO        0x06        /* FIFO RD */
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#define EN0_TCNTHI        0x06        /* High byte of tx byte count WR */
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#define EN0_ISR                0x07        /* Interrupt status reg RD WR */
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#define EN0_CRDALO        0x08        /* low byte of current remote dma address RD */
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#define EN0_RSARLO        0x08        /* Remote start address reg 0 */
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#define EN0_CRDAHI        0x09        /* high byte, current remote dma address RD */
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#define EN0_RSARHI        0x09        /* Remote start address reg 1 */
52
#define EN0_RCNTLO        0x0a        /* Remote byte count reg WR */
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#define EN0_RTL8029ID0        0x0a        /* Realtek ID byte #1 RD */
54
#define EN0_RCNTHI        0x0b        /* Remote byte count reg WR */
55
#define EN0_RTL8029ID1        0x0b        /* Realtek ID byte #2 RD */
56
#define EN0_RSR                0x0c        /* rx status reg RD */
57
#define EN0_RXCR        0x0c        /* RX configuration reg WR */
58
#define EN0_TXCR        0x0d        /* TX configuration reg WR */
59
#define EN0_COUNTER0        0x0d        /* Rcv alignment error counter RD */
60
#define EN0_DCFG        0x0e        /* Data configuration reg WR */
61
#define EN0_COUNTER1        0x0e        /* Rcv CRC error counter RD */
62
#define EN0_IMR                0x0f        /* Interrupt mask reg WR */
63
#define EN0_COUNTER2        0x0f        /* Rcv missed frame error counter RD */
64

    
65
#define EN1_PHYS        0x11
66
#define EN1_CURPAG      0x17
67
#define EN1_MULT        0x18
68

    
69
#define EN2_STARTPG        0x21        /* Starting page of ring bfr RD */
70
#define EN2_STOPPG        0x22        /* Ending page +1 of ring bfr RD */
71

    
72
#define EN3_CONFIG0        0x33
73
#define EN3_CONFIG1        0x34
74
#define EN3_CONFIG2        0x35
75
#define EN3_CONFIG3        0x36
76

    
77
/*  Register accessed at EN_CMD, the 8390 base addr.  */
78
#define E8390_STOP        0x01        /* Stop and reset the chip */
79
#define E8390_START        0x02        /* Start the chip, clear reset */
80
#define E8390_TRANS        0x04        /* Transmit a frame */
81
#define E8390_RREAD        0x08        /* Remote read */
82
#define E8390_RWRITE        0x10        /* Remote write  */
83
#define E8390_NODMA        0x20        /* Remote DMA */
84
#define E8390_PAGE0        0x00        /* Select page chip registers */
85
#define E8390_PAGE1        0x40        /* using the two high-order bits */
86
#define E8390_PAGE2        0x80        /* Page 3 is invalid. */
87

    
88
/* Bits in EN0_ISR - Interrupt status register */
89
#define ENISR_RX        0x01        /* Receiver, no error */
90
#define ENISR_TX        0x02        /* Transmitter, no error */
91
#define ENISR_RX_ERR        0x04        /* Receiver, with error */
92
#define ENISR_TX_ERR        0x08        /* Transmitter, with error */
93
#define ENISR_OVER        0x10        /* Receiver overwrote the ring */
94
#define ENISR_COUNTERS        0x20        /* Counters need emptying */
95
#define ENISR_RDC        0x40        /* remote dma complete */
96
#define ENISR_RESET        0x80        /* Reset completed */
97
#define ENISR_ALL        0x3f        /* Interrupts we will enable */
98

    
99
/* Bits in received packet status byte and EN0_RSR*/
100
#define ENRSR_RXOK        0x01        /* Received a good packet */
101
#define ENRSR_CRC        0x02        /* CRC error */
102
#define ENRSR_FAE        0x04        /* frame alignment error */
103
#define ENRSR_FO        0x08        /* FIFO overrun */
104
#define ENRSR_MPA        0x10        /* missed pkt */
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#define ENRSR_PHY        0x20        /* physical/multicast address */
106
#define ENRSR_DIS        0x40        /* receiver disable. set in monitor mode */
107
#define ENRSR_DEF        0x80        /* deferring */
108

    
109
/* Transmitted packet status, EN0_TSR. */
110
#define ENTSR_PTX 0x01        /* Packet transmitted without error */
111
#define ENTSR_ND  0x02        /* The transmit wasn't deferred. */
112
#define ENTSR_COL 0x04        /* The transmit collided at least once. */
113
#define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
114
#define ENTSR_CRS 0x10        /* The carrier sense was lost. */
115
#define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
116
#define ENTSR_CDH 0x40        /* The collision detect "heartbeat" signal was lost. */
117
#define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
118

    
119
#define NE2000_PMEM_SIZE    (32*1024)
120
#define NE2000_PMEM_START   (16*1024)
121
#define NE2000_PMEM_END     (NE2000_PMEM_SIZE+NE2000_PMEM_START)
122
#define NE2000_MEM_SIZE     NE2000_PMEM_END
123

    
124
typedef struct NE2000State {
125
    uint8_t cmd;
126
    uint32_t start;
127
    uint32_t stop;
128
    uint8_t boundary;
129
    uint8_t tsr;
130
    uint8_t tpsr;
131
    uint16_t tcnt;
132
    uint16_t rcnt;
133
    uint32_t rsar;
134
    uint8_t rsr;
135
    uint8_t rxcr;
136
    uint8_t isr;
137
    uint8_t dcfg;
138
    uint8_t imr;
139
    uint8_t phys[6]; /* mac address */
140
    uint8_t curpag;
141
    uint8_t mult[8]; /* multicast mask array */
142
    qemu_irq irq;
143
    int isa_io_base;
144
    PCIDevice *pci_dev;
145
    VLANClientState *vc;
146
    uint8_t macaddr[6];
147
    uint8_t mem[NE2000_MEM_SIZE];
148
} NE2000State;
149

    
150
static void ne2000_reset(NE2000State *s)
151
{
152
    int i;
153

    
154
    s->isr = ENISR_RESET;
155
    memcpy(s->mem, s->macaddr, 6);
156
    s->mem[14] = 0x57;
157
    s->mem[15] = 0x57;
158

    
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    /* duplicate prom data */
160
    for(i = 15;i >= 0; i--) {
161
        s->mem[2 * i] = s->mem[i];
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        s->mem[2 * i + 1] = s->mem[i];
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    }
164
}
165

    
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static void ne2000_update_irq(NE2000State *s)
167
{
168
    int isr;
169
    isr = (s->isr & s->imr) & 0x7f;
170
#if defined(DEBUG_NE2000)
171
    printf("NE2000: Set IRQ to %d (%02x %02x)\n",
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           isr ? 1 : 0, s->isr, s->imr);
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#endif
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    qemu_set_irq(s->irq, (isr != 0));
175
}
176

    
177
#define POLYNOMIAL 0x04c11db6
178

    
179
/* From FreeBSD */
180
/* XXX: optimize */
181
static int compute_mcast_idx(const uint8_t *ep)
182
{
183
    uint32_t crc;
184
    int carry, i, j;
185
    uint8_t b;
186

    
187
    crc = 0xffffffff;
188
    for (i = 0; i < 6; i++) {
189
        b = *ep++;
190
        for (j = 0; j < 8; j++) {
191
            carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
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            crc <<= 1;
193
            b >>= 1;
194
            if (carry)
195
                crc = ((crc ^ POLYNOMIAL) | carry);
196
        }
197
    }
198
    return (crc >> 26);
199
}
200

    
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static int ne2000_buffer_full(NE2000State *s)
202
{
203
    int avail, index, boundary;
204

    
205
    index = s->curpag << 8;
206
    boundary = s->boundary << 8;
207
    if (index < boundary)
208
        avail = boundary - index;
209
    else
210
        avail = (s->stop - s->start) - (index - boundary);
211
    if (avail < (MAX_ETH_FRAME_SIZE + 4))
212
        return 1;
213
    return 0;
214
}
215

    
216
static int ne2000_can_receive(void *opaque)
217
{
218
    NE2000State *s = opaque;
219

    
220
    if (s->cmd & E8390_STOP)
221
        return 1;
222
    return !ne2000_buffer_full(s);
223
}
224

    
225
#define MIN_BUF_SIZE 60
226

    
227
static void ne2000_receive(void *opaque, const uint8_t *buf, size_t size)
228
{
229
    NE2000State *s = opaque;
230
    uint8_t *p;
231
    unsigned int total_len, next, avail, len, index, mcast_idx;
232
    uint8_t buf1[60];
233
    static const uint8_t broadcast_macaddr[6] =
234
        { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
235

    
236
#if defined(DEBUG_NE2000)
237
    printf("NE2000: received len=%d\n", size);
238
#endif
239

    
240
    if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
241
        return;
242

    
243
    /* XXX: check this */
244
    if (s->rxcr & 0x10) {
245
        /* promiscuous: receive all */
246
    } else {
247
        if (!memcmp(buf,  broadcast_macaddr, 6)) {
248
            /* broadcast address */
249
            if (!(s->rxcr & 0x04))
250
                return;
251
        } else if (buf[0] & 0x01) {
252
            /* multicast */
253
            if (!(s->rxcr & 0x08))
254
                return;
255
            mcast_idx = compute_mcast_idx(buf);
256
            if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
257
                return;
258
        } else if (s->mem[0] == buf[0] &&
259
                   s->mem[2] == buf[1] &&
260
                   s->mem[4] == buf[2] &&
261
                   s->mem[6] == buf[3] &&
262
                   s->mem[8] == buf[4] &&
263
                   s->mem[10] == buf[5]) {
264
            /* match */
265
        } else {
266
            return;
267
        }
268
    }
269

    
270

    
271
    /* if too small buffer, then expand it */
272
    if (size < MIN_BUF_SIZE) {
273
        memcpy(buf1, buf, size);
274
        memset(buf1 + size, 0, MIN_BUF_SIZE - size);
275
        buf = buf1;
276
        size = MIN_BUF_SIZE;
277
    }
278

    
279
    index = s->curpag << 8;
280
    /* 4 bytes for header */
281
    total_len = size + 4;
282
    /* address for next packet (4 bytes for CRC) */
283
    next = index + ((total_len + 4 + 255) & ~0xff);
284
    if (next >= s->stop)
285
        next -= (s->stop - s->start);
286
    /* prepare packet header */
287
    p = s->mem + index;
288
    s->rsr = ENRSR_RXOK; /* receive status */
289
    /* XXX: check this */
290
    if (buf[0] & 0x01)
291
        s->rsr |= ENRSR_PHY;
292
    p[0] = s->rsr;
293
    p[1] = next >> 8;
294
    p[2] = total_len;
295
    p[3] = total_len >> 8;
296
    index += 4;
297

    
298
    /* write packet data */
299
    while (size > 0) {
300
        if (index <= s->stop)
301
            avail = s->stop - index;
302
        else
303
            avail = 0;
304
        len = size;
305
        if (len > avail)
306
            len = avail;
307
        memcpy(s->mem + index, buf, len);
308
        buf += len;
309
        index += len;
310
        if (index == s->stop)
311
            index = s->start;
312
        size -= len;
313
    }
314
    s->curpag = next >> 8;
315

    
316
    /* now we can signal we have received something */
317
    s->isr |= ENISR_RX;
318
    ne2000_update_irq(s);
319
}
320

    
321
static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
322
{
323
    NE2000State *s = opaque;
324
    int offset, page, index;
325

    
326
    addr &= 0xf;
327
#ifdef DEBUG_NE2000
328
    printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
329
#endif
330
    if (addr == E8390_CMD) {
331
        /* control register */
332
        s->cmd = val;
333
        if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
334
            s->isr &= ~ENISR_RESET;
335
            /* test specific case: zero length transfer */
336
            if ((val & (E8390_RREAD | E8390_RWRITE)) &&
337
                s->rcnt == 0) {
338
                s->isr |= ENISR_RDC;
339
                ne2000_update_irq(s);
340
            }
341
            if (val & E8390_TRANS) {
342
                index = (s->tpsr << 8);
343
                /* XXX: next 2 lines are a hack to make netware 3.11 work */
344
                if (index >= NE2000_PMEM_END)
345
                    index -= NE2000_PMEM_SIZE;
346
                /* fail safe: check range on the transmitted length  */
347
                if (index + s->tcnt <= NE2000_PMEM_END) {
348
                    qemu_send_packet(s->vc, s->mem + index, s->tcnt);
349
                }
350
                /* signal end of transfer */
351
                s->tsr = ENTSR_PTX;
352
                s->isr |= ENISR_TX;
353
                s->cmd &= ~E8390_TRANS;
354
                ne2000_update_irq(s);
355
            }
356
        }
357
    } else {
358
        page = s->cmd >> 6;
359
        offset = addr | (page << 4);
360
        switch(offset) {
361
        case EN0_STARTPG:
362
            s->start = val << 8;
363
            break;
364
        case EN0_STOPPG:
365
            s->stop = val << 8;
366
            break;
367
        case EN0_BOUNDARY:
368
            s->boundary = val;
369
            break;
370
        case EN0_IMR:
371
            s->imr = val;
372
            ne2000_update_irq(s);
373
            break;
374
        case EN0_TPSR:
375
            s->tpsr = val;
376
            break;
377
        case EN0_TCNTLO:
378
            s->tcnt = (s->tcnt & 0xff00) | val;
379
            break;
380
        case EN0_TCNTHI:
381
            s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
382
            break;
383
        case EN0_RSARLO:
384
            s->rsar = (s->rsar & 0xff00) | val;
385
            break;
386
        case EN0_RSARHI:
387
            s->rsar = (s->rsar & 0x00ff) | (val << 8);
388
            break;
389
        case EN0_RCNTLO:
390
            s->rcnt = (s->rcnt & 0xff00) | val;
391
            break;
392
        case EN0_RCNTHI:
393
            s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
394
            break;
395
        case EN0_RXCR:
396
            s->rxcr = val;
397
            break;
398
        case EN0_DCFG:
399
            s->dcfg = val;
400
            break;
401
        case EN0_ISR:
402
            s->isr &= ~(val & 0x7f);
403
            ne2000_update_irq(s);
404
            break;
405
        case EN1_PHYS ... EN1_PHYS + 5:
406
            s->phys[offset - EN1_PHYS] = val;
407
            break;
408
        case EN1_CURPAG:
409
            s->curpag = val;
410
            break;
411
        case EN1_MULT ... EN1_MULT + 7:
412
            s->mult[offset - EN1_MULT] = val;
413
            break;
414
        }
415
    }
416
}
417

    
418
static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
419
{
420
    NE2000State *s = opaque;
421
    int offset, page, ret;
422

    
423
    addr &= 0xf;
424
    if (addr == E8390_CMD) {
425
        ret = s->cmd;
426
    } else {
427
        page = s->cmd >> 6;
428
        offset = addr | (page << 4);
429
        switch(offset) {
430
        case EN0_TSR:
431
            ret = s->tsr;
432
            break;
433
        case EN0_BOUNDARY:
434
            ret = s->boundary;
435
            break;
436
        case EN0_ISR:
437
            ret = s->isr;
438
            break;
439
        case EN0_RSARLO:
440
            ret = s->rsar & 0x00ff;
441
            break;
442
        case EN0_RSARHI:
443
            ret = s->rsar >> 8;
444
            break;
445
        case EN1_PHYS ... EN1_PHYS + 5:
446
            ret = s->phys[offset - EN1_PHYS];
447
            break;
448
        case EN1_CURPAG:
449
            ret = s->curpag;
450
            break;
451
        case EN1_MULT ... EN1_MULT + 7:
452
            ret = s->mult[offset - EN1_MULT];
453
            break;
454
        case EN0_RSR:
455
            ret = s->rsr;
456
            break;
457
        case EN2_STARTPG:
458
            ret = s->start >> 8;
459
            break;
460
        case EN2_STOPPG:
461
            ret = s->stop >> 8;
462
            break;
463
        case EN0_RTL8029ID0:
464
            ret = 0x50;
465
            break;
466
        case EN0_RTL8029ID1:
467
            ret = 0x43;
468
            break;
469
        case EN3_CONFIG0:
470
            ret = 0;                /* 10baseT media */
471
            break;
472
        case EN3_CONFIG2:
473
            ret = 0x40;                /* 10baseT active */
474
            break;
475
        case EN3_CONFIG3:
476
            ret = 0x40;                /* Full duplex */
477
            break;
478
        default:
479
            ret = 0x00;
480
            break;
481
        }
482
    }
483
#ifdef DEBUG_NE2000
484
    printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
485
#endif
486
    return ret;
487
}
488

    
489
static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
490
                                     uint32_t val)
491
{
492
    if (addr < 32 ||
493
        (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
494
        s->mem[addr] = val;
495
    }
496
}
497

    
498
static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
499
                                     uint32_t val)
500
{
501
    addr &= ~1; /* XXX: check exact behaviour if not even */
502
    if (addr < 32 ||
503
        (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
504
        *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
505
    }
506
}
507

    
508
static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
509
                                     uint32_t val)
510
{
511
    addr &= ~1; /* XXX: check exact behaviour if not even */
512
    if (addr < 32 ||
513
        (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
514
        cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
515
    }
516
}
517

    
518
static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
519
{
520
    if (addr < 32 ||
521
        (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
522
        return s->mem[addr];
523
    } else {
524
        return 0xff;
525
    }
526
}
527

    
528
static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
529
{
530
    addr &= ~1; /* XXX: check exact behaviour if not even */
531
    if (addr < 32 ||
532
        (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
533
        return le16_to_cpu(*(uint16_t *)(s->mem + addr));
534
    } else {
535
        return 0xffff;
536
    }
537
}
538

    
539
static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
540
{
541
    addr &= ~1; /* XXX: check exact behaviour if not even */
542
    if (addr < 32 ||
543
        (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
544
        return le32_to_cpupu((uint32_t *)(s->mem + addr));
545
    } else {
546
        return 0xffffffff;
547
    }
548
}
549

    
550
static inline void ne2000_dma_update(NE2000State *s, int len)
551
{
552
    s->rsar += len;
553
    /* wrap */
554
    /* XXX: check what to do if rsar > stop */
555
    if (s->rsar == s->stop)
556
        s->rsar = s->start;
557

    
558
    if (s->rcnt <= len) {
559
        s->rcnt = 0;
560
        /* signal end of transfer */
561
        s->isr |= ENISR_RDC;
562
        ne2000_update_irq(s);
563
    } else {
564
        s->rcnt -= len;
565
    }
566
}
567

    
568
static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
569
{
570
    NE2000State *s = opaque;
571

    
572
#ifdef DEBUG_NE2000
573
    printf("NE2000: asic write val=0x%04x\n", val);
574
#endif
575
    if (s->rcnt == 0)
576
        return;
577
    if (s->dcfg & 0x01) {
578
        /* 16 bit access */
579
        ne2000_mem_writew(s, s->rsar, val);
580
        ne2000_dma_update(s, 2);
581
    } else {
582
        /* 8 bit access */
583
        ne2000_mem_writeb(s, s->rsar, val);
584
        ne2000_dma_update(s, 1);
585
    }
586
}
587

    
588
static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
589
{
590
    NE2000State *s = opaque;
591
    int ret;
592

    
593
    if (s->dcfg & 0x01) {
594
        /* 16 bit access */
595
        ret = ne2000_mem_readw(s, s->rsar);
596
        ne2000_dma_update(s, 2);
597
    } else {
598
        /* 8 bit access */
599
        ret = ne2000_mem_readb(s, s->rsar);
600
        ne2000_dma_update(s, 1);
601
    }
602
#ifdef DEBUG_NE2000
603
    printf("NE2000: asic read val=0x%04x\n", ret);
604
#endif
605
    return ret;
606
}
607

    
608
static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
609
{
610
    NE2000State *s = opaque;
611

    
612
#ifdef DEBUG_NE2000
613
    printf("NE2000: asic writel val=0x%04x\n", val);
614
#endif
615
    if (s->rcnt == 0)
616
        return;
617
    /* 32 bit access */
618
    ne2000_mem_writel(s, s->rsar, val);
619
    ne2000_dma_update(s, 4);
620
}
621

    
622
static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
623
{
624
    NE2000State *s = opaque;
625
    int ret;
626

    
627
    /* 32 bit access */
628
    ret = ne2000_mem_readl(s, s->rsar);
629
    ne2000_dma_update(s, 4);
630
#ifdef DEBUG_NE2000
631
    printf("NE2000: asic readl val=0x%04x\n", ret);
632
#endif
633
    return ret;
634
}
635

    
636
static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
637
{
638
    /* nothing to do (end of reset pulse) */
639
}
640

    
641
static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
642
{
643
    NE2000State *s = opaque;
644
    ne2000_reset(s);
645
    return 0;
646
}
647

    
648
static void ne2000_save(QEMUFile* f,void* opaque)
649
{
650
        NE2000State* s=(NE2000State*)opaque;
651
        uint32_t tmp;
652

    
653
        if (s->pci_dev)
654
            pci_device_save(s->pci_dev, f);
655

    
656
        qemu_put_8s(f, &s->rxcr);
657

    
658
        qemu_put_8s(f, &s->cmd);
659
        qemu_put_be32s(f, &s->start);
660
        qemu_put_be32s(f, &s->stop);
661
        qemu_put_8s(f, &s->boundary);
662
        qemu_put_8s(f, &s->tsr);
663
        qemu_put_8s(f, &s->tpsr);
664
        qemu_put_be16s(f, &s->tcnt);
665
        qemu_put_be16s(f, &s->rcnt);
666
        qemu_put_be32s(f, &s->rsar);
667
        qemu_put_8s(f, &s->rsr);
668
        qemu_put_8s(f, &s->isr);
669
        qemu_put_8s(f, &s->dcfg);
670
        qemu_put_8s(f, &s->imr);
671
        qemu_put_buffer(f, s->phys, 6);
672
        qemu_put_8s(f, &s->curpag);
673
        qemu_put_buffer(f, s->mult, 8);
674
        tmp = 0;
675
        qemu_put_be32s(f, &tmp); /* ignored, was irq */
676
        qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
677
}
678

    
679
static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
680
{
681
        NE2000State* s=(NE2000State*)opaque;
682
        int ret;
683
        uint32_t tmp;
684

    
685
        if (version_id > 3)
686
            return -EINVAL;
687

    
688
        if (s->pci_dev && version_id >= 3) {
689
            ret = pci_device_load(s->pci_dev, f);
690
            if (ret < 0)
691
                return ret;
692
        }
693

    
694
        if (version_id >= 2) {
695
            qemu_get_8s(f, &s->rxcr);
696
        } else {
697
            s->rxcr = 0x0c;
698
        }
699

    
700
        qemu_get_8s(f, &s->cmd);
701
        qemu_get_be32s(f, &s->start);
702
        qemu_get_be32s(f, &s->stop);
703
        qemu_get_8s(f, &s->boundary);
704
        qemu_get_8s(f, &s->tsr);
705
        qemu_get_8s(f, &s->tpsr);
706
        qemu_get_be16s(f, &s->tcnt);
707
        qemu_get_be16s(f, &s->rcnt);
708
        qemu_get_be32s(f, &s->rsar);
709
        qemu_get_8s(f, &s->rsr);
710
        qemu_get_8s(f, &s->isr);
711
        qemu_get_8s(f, &s->dcfg);
712
        qemu_get_8s(f, &s->imr);
713
        qemu_get_buffer(f, s->phys, 6);
714
        qemu_get_8s(f, &s->curpag);
715
        qemu_get_buffer(f, s->mult, 8);
716
        qemu_get_be32s(f, &tmp); /* ignored */
717
        qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
718

    
719
        return 0;
720
}
721

    
722
static void isa_ne2000_cleanup(VLANClientState *vc)
723
{
724
    NE2000State *s = vc->opaque;
725

    
726
    unregister_savevm("ne2000", s);
727

    
728
    isa_unassign_ioport(s->isa_io_base, 16);
729
    isa_unassign_ioport(s->isa_io_base + 0x10, 2);
730
    isa_unassign_ioport(s->isa_io_base + 0x1f, 1);
731

    
732
    qemu_free(s);
733
}
734

    
735
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd)
736
{
737
    NE2000State *s;
738

    
739
    qemu_check_nic_model(nd, "ne2k_isa");
740

    
741
    s = qemu_mallocz(sizeof(NE2000State));
742

    
743
    register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
744
    register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
745

    
746
    register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
747
    register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
748
    register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
749
    register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
750

    
751
    register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
752
    register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
753
    s->isa_io_base = base;
754
    s->irq = irq;
755
    memcpy(s->macaddr, nd->macaddr, 6);
756

    
757
    ne2000_reset(s);
758

    
759
    s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
760
                                 ne2000_can_receive, ne2000_receive, NULL,
761
                                 isa_ne2000_cleanup, s);
762

    
763
    qemu_format_nic_info_str(s->vc, s->macaddr);
764

    
765
    register_savevm("ne2000", -1, 2, ne2000_save, ne2000_load, s);
766
}
767

    
768
/***********************************************************/
769
/* PCI NE2000 definitions */
770

    
771
typedef struct PCINE2000State {
772
    PCIDevice dev;
773
    NE2000State ne2000;
774
} PCINE2000State;
775

    
776
static void ne2000_map(PCIDevice *pci_dev, int region_num,
777
                       uint32_t addr, uint32_t size, int type)
778
{
779
    PCINE2000State *d = (PCINE2000State *)pci_dev;
780
    NE2000State *s = &d->ne2000;
781

    
782
    register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
783
    register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
784

    
785
    register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
786
    register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
787
    register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
788
    register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
789
    register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
790
    register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
791

    
792
    register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
793
    register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
794
}
795

    
796
static void ne2000_cleanup(VLANClientState *vc)
797
{
798
    NE2000State *s = vc->opaque;
799

    
800
    unregister_savevm("ne2000", s);
801
}
802

    
803
static void pci_ne2000_init(PCIDevice *pci_dev)
804
{
805
    PCINE2000State *d = (PCINE2000State *)pci_dev;
806
    NE2000State *s;
807
    uint8_t *pci_conf;
808

    
809
    pci_conf = d->dev.config;
810
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
811
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029);
812
    pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
813
    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
814
    pci_conf[0x3d] = 1; // interrupt pin 0
815

    
816
    pci_register_io_region(&d->dev, 0, 0x100,
817
                           PCI_ADDRESS_SPACE_IO, ne2000_map);
818
    s = &d->ne2000;
819
    s->irq = d->dev.irq[0];
820
    s->pci_dev = (PCIDevice *)d;
821
    qdev_get_macaddr(&d->dev.qdev, s->macaddr);
822
    ne2000_reset(s);
823
    s->vc = qdev_get_vlan_client(&d->dev.qdev,
824
                                 ne2000_can_receive, ne2000_receive, NULL,
825
                                 ne2000_cleanup, s);
826

    
827
    qemu_format_nic_info_str(s->vc, s->macaddr);
828

    
829
    register_savevm("ne2000", -1, 3, ne2000_save, ne2000_load, s);
830
}
831

    
832
static void ne2000_register_devices(void)
833
{
834
    pci_qdev_register("ne2k_pci", sizeof(PCINE2000State), pci_ne2000_init);
835
}
836

    
837
device_init(ne2000_register_devices)