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/**
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 * QEMU RTL8139 emulation
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 *
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 * Copyright (c) 2006 Igor Kovalenko
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 * Modifications:
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 *  2006-Jan-28  Mark Malakanov :   TSAD and CSCR implementation (for Windows driver)
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 *
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 *  2006-Apr-28  Juergen Lock   :   EEPROM emulation changes for FreeBSD driver
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 *                                  HW revision ID changes for FreeBSD driver
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 *
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 *  2006-Jul-01  Igor Kovalenko :   Implemented loopback mode for FreeBSD driver
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 *                                  Corrected packet transfer reassembly routine for 8139C+ mode
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 *                                  Rearranged debugging print statements
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 *                                  Implemented PCI timer interrupt (disabled by default)
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 *                                  Implemented Tally Counters, increased VM load/save version
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 *                                  Implemented IP/TCP/UDP checksum task offloading
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 *
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 *  2006-Jul-04  Igor Kovalenko :   Implemented TCP segmentation offloading
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 *                                  Fixed MTU=1500 for produced ethernet frames
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 *
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 *  2006-Jul-09  Igor Kovalenko :   Fixed TCP header length calculation while processing
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 *                                  segmentation offloading
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 *                                  Removed slirp.h dependency
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 *                                  Added rx/tx buffer reset when enabling rx/tx operation
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 */
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#include "hw.h"
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#include "pci.h"
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#include "qemu-timer.h"
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#include "net.h"
50

    
51
/* debug RTL8139 card */
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//#define DEBUG_RTL8139 1
53

    
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#define PCI_FREQUENCY 33000000L
55

    
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/* debug RTL8139 card C+ mode only */
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//#define DEBUG_RTL8139CP 1
58

    
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/* Calculate CRCs properly on Rx packets */
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#define RTL8139_CALCULATE_RXCRC 1
61

    
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/* Uncomment to enable on-board timer interrupts */
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//#define RTL8139_ONBOARD_TIMER 1
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#if defined(RTL8139_CALCULATE_RXCRC)
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/* For crc32 */
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#include <zlib.h>
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#endif
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#define SET_MASKED(input, mask, curr) \
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    ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
72

    
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/* arg % size for size which is a power of 2 */
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#define MOD2(input, size) \
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    ( ( input ) & ( size - 1 )  )
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#if defined (DEBUG_RTL8139)
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#  define DEBUG_PRINT(x) do { printf x ; } while (0)
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#else
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#  define DEBUG_PRINT(x)
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#endif
82

    
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/* Symbolic offsets to registers. */
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enum RTL8139_registers {
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    MAC0 = 0,        /* Ethernet hardware address. */
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    MAR0 = 8,        /* Multicast filter. */
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    TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
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                     /* Dump Tally Conter control register(64bit). C+ mode only */
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    TxAddr0 = 0x20,  /* Tx descriptors (also four 32bit). */
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    RxBuf = 0x30,
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    ChipCmd = 0x37,
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    RxBufPtr = 0x38,
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    RxBufAddr = 0x3A,
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    IntrMask = 0x3C,
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    IntrStatus = 0x3E,
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    TxConfig = 0x40,
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    RxConfig = 0x44,
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    Timer = 0x48,        /* A general-purpose counter. */
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    RxMissed = 0x4C,    /* 24 bits valid, write clears. */
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    Cfg9346 = 0x50,
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    Config0 = 0x51,
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    Config1 = 0x52,
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    FlashReg = 0x54,
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    MediaStatus = 0x58,
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    Config3 = 0x59,
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    Config4 = 0x5A,        /* absent on RTL-8139A */
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    HltClk = 0x5B,
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    MultiIntr = 0x5C,
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    PCIRevisionID = 0x5E,
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    TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
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    BasicModeCtrl = 0x62,
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    BasicModeStatus = 0x64,
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    NWayAdvert = 0x66,
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    NWayLPAR = 0x68,
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    NWayExpansion = 0x6A,
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    /* Undocumented registers, but required for proper operation. */
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    FIFOTMS = 0x70,        /* FIFO Control and test. */
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    CSCR = 0x74,        /* Chip Status and Configuration Register. */
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    PARA78 = 0x78,
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    PARA7c = 0x7c,        /* Magic transceiver parameter register. */
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    Config5 = 0xD8,        /* absent on RTL-8139A */
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    /* C+ mode */
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    TxPoll        = 0xD9,    /* Tell chip to check Tx descriptors for work */
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    RxMaxSize    = 0xDA, /* Max size of an Rx packet (8169 only) */
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    CpCmd        = 0xE0, /* C+ Command register (C+ mode only) */
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    IntrMitigate    = 0xE2,    /* rx/tx interrupt mitigation control */
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    RxRingAddrLO    = 0xE4, /* 64-bit start addr of Rx ring */
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    RxRingAddrHI    = 0xE8, /* 64-bit start addr of Rx ring */
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    TxThresh    = 0xEC, /* Early Tx threshold */
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};
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enum ClearBitMasks {
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    MultiIntrClear = 0xF000,
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    ChipCmdClear = 0xE2,
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    Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
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};
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enum ChipCmdBits {
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    CmdReset = 0x10,
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    CmdRxEnb = 0x08,
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    CmdTxEnb = 0x04,
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    RxBufEmpty = 0x01,
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};
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/* C+ mode */
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enum CplusCmdBits {
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    CPlusRxVLAN   = 0x0040, /* enable receive VLAN detagging */
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    CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
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    CPlusRxEnb    = 0x0002,
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    CPlusTxEnb    = 0x0001,
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};
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/* Interrupt register bits, using my own meaningful names. */
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enum IntrStatusBits {
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    PCIErr = 0x8000,
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    PCSTimeout = 0x4000,
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    RxFIFOOver = 0x40,
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    RxUnderrun = 0x20,
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    RxOverflow = 0x10,
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    TxErr = 0x08,
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    TxOK = 0x04,
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    RxErr = 0x02,
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    RxOK = 0x01,
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    RxAckBits = RxFIFOOver | RxOverflow | RxOK,
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};
167

    
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enum TxStatusBits {
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    TxHostOwns = 0x2000,
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    TxUnderrun = 0x4000,
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    TxStatOK = 0x8000,
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    TxOutOfWindow = 0x20000000,
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    TxAborted = 0x40000000,
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    TxCarrierLost = 0x80000000,
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};
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enum RxStatusBits {
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    RxMulticast = 0x8000,
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    RxPhysical = 0x4000,
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    RxBroadcast = 0x2000,
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    RxBadSymbol = 0x0020,
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    RxRunt = 0x0010,
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    RxTooLong = 0x0008,
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    RxCRCErr = 0x0004,
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    RxBadAlign = 0x0002,
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    RxStatusOK = 0x0001,
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};
187

    
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/* Bits in RxConfig. */
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enum rx_mode_bits {
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    AcceptErr = 0x20,
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    AcceptRunt = 0x10,
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    AcceptBroadcast = 0x08,
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    AcceptMulticast = 0x04,
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    AcceptMyPhys = 0x02,
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    AcceptAllPhys = 0x01,
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};
197

    
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/* Bits in TxConfig. */
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enum tx_config_bits {
200

    
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        /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
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        TxIFGShift = 24,
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        TxIFG84 = (0 << TxIFGShift),    /* 8.4us / 840ns (10 / 100Mbps) */
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        TxIFG88 = (1 << TxIFGShift),    /* 8.8us / 880ns (10 / 100Mbps) */
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        TxIFG92 = (2 << TxIFGShift),    /* 9.2us / 920ns (10 / 100Mbps) */
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        TxIFG96 = (3 << TxIFGShift),    /* 9.6us / 960ns (10 / 100Mbps) */
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    TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
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    TxCRC = (1 << 16),    /* DISABLE appending CRC to end of Tx packets */
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    TxClearAbt = (1 << 0),    /* Clear abort (WO) */
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    TxDMAShift = 8,        /* DMA burst value (0-7) is shifted this many bits */
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    TxRetryShift = 4,    /* TXRR value (0-15) is shifted this many bits */
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    TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
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};
216

    
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/* Transmit Status of All Descriptors (TSAD) Register */
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enum TSAD_bits {
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 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
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 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
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 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
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 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
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 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
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 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
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 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
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 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
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 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
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 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
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 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
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 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
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 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
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 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
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 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
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 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
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};
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/* Bits in Config1 */
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enum Config1Bits {
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    Cfg1_PM_Enable = 0x01,
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    Cfg1_VPD_Enable = 0x02,
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    Cfg1_PIO = 0x04,
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    Cfg1_MMIO = 0x08,
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    LWAKE = 0x10,        /* not on 8139, 8139A */
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    Cfg1_Driver_Load = 0x20,
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    Cfg1_LED0 = 0x40,
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    Cfg1_LED1 = 0x80,
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    SLEEP = (1 << 1),    /* only on 8139, 8139A */
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    PWRDN = (1 << 0),    /* only on 8139, 8139A */
251
};
252

    
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/* Bits in Config3 */
254
enum Config3Bits {
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    Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */
256
    Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
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    Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
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    Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */
259
    Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */
260
    Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
261
    Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */
262
    Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
263
};
264

    
265
/* Bits in Config4 */
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enum Config4Bits {
267
    LWPTN = (1 << 2),    /* not on 8139, 8139A */
268
};
269

    
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/* Bits in Config5 */
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enum Config5Bits {
272
    Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */
273
    Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */
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    Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */
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    Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
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    Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */
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    Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */
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    Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */
279
};
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281
enum RxConfigBits {
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    /* rx fifo threshold */
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    RxCfgFIFOShift = 13,
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    RxCfgFIFONone = (7 << RxCfgFIFOShift),
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    /* Max DMA burst */
287
    RxCfgDMAShift = 8,
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    RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
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    /* rx ring buffer length */
291
    RxCfgRcv8K = 0,
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    RxCfgRcv16K = (1 << 11),
293
    RxCfgRcv32K = (1 << 12),
294
    RxCfgRcv64K = (1 << 11) | (1 << 12),
295

    
296
    /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
297
    RxNoWrap = (1 << 7),
298
};
299

    
300
/* Twister tuning parameters from RealTek.
301
   Completely undocumented, but required to tune bad links on some boards. */
302
/*
303
enum CSCRBits {
304
    CSCR_LinkOKBit = 0x0400,
305
    CSCR_LinkChangeBit = 0x0800,
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    CSCR_LinkStatusBits = 0x0f000,
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    CSCR_LinkDownOffCmd = 0x003c0,
308
    CSCR_LinkDownCmd = 0x0f3c0,
309
*/
310
enum CSCRBits {
311
    CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
312
    CSCR_LD  = 1<<9,  /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
313
    CSCR_HEART_BIT = 1<<8,  /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
314
    CSCR_JBEN = 1<<7,  /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
315
    CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
316
    CSCR_F_Connect  = 1<<5,  /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
317
    CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
318
    CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
319
    CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
320
};
321

    
322
enum Cfg9346Bits {
323
    Cfg9346_Lock = 0x00,
324
    Cfg9346_Unlock = 0xC0,
325
};
326

    
327
typedef enum {
328
    CH_8139 = 0,
329
    CH_8139_K,
330
    CH_8139A,
331
    CH_8139A_G,
332
    CH_8139B,
333
    CH_8130,
334
    CH_8139C,
335
    CH_8100,
336
    CH_8100B_8139D,
337
    CH_8101,
338
} chip_t;
339

    
340
enum chip_flags {
341
    HasHltClk = (1 << 0),
342
    HasLWake = (1 << 1),
343
};
344

    
345
#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
346
    (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
347
#define HW_REVID_MASK    HW_REVID(1, 1, 1, 1, 1, 1, 1)
348

    
349
#define RTL8139_PCI_REVID_8139      0x10
350
#define RTL8139_PCI_REVID_8139CPLUS 0x20
351

    
352
#define RTL8139_PCI_REVID           RTL8139_PCI_REVID_8139CPLUS
353

    
354
/* Size is 64 * 16bit words */
355
#define EEPROM_9346_ADDR_BITS 6
356
#define EEPROM_9346_SIZE  (1 << EEPROM_9346_ADDR_BITS)
357
#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
358

    
359
enum Chip9346Operation
360
{
361
    Chip9346_op_mask = 0xc0,          /* 10 zzzzzz */
362
    Chip9346_op_read = 0x80,          /* 10 AAAAAA */
363
    Chip9346_op_write = 0x40,         /* 01 AAAAAA D(15)..D(0) */
364
    Chip9346_op_ext_mask = 0xf0,      /* 11 zzzzzz */
365
    Chip9346_op_write_enable = 0x30,  /* 00 11zzzz */
366
    Chip9346_op_write_all = 0x10,     /* 00 01zzzz */
367
    Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
368
};
369

    
370
enum Chip9346Mode
371
{
372
    Chip9346_none = 0,
373
    Chip9346_enter_command_mode,
374
    Chip9346_read_command,
375
    Chip9346_data_read,      /* from output register */
376
    Chip9346_data_write,     /* to input register, then to contents at specified address */
377
    Chip9346_data_write_all, /* to input register, then filling contents */
378
};
379

    
380
typedef struct EEprom9346
381
{
382
    uint16_t contents[EEPROM_9346_SIZE];
383
    int      mode;
384
    uint32_t tick;
385
    uint8_t  address;
386
    uint16_t input;
387
    uint16_t output;
388

    
389
    uint8_t eecs;
390
    uint8_t eesk;
391
    uint8_t eedi;
392
    uint8_t eedo;
393
} EEprom9346;
394

    
395
typedef struct RTL8139TallyCounters
396
{
397
    /* Tally counters */
398
    uint64_t   TxOk;
399
    uint64_t   RxOk;
400
    uint64_t   TxERR;
401
    uint32_t   RxERR;
402
    uint16_t   MissPkt;
403
    uint16_t   FAE;
404
    uint32_t   Tx1Col;
405
    uint32_t   TxMCol;
406
    uint64_t   RxOkPhy;
407
    uint64_t   RxOkBrd;
408
    uint32_t   RxOkMul;
409
    uint16_t   TxAbt;
410
    uint16_t   TxUndrn;
411
} RTL8139TallyCounters;
412

    
413
/* Clears all tally counters */
414
static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
415

    
416
/* Writes tally counters to specified physical memory address */
417
static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
418

    
419
/* Loads values of tally counters from VM state file */
420
static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters);
421

    
422
/* Saves values of tally counters to VM state file */
423
static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters);
424

    
425
typedef struct RTL8139State {
426
    uint8_t phys[8]; /* mac address */
427
    uint8_t mult[8]; /* multicast mask array */
428

    
429
    uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
430
    uint32_t TxAddr[4];   /* TxAddr0 */
431
    uint32_t RxBuf;       /* Receive buffer */
432
    uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
433
    uint32_t RxBufPtr;
434
    uint32_t RxBufAddr;
435

    
436
    uint16_t IntrStatus;
437
    uint16_t IntrMask;
438

    
439
    uint32_t TxConfig;
440
    uint32_t RxConfig;
441
    uint32_t RxMissed;
442

    
443
    uint16_t CSCR;
444

    
445
    uint8_t  Cfg9346;
446
    uint8_t  Config0;
447
    uint8_t  Config1;
448
    uint8_t  Config3;
449
    uint8_t  Config4;
450
    uint8_t  Config5;
451

    
452
    uint8_t  clock_enabled;
453
    uint8_t  bChipCmdState;
454

    
455
    uint16_t MultiIntr;
456

    
457
    uint16_t BasicModeCtrl;
458
    uint16_t BasicModeStatus;
459
    uint16_t NWayAdvert;
460
    uint16_t NWayLPAR;
461
    uint16_t NWayExpansion;
462

    
463
    uint16_t CpCmd;
464
    uint8_t  TxThresh;
465

    
466
    PCIDevice *pci_dev;
467
    VLANClientState *vc;
468
    uint8_t macaddr[6];
469
    int rtl8139_mmio_io_addr;
470

    
471
    /* C ring mode */
472
    uint32_t   currTxDesc;
473

    
474
    /* C+ mode */
475
    uint32_t   cplus_enabled;
476

    
477
    uint32_t   currCPlusRxDesc;
478
    uint32_t   currCPlusTxDesc;
479

    
480
    uint32_t   RxRingAddrLO;
481
    uint32_t   RxRingAddrHI;
482

    
483
    EEprom9346 eeprom;
484

    
485
    uint32_t   TCTR;
486
    uint32_t   TimerInt;
487
    int64_t    TCTR_base;
488

    
489
    /* Tally counters */
490
    RTL8139TallyCounters tally_counters;
491

    
492
    /* Non-persistent data */
493
    uint8_t   *cplus_txbuffer;
494
    int        cplus_txbuffer_len;
495
    int        cplus_txbuffer_offset;
496

    
497
    /* PCI interrupt timer */
498
    QEMUTimer *timer;
499

    
500
} RTL8139State;
501

    
502
static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
503
{
504
    DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
505

    
506
    switch (command & Chip9346_op_mask)
507
    {
508
        case Chip9346_op_read:
509
        {
510
            eeprom->address = command & EEPROM_9346_ADDR_MASK;
511
            eeprom->output = eeprom->contents[eeprom->address];
512
            eeprom->eedo = 0;
513
            eeprom->tick = 0;
514
            eeprom->mode = Chip9346_data_read;
515
            DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
516
                   eeprom->address, eeprom->output));
517
        }
518
        break;
519

    
520
        case Chip9346_op_write:
521
        {
522
            eeprom->address = command & EEPROM_9346_ADDR_MASK;
523
            eeprom->input = 0;
524
            eeprom->tick = 0;
525
            eeprom->mode = Chip9346_none; /* Chip9346_data_write */
526
            DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
527
                   eeprom->address));
528
        }
529
        break;
530
        default:
531
            eeprom->mode = Chip9346_none;
532
            switch (command & Chip9346_op_ext_mask)
533
            {
534
                case Chip9346_op_write_enable:
535
                    DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
536
                    break;
537
                case Chip9346_op_write_all:
538
                    DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
539
                    break;
540
                case Chip9346_op_write_disable:
541
                    DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
542
                    break;
543
            }
544
            break;
545
    }
546
}
547

    
548
static void prom9346_shift_clock(EEprom9346 *eeprom)
549
{
550
    int bit = eeprom->eedi?1:0;
551

    
552
    ++ eeprom->tick;
553

    
554
    DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
555

    
556
    switch (eeprom->mode)
557
    {
558
        case Chip9346_enter_command_mode:
559
            if (bit)
560
            {
561
                eeprom->mode = Chip9346_read_command;
562
                eeprom->tick = 0;
563
                eeprom->input = 0;
564
                DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
565
            }
566
            break;
567

    
568
        case Chip9346_read_command:
569
            eeprom->input = (eeprom->input << 1) | (bit & 1);
570
            if (eeprom->tick == 8)
571
            {
572
                prom9346_decode_command(eeprom, eeprom->input & 0xff);
573
            }
574
            break;
575

    
576
        case Chip9346_data_read:
577
            eeprom->eedo = (eeprom->output & 0x8000)?1:0;
578
            eeprom->output <<= 1;
579
            if (eeprom->tick == 16)
580
            {
581
#if 1
582
        // the FreeBSD drivers (rl and re) don't explicitly toggle
583
        // CS between reads (or does setting Cfg9346 to 0 count too?),
584
        // so we need to enter wait-for-command state here
585
                eeprom->mode = Chip9346_enter_command_mode;
586
                eeprom->input = 0;
587
                eeprom->tick = 0;
588

    
589
                DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
590
#else
591
        // original behaviour
592
                ++eeprom->address;
593
                eeprom->address &= EEPROM_9346_ADDR_MASK;
594
                eeprom->output = eeprom->contents[eeprom->address];
595
                eeprom->tick = 0;
596

    
597
                DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
598
                       eeprom->address, eeprom->output));
599
#endif
600
            }
601
            break;
602

    
603
        case Chip9346_data_write:
604
            eeprom->input = (eeprom->input << 1) | (bit & 1);
605
            if (eeprom->tick == 16)
606
            {
607
                DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
608
                       eeprom->address, eeprom->input));
609

    
610
                eeprom->contents[eeprom->address] = eeprom->input;
611
                eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
612
                eeprom->tick = 0;
613
                eeprom->input = 0;
614
            }
615
            break;
616

    
617
        case Chip9346_data_write_all:
618
            eeprom->input = (eeprom->input << 1) | (bit & 1);
619
            if (eeprom->tick == 16)
620
            {
621
                int i;
622
                for (i = 0; i < EEPROM_9346_SIZE; i++)
623
                {
624
                    eeprom->contents[i] = eeprom->input;
625
                }
626
                DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
627
                       eeprom->input));
628

    
629
                eeprom->mode = Chip9346_enter_command_mode;
630
                eeprom->tick = 0;
631
                eeprom->input = 0;
632
            }
633
            break;
634

    
635
        default:
636
            break;
637
    }
638
}
639

    
640
static int prom9346_get_wire(RTL8139State *s)
641
{
642
    EEprom9346 *eeprom = &s->eeprom;
643
    if (!eeprom->eecs)
644
        return 0;
645

    
646
    return eeprom->eedo;
647
}
648

    
649
/* FIXME: This should be merged into/replaced by eeprom93xx.c.  */
650
static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
651
{
652
    EEprom9346 *eeprom = &s->eeprom;
653
    uint8_t old_eecs = eeprom->eecs;
654
    uint8_t old_eesk = eeprom->eesk;
655

    
656
    eeprom->eecs = eecs;
657
    eeprom->eesk = eesk;
658
    eeprom->eedi = eedi;
659

    
660
    DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
661
                 eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
662

    
663
    if (!old_eecs && eecs)
664
    {
665
        /* Synchronize start */
666
        eeprom->tick = 0;
667
        eeprom->input = 0;
668
        eeprom->output = 0;
669
        eeprom->mode = Chip9346_enter_command_mode;
670

    
671
        DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
672
    }
673

    
674
    if (!eecs)
675
    {
676
        DEBUG_PRINT(("=== eeprom: end access\n"));
677
        return;
678
    }
679

    
680
    if (!old_eesk && eesk)
681
    {
682
        /* SK front rules */
683
        prom9346_shift_clock(eeprom);
684
    }
685
}
686

    
687
static void rtl8139_update_irq(RTL8139State *s)
688
{
689
    int isr;
690
    isr = (s->IntrStatus & s->IntrMask) & 0xffff;
691

    
692
    DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
693
       isr ? 1 : 0, s->IntrStatus, s->IntrMask));
694

    
695
    qemu_set_irq(s->pci_dev->irq[0], (isr != 0));
696
}
697

    
698
#define POLYNOMIAL 0x04c11db6
699

    
700
/* From FreeBSD */
701
/* XXX: optimize */
702
static int compute_mcast_idx(const uint8_t *ep)
703
{
704
    uint32_t crc;
705
    int carry, i, j;
706
    uint8_t b;
707

    
708
    crc = 0xffffffff;
709
    for (i = 0; i < 6; i++) {
710
        b = *ep++;
711
        for (j = 0; j < 8; j++) {
712
            carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
713
            crc <<= 1;
714
            b >>= 1;
715
            if (carry)
716
                crc = ((crc ^ POLYNOMIAL) | carry);
717
        }
718
    }
719
    return (crc >> 26);
720
}
721

    
722
static int rtl8139_RxWrap(RTL8139State *s)
723
{
724
    /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
725
    return (s->RxConfig & (1 << 7));
726
}
727

    
728
static int rtl8139_receiver_enabled(RTL8139State *s)
729
{
730
    return s->bChipCmdState & CmdRxEnb;
731
}
732

    
733
static int rtl8139_transmitter_enabled(RTL8139State *s)
734
{
735
    return s->bChipCmdState & CmdTxEnb;
736
}
737

    
738
static int rtl8139_cp_receiver_enabled(RTL8139State *s)
739
{
740
    return s->CpCmd & CPlusRxEnb;
741
}
742

    
743
static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
744
{
745
    return s->CpCmd & CPlusTxEnb;
746
}
747

    
748
static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
749
{
750
    if (s->RxBufAddr + size > s->RxBufferSize)
751
    {
752
        int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
753

    
754
        /* write packet data */
755
        if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
756
        {
757
            DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
758

    
759
            if (size > wrapped)
760
            {
761
                cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
762
                                           buf, size-wrapped );
763
            }
764

    
765
            /* reset buffer pointer */
766
            s->RxBufAddr = 0;
767

    
768
            cpu_physical_memory_write( s->RxBuf + s->RxBufAddr,
769
                                       buf + (size-wrapped), wrapped );
770

    
771
            s->RxBufAddr = wrapped;
772

    
773
            return;
774
        }
775
    }
776

    
777
    /* non-wrapping path or overwrapping enabled */
778
    cpu_physical_memory_write( s->RxBuf + s->RxBufAddr, buf, size );
779

    
780
    s->RxBufAddr += size;
781
}
782

    
783
#define MIN_BUF_SIZE 60
784
static inline target_phys_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
785
{
786
#if TARGET_PHYS_ADDR_BITS > 32
787
    return low | ((target_phys_addr_t)high << 32);
788
#else
789
    return low;
790
#endif
791
}
792

    
793
static int rtl8139_can_receive(void *opaque)
794
{
795
    RTL8139State *s = opaque;
796
    int avail;
797

    
798
    /* Receive (drop) packets if card is disabled.  */
799
    if (!s->clock_enabled)
800
      return 1;
801
    if (!rtl8139_receiver_enabled(s))
802
      return 1;
803

    
804
    if (rtl8139_cp_receiver_enabled(s)) {
805
        /* ??? Flow control not implemented in c+ mode.
806
           This is a hack to work around slirp deficiencies anyway.  */
807
        return 1;
808
    } else {
809
        avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
810
                     s->RxBufferSize);
811
        return (avail == 0 || avail >= 1514);
812
    }
813
}
814

    
815
static void rtl8139_do_receive(void *opaque, const uint8_t *buf, int size, int do_interrupt)
816
{
817
    RTL8139State *s = opaque;
818

    
819
    uint32_t packet_header = 0;
820

    
821
    uint8_t buf1[60];
822
    static const uint8_t broadcast_macaddr[6] =
823
        { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
824

    
825
    DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
826

    
827
    /* test if board clock is stopped */
828
    if (!s->clock_enabled)
829
    {
830
        DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
831
        return;
832
    }
833

    
834
    /* first check if receiver is enabled */
835

    
836
    if (!rtl8139_receiver_enabled(s))
837
    {
838
        DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
839
        return;
840
    }
841

    
842
    /* XXX: check this */
843
    if (s->RxConfig & AcceptAllPhys) {
844
        /* promiscuous: receive all */
845
        DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
846

    
847
    } else {
848
        if (!memcmp(buf,  broadcast_macaddr, 6)) {
849
            /* broadcast address */
850
            if (!(s->RxConfig & AcceptBroadcast))
851
            {
852
                DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
853

    
854
                /* update tally counter */
855
                ++s->tally_counters.RxERR;
856

    
857
                return;
858
            }
859

    
860
            packet_header |= RxBroadcast;
861

    
862
            DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
863

    
864
            /* update tally counter */
865
            ++s->tally_counters.RxOkBrd;
866

    
867
        } else if (buf[0] & 0x01) {
868
            /* multicast */
869
            if (!(s->RxConfig & AcceptMulticast))
870
            {
871
                DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
872

    
873
                /* update tally counter */
874
                ++s->tally_counters.RxERR;
875

    
876
                return;
877
            }
878

    
879
            int mcast_idx = compute_mcast_idx(buf);
880

    
881
            if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
882
            {
883
                DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
884

    
885
                /* update tally counter */
886
                ++s->tally_counters.RxERR;
887

    
888
                return;
889
            }
890

    
891
            packet_header |= RxMulticast;
892

    
893
            DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
894

    
895
            /* update tally counter */
896
            ++s->tally_counters.RxOkMul;
897

    
898
        } else if (s->phys[0] == buf[0] &&
899
                   s->phys[1] == buf[1] &&
900
                   s->phys[2] == buf[2] &&
901
                   s->phys[3] == buf[3] &&
902
                   s->phys[4] == buf[4] &&
903
                   s->phys[5] == buf[5]) {
904
            /* match */
905
            if (!(s->RxConfig & AcceptMyPhys))
906
            {
907
                DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
908

    
909
                /* update tally counter */
910
                ++s->tally_counters.RxERR;
911

    
912
                return;
913
            }
914

    
915
            packet_header |= RxPhysical;
916

    
917
            DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
918

    
919
            /* update tally counter */
920
            ++s->tally_counters.RxOkPhy;
921

    
922
        } else {
923

    
924
            DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
925

    
926
            /* update tally counter */
927
            ++s->tally_counters.RxERR;
928

    
929
            return;
930
        }
931
    }
932

    
933
    /* if too small buffer, then expand it */
934
    if (size < MIN_BUF_SIZE) {
935
        memcpy(buf1, buf, size);
936
        memset(buf1 + size, 0, MIN_BUF_SIZE - size);
937
        buf = buf1;
938
        size = MIN_BUF_SIZE;
939
    }
940

    
941
    if (rtl8139_cp_receiver_enabled(s))
942
    {
943
        DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
944

    
945
        /* begin C+ receiver mode */
946

    
947
/* w0 ownership flag */
948
#define CP_RX_OWN (1<<31)
949
/* w0 end of ring flag */
950
#define CP_RX_EOR (1<<30)
951
/* w0 bits 0...12 : buffer size */
952
#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
953
/* w1 tag available flag */
954
#define CP_RX_TAVA (1<<16)
955
/* w1 bits 0...15 : VLAN tag */
956
#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
957
/* w2 low  32bit of Rx buffer ptr */
958
/* w3 high 32bit of Rx buffer ptr */
959

    
960
        int descriptor = s->currCPlusRxDesc;
961
        target_phys_addr_t cplus_rx_ring_desc;
962

    
963
        cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
964
        cplus_rx_ring_desc += 16 * descriptor;
965

    
966
        DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
967
               descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
968

    
969
        uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
970

    
971
        cpu_physical_memory_read(cplus_rx_ring_desc,    (uint8_t *)&val, 4);
972
        rxdw0 = le32_to_cpu(val);
973
        cpu_physical_memory_read(cplus_rx_ring_desc+4,  (uint8_t *)&val, 4);
974
        rxdw1 = le32_to_cpu(val);
975
        cpu_physical_memory_read(cplus_rx_ring_desc+8,  (uint8_t *)&val, 4);
976
        rxbufLO = le32_to_cpu(val);
977
        cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
978
        rxbufHI = le32_to_cpu(val);
979

    
980
        DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
981
               descriptor,
982
               rxdw0, rxdw1, rxbufLO, rxbufHI));
983

    
984
        if (!(rxdw0 & CP_RX_OWN))
985
        {
986
            DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
987

    
988
            s->IntrStatus |= RxOverflow;
989
            ++s->RxMissed;
990

    
991
            /* update tally counter */
992
            ++s->tally_counters.RxERR;
993
            ++s->tally_counters.MissPkt;
994

    
995
            rtl8139_update_irq(s);
996
            return;
997
        }
998

    
999
        uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1000

    
1001
        /* TODO: scatter the packet over available receive ring descriptors space */
1002

    
1003
        if (size+4 > rx_space)
1004
        {
1005
            DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
1006
                   descriptor, rx_space, size));
1007

    
1008
            s->IntrStatus |= RxOverflow;
1009
            ++s->RxMissed;
1010

    
1011
            /* update tally counter */
1012
            ++s->tally_counters.RxERR;
1013
            ++s->tally_counters.MissPkt;
1014

    
1015
            rtl8139_update_irq(s);
1016
            return;
1017
        }
1018

    
1019
        target_phys_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1020

    
1021
        /* receive/copy to target memory */
1022
        cpu_physical_memory_write( rx_addr, buf, size );
1023

    
1024
        if (s->CpCmd & CPlusRxChkSum)
1025
        {
1026
            /* do some packet checksumming */
1027
        }
1028

    
1029
        /* write checksum */
1030
#if defined (RTL8139_CALCULATE_RXCRC)
1031
        val = cpu_to_le32(crc32(0, buf, size));
1032
#else
1033
        val = 0;
1034
#endif
1035
        cpu_physical_memory_write( rx_addr+size, (uint8_t *)&val, 4);
1036

    
1037
/* first segment of received packet flag */
1038
#define CP_RX_STATUS_FS (1<<29)
1039
/* last segment of received packet flag */
1040
#define CP_RX_STATUS_LS (1<<28)
1041
/* multicast packet flag */
1042
#define CP_RX_STATUS_MAR (1<<26)
1043
/* physical-matching packet flag */
1044
#define CP_RX_STATUS_PAM (1<<25)
1045
/* broadcast packet flag */
1046
#define CP_RX_STATUS_BAR (1<<24)
1047
/* runt packet flag */
1048
#define CP_RX_STATUS_RUNT (1<<19)
1049
/* crc error flag */
1050
#define CP_RX_STATUS_CRC (1<<18)
1051
/* IP checksum error flag */
1052
#define CP_RX_STATUS_IPF (1<<15)
1053
/* UDP checksum error flag */
1054
#define CP_RX_STATUS_UDPF (1<<14)
1055
/* TCP checksum error flag */
1056
#define CP_RX_STATUS_TCPF (1<<13)
1057

    
1058
        /* transfer ownership to target */
1059
        rxdw0 &= ~CP_RX_OWN;
1060

    
1061
        /* set first segment bit */
1062
        rxdw0 |= CP_RX_STATUS_FS;
1063

    
1064
        /* set last segment bit */
1065
        rxdw0 |= CP_RX_STATUS_LS;
1066

    
1067
        /* set received packet type flags */
1068
        if (packet_header & RxBroadcast)
1069
            rxdw0 |= CP_RX_STATUS_BAR;
1070
        if (packet_header & RxMulticast)
1071
            rxdw0 |= CP_RX_STATUS_MAR;
1072
        if (packet_header & RxPhysical)
1073
            rxdw0 |= CP_RX_STATUS_PAM;
1074

    
1075
        /* set received size */
1076
        rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1077
        rxdw0 |= (size+4);
1078

    
1079
        /* reset VLAN tag flag */
1080
        rxdw1 &= ~CP_RX_TAVA;
1081

    
1082
        /* update ring data */
1083
        val = cpu_to_le32(rxdw0);
1084
        cpu_physical_memory_write(cplus_rx_ring_desc,    (uint8_t *)&val, 4);
1085
        val = cpu_to_le32(rxdw1);
1086
        cpu_physical_memory_write(cplus_rx_ring_desc+4,  (uint8_t *)&val, 4);
1087

    
1088
        /* update tally counter */
1089
        ++s->tally_counters.RxOk;
1090

    
1091
        /* seek to next Rx descriptor */
1092
        if (rxdw0 & CP_RX_EOR)
1093
        {
1094
            s->currCPlusRxDesc = 0;
1095
        }
1096
        else
1097
        {
1098
            ++s->currCPlusRxDesc;
1099
        }
1100

    
1101
        DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
1102

    
1103
    }
1104
    else
1105
    {
1106
        DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
1107

    
1108
        /* begin ring receiver mode */
1109
        int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1110

    
1111
        /* if receiver buffer is empty then avail == 0 */
1112

    
1113
        if (avail != 0 && size + 8 >= avail)
1114
        {
1115
            DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
1116
                   s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
1117

    
1118
            s->IntrStatus |= RxOverflow;
1119
            ++s->RxMissed;
1120
            rtl8139_update_irq(s);
1121
            return;
1122
        }
1123

    
1124
        packet_header |= RxStatusOK;
1125

    
1126
        packet_header |= (((size+4) << 16) & 0xffff0000);
1127

    
1128
        /* write header */
1129
        uint32_t val = cpu_to_le32(packet_header);
1130

    
1131
        rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1132

    
1133
        rtl8139_write_buffer(s, buf, size);
1134

    
1135
        /* write checksum */
1136
#if defined (RTL8139_CALCULATE_RXCRC)
1137
        val = cpu_to_le32(crc32(0, buf, size));
1138
#else
1139
        val = 0;
1140
#endif
1141

    
1142
        rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1143

    
1144
        /* correct buffer write pointer */
1145
        s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1146

    
1147
        /* now we can signal we have received something */
1148

    
1149
        DEBUG_PRINT(("   received: rx buffer length %d head 0x%04x read 0x%04x\n",
1150
               s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
1151
    }
1152

    
1153
    s->IntrStatus |= RxOK;
1154

    
1155
    if (do_interrupt)
1156
    {
1157
        rtl8139_update_irq(s);
1158
    }
1159
}
1160

    
1161
static void rtl8139_receive(void *opaque, const uint8_t *buf, size_t size)
1162
{
1163
    rtl8139_do_receive(opaque, buf, size, 1);
1164
}
1165

    
1166
static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1167
{
1168
    s->RxBufferSize = bufferSize;
1169
    s->RxBufPtr  = 0;
1170
    s->RxBufAddr = 0;
1171
}
1172

    
1173
static void rtl8139_reset(RTL8139State *s)
1174
{
1175
    int i;
1176

    
1177
    /* restore MAC address */
1178
    memcpy(s->phys, s->macaddr, 6);
1179

    
1180
    /* reset interrupt mask */
1181
    s->IntrStatus = 0;
1182
    s->IntrMask = 0;
1183

    
1184
    rtl8139_update_irq(s);
1185

    
1186
    /* prepare eeprom */
1187
    s->eeprom.contents[0] = 0x8129;
1188
#if 1
1189
    // PCI vendor and device ID should be mirrored here
1190
    s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
1191
    s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
1192
#endif
1193

    
1194
    s->eeprom.contents[7] = s->macaddr[0] | s->macaddr[1] << 8;
1195
    s->eeprom.contents[8] = s->macaddr[2] | s->macaddr[3] << 8;
1196
    s->eeprom.contents[9] = s->macaddr[4] | s->macaddr[5] << 8;
1197

    
1198
    /* mark all status registers as owned by host */
1199
    for (i = 0; i < 4; ++i)
1200
    {
1201
        s->TxStatus[i] = TxHostOwns;
1202
    }
1203

    
1204
    s->currTxDesc = 0;
1205
    s->currCPlusRxDesc = 0;
1206
    s->currCPlusTxDesc = 0;
1207

    
1208
    s->RxRingAddrLO = 0;
1209
    s->RxRingAddrHI = 0;
1210

    
1211
    s->RxBuf = 0;
1212

    
1213
    rtl8139_reset_rxring(s, 8192);
1214

    
1215
    /* ACK the reset */
1216
    s->TxConfig = 0;
1217

    
1218
#if 0
1219
//    s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139  HasHltClk
1220
    s->clock_enabled = 0;
1221
#else
1222
    s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1223
    s->clock_enabled = 1;
1224
#endif
1225

    
1226
    s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1227

    
1228
    /* set initial state data */
1229
    s->Config0 = 0x0; /* No boot ROM */
1230
    s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1231
    s->Config3 = 0x1; /* fast back-to-back compatible */
1232
    s->Config5 = 0x0;
1233

    
1234
    s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1235

    
1236
    s->CpCmd   = 0x0; /* reset C+ mode */
1237
    s->cplus_enabled = 0;
1238

    
1239

    
1240
//    s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1241
//    s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1242
    s->BasicModeCtrl = 0x1000; // autonegotiation
1243

    
1244
    s->BasicModeStatus  = 0x7809;
1245
    //s->BasicModeStatus |= 0x0040; /* UTP medium */
1246
    s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1247
    s->BasicModeStatus |= 0x0004; /* link is up */
1248

    
1249
    s->NWayAdvert    = 0x05e1; /* all modes, full duplex */
1250
    s->NWayLPAR      = 0x05e1; /* all modes, full duplex */
1251
    s->NWayExpansion = 0x0001; /* autonegotiation supported */
1252

    
1253
    /* also reset timer and disable timer interrupt */
1254
    s->TCTR = 0;
1255
    s->TimerInt = 0;
1256
    s->TCTR_base = 0;
1257

    
1258
    /* reset tally counters */
1259
    RTL8139TallyCounters_clear(&s->tally_counters);
1260
}
1261

    
1262
static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1263
{
1264
    counters->TxOk = 0;
1265
    counters->RxOk = 0;
1266
    counters->TxERR = 0;
1267
    counters->RxERR = 0;
1268
    counters->MissPkt = 0;
1269
    counters->FAE = 0;
1270
    counters->Tx1Col = 0;
1271
    counters->TxMCol = 0;
1272
    counters->RxOkPhy = 0;
1273
    counters->RxOkBrd = 0;
1274
    counters->RxOkMul = 0;
1275
    counters->TxAbt = 0;
1276
    counters->TxUndrn = 0;
1277
}
1278

    
1279
static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* tally_counters)
1280
{
1281
    uint16_t val16;
1282
    uint32_t val32;
1283
    uint64_t val64;
1284

    
1285
    val64 = cpu_to_le64(tally_counters->TxOk);
1286
    cpu_physical_memory_write(tc_addr + 0,    (uint8_t *)&val64, 8);
1287

    
1288
    val64 = cpu_to_le64(tally_counters->RxOk);
1289
    cpu_physical_memory_write(tc_addr + 8,    (uint8_t *)&val64, 8);
1290

    
1291
    val64 = cpu_to_le64(tally_counters->TxERR);
1292
    cpu_physical_memory_write(tc_addr + 16,    (uint8_t *)&val64, 8);
1293

    
1294
    val32 = cpu_to_le32(tally_counters->RxERR);
1295
    cpu_physical_memory_write(tc_addr + 24,    (uint8_t *)&val32, 4);
1296

    
1297
    val16 = cpu_to_le16(tally_counters->MissPkt);
1298
    cpu_physical_memory_write(tc_addr + 28,    (uint8_t *)&val16, 2);
1299

    
1300
    val16 = cpu_to_le16(tally_counters->FAE);
1301
    cpu_physical_memory_write(tc_addr + 30,    (uint8_t *)&val16, 2);
1302

    
1303
    val32 = cpu_to_le32(tally_counters->Tx1Col);
1304
    cpu_physical_memory_write(tc_addr + 32,    (uint8_t *)&val32, 4);
1305

    
1306
    val32 = cpu_to_le32(tally_counters->TxMCol);
1307
    cpu_physical_memory_write(tc_addr + 36,    (uint8_t *)&val32, 4);
1308

    
1309
    val64 = cpu_to_le64(tally_counters->RxOkPhy);
1310
    cpu_physical_memory_write(tc_addr + 40,    (uint8_t *)&val64, 8);
1311

    
1312
    val64 = cpu_to_le64(tally_counters->RxOkBrd);
1313
    cpu_physical_memory_write(tc_addr + 48,    (uint8_t *)&val64, 8);
1314

    
1315
    val32 = cpu_to_le32(tally_counters->RxOkMul);
1316
    cpu_physical_memory_write(tc_addr + 56,    (uint8_t *)&val32, 4);
1317

    
1318
    val16 = cpu_to_le16(tally_counters->TxAbt);
1319
    cpu_physical_memory_write(tc_addr + 60,    (uint8_t *)&val16, 2);
1320

    
1321
    val16 = cpu_to_le16(tally_counters->TxUndrn);
1322
    cpu_physical_memory_write(tc_addr + 62,    (uint8_t *)&val16, 2);
1323
}
1324

    
1325
/* Loads values of tally counters from VM state file */
1326
static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1327
{
1328
    qemu_get_be64s(f, &tally_counters->TxOk);
1329
    qemu_get_be64s(f, &tally_counters->RxOk);
1330
    qemu_get_be64s(f, &tally_counters->TxERR);
1331
    qemu_get_be32s(f, &tally_counters->RxERR);
1332
    qemu_get_be16s(f, &tally_counters->MissPkt);
1333
    qemu_get_be16s(f, &tally_counters->FAE);
1334
    qemu_get_be32s(f, &tally_counters->Tx1Col);
1335
    qemu_get_be32s(f, &tally_counters->TxMCol);
1336
    qemu_get_be64s(f, &tally_counters->RxOkPhy);
1337
    qemu_get_be64s(f, &tally_counters->RxOkBrd);
1338
    qemu_get_be32s(f, &tally_counters->RxOkMul);
1339
    qemu_get_be16s(f, &tally_counters->TxAbt);
1340
    qemu_get_be16s(f, &tally_counters->TxUndrn);
1341
}
1342

    
1343
/* Saves values of tally counters to VM state file */
1344
static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters)
1345
{
1346
    qemu_put_be64s(f, &tally_counters->TxOk);
1347
    qemu_put_be64s(f, &tally_counters->RxOk);
1348
    qemu_put_be64s(f, &tally_counters->TxERR);
1349
    qemu_put_be32s(f, &tally_counters->RxERR);
1350
    qemu_put_be16s(f, &tally_counters->MissPkt);
1351
    qemu_put_be16s(f, &tally_counters->FAE);
1352
    qemu_put_be32s(f, &tally_counters->Tx1Col);
1353
    qemu_put_be32s(f, &tally_counters->TxMCol);
1354
    qemu_put_be64s(f, &tally_counters->RxOkPhy);
1355
    qemu_put_be64s(f, &tally_counters->RxOkBrd);
1356
    qemu_put_be32s(f, &tally_counters->RxOkMul);
1357
    qemu_put_be16s(f, &tally_counters->TxAbt);
1358
    qemu_put_be16s(f, &tally_counters->TxUndrn);
1359
}
1360

    
1361
static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1362
{
1363
    val &= 0xff;
1364

    
1365
    DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
1366

    
1367
    if (val & CmdReset)
1368
    {
1369
        DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
1370
        rtl8139_reset(s);
1371
    }
1372
    if (val & CmdRxEnb)
1373
    {
1374
        DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
1375

    
1376
        s->currCPlusRxDesc = 0;
1377
    }
1378
    if (val & CmdTxEnb)
1379
    {
1380
        DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
1381

    
1382
        s->currCPlusTxDesc = 0;
1383
    }
1384

    
1385
    /* mask unwriteable bits */
1386
    val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1387

    
1388
    /* Deassert reset pin before next read */
1389
    val &= ~CmdReset;
1390

    
1391
    s->bChipCmdState = val;
1392
}
1393

    
1394
static int rtl8139_RxBufferEmpty(RTL8139State *s)
1395
{
1396
    int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1397

    
1398
    if (unread != 0)
1399
    {
1400
        DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
1401
        return 0;
1402
    }
1403

    
1404
    DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
1405

    
1406
    return 1;
1407
}
1408

    
1409
static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1410
{
1411
    uint32_t ret = s->bChipCmdState;
1412

    
1413
    if (rtl8139_RxBufferEmpty(s))
1414
        ret |= RxBufEmpty;
1415

    
1416
    DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
1417

    
1418
    return ret;
1419
}
1420

    
1421
static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1422
{
1423
    val &= 0xffff;
1424

    
1425
    DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
1426

    
1427
    s->cplus_enabled = 1;
1428

    
1429
    /* mask unwriteable bits */
1430
    val = SET_MASKED(val, 0xff84, s->CpCmd);
1431

    
1432
    s->CpCmd = val;
1433
}
1434

    
1435
static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1436
{
1437
    uint32_t ret = s->CpCmd;
1438

    
1439
    DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
1440

    
1441
    return ret;
1442
}
1443

    
1444
static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1445
{
1446
    DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
1447
}
1448

    
1449
static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1450
{
1451
    uint32_t ret = 0;
1452

    
1453
    DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
1454

    
1455
    return ret;
1456
}
1457

    
1458
static int rtl8139_config_writeable(RTL8139State *s)
1459
{
1460
    if (s->Cfg9346 & Cfg9346_Unlock)
1461
    {
1462
        return 1;
1463
    }
1464

    
1465
    DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
1466

    
1467
    return 0;
1468
}
1469

    
1470
static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1471
{
1472
    val &= 0xffff;
1473

    
1474
    DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
1475

    
1476
    /* mask unwriteable bits */
1477
    uint32_t mask = 0x4cff;
1478

    
1479
    if (1 || !rtl8139_config_writeable(s))
1480
    {
1481
        /* Speed setting and autonegotiation enable bits are read-only */
1482
        mask |= 0x3000;
1483
        /* Duplex mode setting is read-only */
1484
        mask |= 0x0100;
1485
    }
1486

    
1487
    val = SET_MASKED(val, mask, s->BasicModeCtrl);
1488

    
1489
    s->BasicModeCtrl = val;
1490
}
1491

    
1492
static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1493
{
1494
    uint32_t ret = s->BasicModeCtrl;
1495

    
1496
    DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
1497

    
1498
    return ret;
1499
}
1500

    
1501
static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1502
{
1503
    val &= 0xffff;
1504

    
1505
    DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
1506

    
1507
    /* mask unwriteable bits */
1508
    val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1509

    
1510
    s->BasicModeStatus = val;
1511
}
1512

    
1513
static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1514
{
1515
    uint32_t ret = s->BasicModeStatus;
1516

    
1517
    DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
1518

    
1519
    return ret;
1520
}
1521

    
1522
static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1523
{
1524
    val &= 0xff;
1525

    
1526
    DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
1527

    
1528
    /* mask unwriteable bits */
1529
    val = SET_MASKED(val, 0x31, s->Cfg9346);
1530

    
1531
    uint32_t opmode = val & 0xc0;
1532
    uint32_t eeprom_val = val & 0xf;
1533

    
1534
    if (opmode == 0x80) {
1535
        /* eeprom access */
1536
        int eecs = (eeprom_val & 0x08)?1:0;
1537
        int eesk = (eeprom_val & 0x04)?1:0;
1538
        int eedi = (eeprom_val & 0x02)?1:0;
1539
        prom9346_set_wire(s, eecs, eesk, eedi);
1540
    } else if (opmode == 0x40) {
1541
        /* Reset.  */
1542
        val = 0;
1543
        rtl8139_reset(s);
1544
    }
1545

    
1546
    s->Cfg9346 = val;
1547
}
1548

    
1549
static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1550
{
1551
    uint32_t ret = s->Cfg9346;
1552

    
1553
    uint32_t opmode = ret & 0xc0;
1554

    
1555
    if (opmode == 0x80)
1556
    {
1557
        /* eeprom access */
1558
        int eedo = prom9346_get_wire(s);
1559
        if (eedo)
1560
        {
1561
            ret |=  0x01;
1562
        }
1563
        else
1564
        {
1565
            ret &= ~0x01;
1566
        }
1567
    }
1568

    
1569
    DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
1570

    
1571
    return ret;
1572
}
1573

    
1574
static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1575
{
1576
    val &= 0xff;
1577

    
1578
    DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
1579

    
1580
    if (!rtl8139_config_writeable(s))
1581
        return;
1582

    
1583
    /* mask unwriteable bits */
1584
    val = SET_MASKED(val, 0xf8, s->Config0);
1585

    
1586
    s->Config0 = val;
1587
}
1588

    
1589
static uint32_t rtl8139_Config0_read(RTL8139State *s)
1590
{
1591
    uint32_t ret = s->Config0;
1592

    
1593
    DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
1594

    
1595
    return ret;
1596
}
1597

    
1598
static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1599
{
1600
    val &= 0xff;
1601

    
1602
    DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
1603

    
1604
    if (!rtl8139_config_writeable(s))
1605
        return;
1606

    
1607
    /* mask unwriteable bits */
1608
    val = SET_MASKED(val, 0xC, s->Config1);
1609

    
1610
    s->Config1 = val;
1611
}
1612

    
1613
static uint32_t rtl8139_Config1_read(RTL8139State *s)
1614
{
1615
    uint32_t ret = s->Config1;
1616

    
1617
    DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
1618

    
1619
    return ret;
1620
}
1621

    
1622
static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1623
{
1624
    val &= 0xff;
1625

    
1626
    DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
1627

    
1628
    if (!rtl8139_config_writeable(s))
1629
        return;
1630

    
1631
    /* mask unwriteable bits */
1632
    val = SET_MASKED(val, 0x8F, s->Config3);
1633

    
1634
    s->Config3 = val;
1635
}
1636

    
1637
static uint32_t rtl8139_Config3_read(RTL8139State *s)
1638
{
1639
    uint32_t ret = s->Config3;
1640

    
1641
    DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
1642

    
1643
    return ret;
1644
}
1645

    
1646
static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1647
{
1648
    val &= 0xff;
1649

    
1650
    DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
1651

    
1652
    if (!rtl8139_config_writeable(s))
1653
        return;
1654

    
1655
    /* mask unwriteable bits */
1656
    val = SET_MASKED(val, 0x0a, s->Config4);
1657

    
1658
    s->Config4 = val;
1659
}
1660

    
1661
static uint32_t rtl8139_Config4_read(RTL8139State *s)
1662
{
1663
    uint32_t ret = s->Config4;
1664

    
1665
    DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
1666

    
1667
    return ret;
1668
}
1669

    
1670
static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1671
{
1672
    val &= 0xff;
1673

    
1674
    DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
1675

    
1676
    /* mask unwriteable bits */
1677
    val = SET_MASKED(val, 0x80, s->Config5);
1678

    
1679
    s->Config5 = val;
1680
}
1681

    
1682
static uint32_t rtl8139_Config5_read(RTL8139State *s)
1683
{
1684
    uint32_t ret = s->Config5;
1685

    
1686
    DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
1687

    
1688
    return ret;
1689
}
1690

    
1691
static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1692
{
1693
    if (!rtl8139_transmitter_enabled(s))
1694
    {
1695
        DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
1696
        return;
1697
    }
1698

    
1699
    DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
1700

    
1701
    val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1702

    
1703
    s->TxConfig = val;
1704
}
1705

    
1706
static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1707
{
1708
    DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
1709

    
1710
    uint32_t tc = s->TxConfig;
1711
    tc &= 0xFFFFFF00;
1712
    tc |= (val & 0x000000FF);
1713
    rtl8139_TxConfig_write(s, tc);
1714
}
1715

    
1716
static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1717
{
1718
    uint32_t ret = s->TxConfig;
1719

    
1720
    DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
1721

    
1722
    return ret;
1723
}
1724

    
1725
static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1726
{
1727
    DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
1728

    
1729
    /* mask unwriteable bits */
1730
    val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1731

    
1732
    s->RxConfig = val;
1733

    
1734
    /* reset buffer size and read/write pointers */
1735
    rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1736

    
1737
    DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
1738
}
1739

    
1740
static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1741
{
1742
    uint32_t ret = s->RxConfig;
1743

    
1744
    DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
1745

    
1746
    return ret;
1747
}
1748

    
1749
static void rtl8139_transfer_frame(RTL8139State *s, const uint8_t *buf, int size, int do_interrupt)
1750
{
1751
    if (!size)
1752
    {
1753
        DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
1754
        return;
1755
    }
1756

    
1757
    if (TxLoopBack == (s->TxConfig & TxLoopBack))
1758
    {
1759
        DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
1760
        rtl8139_do_receive(s, buf, size, do_interrupt);
1761
    }
1762
    else
1763
    {
1764
        qemu_send_packet(s->vc, buf, size);
1765
    }
1766
}
1767

    
1768
static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1769
{
1770
    if (!rtl8139_transmitter_enabled(s))
1771
    {
1772
        DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
1773
                     descriptor));
1774
        return 0;
1775
    }
1776

    
1777
    if (s->TxStatus[descriptor] & TxHostOwns)
1778
    {
1779
        DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
1780
                     descriptor, s->TxStatus[descriptor]));
1781
        return 0;
1782
    }
1783

    
1784
    DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
1785

    
1786
    int txsize = s->TxStatus[descriptor] & 0x1fff;
1787
    uint8_t txbuffer[0x2000];
1788

    
1789
    DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
1790
                 txsize, s->TxAddr[descriptor]));
1791

    
1792
    cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
1793

    
1794
    /* Mark descriptor as transferred */
1795
    s->TxStatus[descriptor] |= TxHostOwns;
1796
    s->TxStatus[descriptor] |= TxStatOK;
1797

    
1798
    rtl8139_transfer_frame(s, txbuffer, txsize, 0);
1799

    
1800
    DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
1801

    
1802
    /* update interrupt */
1803
    s->IntrStatus |= TxOK;
1804
    rtl8139_update_irq(s);
1805

    
1806
    return 1;
1807
}
1808

    
1809
/* structures and macros for task offloading */
1810
typedef struct ip_header
1811
{
1812
    uint8_t  ip_ver_len;    /* version and header length */
1813
    uint8_t  ip_tos;        /* type of service */
1814
    uint16_t ip_len;        /* total length */
1815
    uint16_t ip_id;         /* identification */
1816
    uint16_t ip_off;        /* fragment offset field */
1817
    uint8_t  ip_ttl;        /* time to live */
1818
    uint8_t  ip_p;          /* protocol */
1819
    uint16_t ip_sum;        /* checksum */
1820
    uint32_t ip_src,ip_dst; /* source and dest address */
1821
} ip_header;
1822

    
1823
#define IP_HEADER_VERSION_4 4
1824
#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1825
#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1826

    
1827
typedef struct tcp_header
1828
{
1829
    uint16_t th_sport;                /* source port */
1830
    uint16_t th_dport;                /* destination port */
1831
    uint32_t th_seq;                        /* sequence number */
1832
    uint32_t th_ack;                        /* acknowledgement number */
1833
    uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1834
    uint16_t th_win;                        /* window */
1835
    uint16_t th_sum;                        /* checksum */
1836
    uint16_t th_urp;                        /* urgent pointer */
1837
} tcp_header;
1838

    
1839
typedef struct udp_header
1840
{
1841
    uint16_t uh_sport; /* source port */
1842
    uint16_t uh_dport; /* destination port */
1843
    uint16_t uh_ulen;  /* udp length */
1844
    uint16_t uh_sum;   /* udp checksum */
1845
} udp_header;
1846

    
1847
typedef struct ip_pseudo_header
1848
{
1849
    uint32_t ip_src;
1850
    uint32_t ip_dst;
1851
    uint8_t  zeros;
1852
    uint8_t  ip_proto;
1853
    uint16_t ip_payload;
1854
} ip_pseudo_header;
1855

    
1856
#define IP_PROTO_TCP 6
1857
#define IP_PROTO_UDP 17
1858

    
1859
#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1860
#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1861
#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1862

    
1863
#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1864

    
1865
#define TCP_FLAG_FIN  0x01
1866
#define TCP_FLAG_PUSH 0x08
1867

    
1868
/* produces ones' complement sum of data */
1869
static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1870
{
1871
    uint32_t result = 0;
1872

    
1873
    for (; len > 1; data+=2, len-=2)
1874
    {
1875
        result += *(uint16_t*)data;
1876
    }
1877

    
1878
    /* add the remainder byte */
1879
    if (len)
1880
    {
1881
        uint8_t odd[2] = {*data, 0};
1882
        result += *(uint16_t*)odd;
1883
    }
1884

    
1885
    while (result>>16)
1886
        result = (result & 0xffff) + (result >> 16);
1887

    
1888
    return result;
1889
}
1890

    
1891
static uint16_t ip_checksum(void *data, size_t len)
1892
{
1893
    return ~ones_complement_sum((uint8_t*)data, len);
1894
}
1895

    
1896
static int rtl8139_cplus_transmit_one(RTL8139State *s)
1897
{
1898
    if (!rtl8139_transmitter_enabled(s))
1899
    {
1900
        DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
1901
        return 0;
1902
    }
1903

    
1904
    if (!rtl8139_cp_transmitter_enabled(s))
1905
    {
1906
        DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
1907
        return 0 ;
1908
    }
1909

    
1910
    int descriptor = s->currCPlusTxDesc;
1911

    
1912
    target_phys_addr_t cplus_tx_ring_desc =
1913
        rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1914

    
1915
    /* Normal priority ring */
1916
    cplus_tx_ring_desc += 16 * descriptor;
1917

    
1918
    DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
1919
           descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
1920

    
1921
    uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1922

    
1923
    cpu_physical_memory_read(cplus_tx_ring_desc,    (uint8_t *)&val, 4);
1924
    txdw0 = le32_to_cpu(val);
1925
    cpu_physical_memory_read(cplus_tx_ring_desc+4,  (uint8_t *)&val, 4);
1926
    txdw1 = le32_to_cpu(val);
1927
    cpu_physical_memory_read(cplus_tx_ring_desc+8,  (uint8_t *)&val, 4);
1928
    txbufLO = le32_to_cpu(val);
1929
    cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1930
    txbufHI = le32_to_cpu(val);
1931

    
1932
    DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
1933
           descriptor,
1934
           txdw0, txdw1, txbufLO, txbufHI));
1935

    
1936
/* w0 ownership flag */
1937
#define CP_TX_OWN (1<<31)
1938
/* w0 end of ring flag */
1939
#define CP_TX_EOR (1<<30)
1940
/* first segment of received packet flag */
1941
#define CP_TX_FS (1<<29)
1942
/* last segment of received packet flag */
1943
#define CP_TX_LS (1<<28)
1944
/* large send packet flag */
1945
#define CP_TX_LGSEN (1<<27)
1946
/* large send MSS mask, bits 16...25 */
1947
#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1948

    
1949
/* IP checksum offload flag */
1950
#define CP_TX_IPCS (1<<18)
1951
/* UDP checksum offload flag */
1952
#define CP_TX_UDPCS (1<<17)
1953
/* TCP checksum offload flag */
1954
#define CP_TX_TCPCS (1<<16)
1955

    
1956
/* w0 bits 0...15 : buffer size */
1957
#define CP_TX_BUFFER_SIZE (1<<16)
1958
#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1959
/* w1 tag available flag */
1960
#define CP_RX_TAGC (1<<17)
1961
/* w1 bits 0...15 : VLAN tag */
1962
#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1963
/* w2 low  32bit of Rx buffer ptr */
1964
/* w3 high 32bit of Rx buffer ptr */
1965

    
1966
/* set after transmission */
1967
/* FIFO underrun flag */
1968
#define CP_TX_STATUS_UNF (1<<25)
1969
/* transmit error summary flag, valid if set any of three below */
1970
#define CP_TX_STATUS_TES (1<<23)
1971
/* out-of-window collision flag */
1972
#define CP_TX_STATUS_OWC (1<<22)
1973
/* link failure flag */
1974
#define CP_TX_STATUS_LNKF (1<<21)
1975
/* excessive collisions flag */
1976
#define CP_TX_STATUS_EXC (1<<20)
1977

    
1978
    if (!(txdw0 & CP_TX_OWN))
1979
    {
1980
        DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
1981
        return 0 ;
1982
    }
1983

    
1984
    DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
1985

    
1986
    if (txdw0 & CP_TX_FS)
1987
    {
1988
        DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
1989

    
1990
        /* reset internal buffer offset */
1991
        s->cplus_txbuffer_offset = 0;
1992
    }
1993

    
1994
    int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
1995
    target_phys_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
1996

    
1997
    /* make sure we have enough space to assemble the packet */
1998
    if (!s->cplus_txbuffer)
1999
    {
2000
        s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2001
        s->cplus_txbuffer = malloc(s->cplus_txbuffer_len);
2002
        s->cplus_txbuffer_offset = 0;
2003

    
2004
        DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
2005
    }
2006

    
2007
    while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2008
    {
2009
        s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
2010
        s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
2011

    
2012
        DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
2013
    }
2014

    
2015
    if (!s->cplus_txbuffer)
2016
    {
2017
        /* out of memory */
2018

    
2019
        DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
2020

    
2021
        /* update tally counter */
2022
        ++s->tally_counters.TxERR;
2023
        ++s->tally_counters.TxAbt;
2024

    
2025
        return 0;
2026
    }
2027

    
2028
    /* append more data to the packet */
2029

    
2030
    DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
2031
                 txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
2032

    
2033
    cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2034
    s->cplus_txbuffer_offset += txsize;
2035

    
2036
    /* seek to next Rx descriptor */
2037
    if (txdw0 & CP_TX_EOR)
2038
    {
2039
        s->currCPlusTxDesc = 0;
2040
    }
2041
    else
2042
    {
2043
        ++s->currCPlusTxDesc;
2044
        if (s->currCPlusTxDesc >= 64)
2045
            s->currCPlusTxDesc = 0;
2046
    }
2047

    
2048
    /* transfer ownership to target */
2049
    txdw0 &= ~CP_RX_OWN;
2050

    
2051
    /* reset error indicator bits */
2052
    txdw0 &= ~CP_TX_STATUS_UNF;
2053
    txdw0 &= ~CP_TX_STATUS_TES;
2054
    txdw0 &= ~CP_TX_STATUS_OWC;
2055
    txdw0 &= ~CP_TX_STATUS_LNKF;
2056
    txdw0 &= ~CP_TX_STATUS_EXC;
2057

    
2058
    /* update ring data */
2059
    val = cpu_to_le32(txdw0);
2060
    cpu_physical_memory_write(cplus_tx_ring_desc,    (uint8_t *)&val, 4);
2061
//    val = cpu_to_le32(txdw1);
2062
//    cpu_physical_memory_write(cplus_tx_ring_desc+4,  &val, 4);
2063

    
2064
    /* Now decide if descriptor being processed is holding the last segment of packet */
2065
    if (txdw0 & CP_TX_LS)
2066
    {
2067
        DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
2068

    
2069
        /* can transfer fully assembled packet */
2070

    
2071
        uint8_t *saved_buffer  = s->cplus_txbuffer;
2072
        int      saved_size    = s->cplus_txbuffer_offset;
2073
        int      saved_buffer_len = s->cplus_txbuffer_len;
2074

    
2075
        /* reset the card space to protect from recursive call */
2076
        s->cplus_txbuffer = NULL;
2077
        s->cplus_txbuffer_offset = 0;
2078
        s->cplus_txbuffer_len = 0;
2079

    
2080
        if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2081
        {
2082
            DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
2083

    
2084
            #define ETH_P_IP        0x0800                /* Internet Protocol packet        */
2085
            #define ETH_HLEN    14
2086
            #define ETH_MTU     1500
2087

    
2088
            /* ip packet header */
2089
            ip_header *ip = 0;
2090
            int hlen = 0;
2091
            uint8_t  ip_protocol = 0;
2092
            uint16_t ip_data_len = 0;
2093

    
2094
            uint8_t *eth_payload_data = 0;
2095
            size_t   eth_payload_len  = 0;
2096

    
2097
            int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2098
            if (proto == ETH_P_IP)
2099
            {
2100
                DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
2101

    
2102
                /* not aligned */
2103
                eth_payload_data = saved_buffer + ETH_HLEN;
2104
                eth_payload_len  = saved_size   - ETH_HLEN;
2105

    
2106
                ip = (ip_header*)eth_payload_data;
2107

    
2108
                if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2109
                    DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
2110
                    ip = NULL;
2111
                } else {
2112
                    hlen = IP_HEADER_LENGTH(ip);
2113
                    ip_protocol = ip->ip_p;
2114
                    ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
2115
                }
2116
            }
2117

    
2118
            if (ip)
2119
            {
2120
                if (txdw0 & CP_TX_IPCS)
2121
                {
2122
                    DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
2123

    
2124
                    if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
2125
                        /* bad packet header len */
2126
                        /* or packet too short */
2127
                    }
2128
                    else
2129
                    {
2130
                        ip->ip_sum = 0;
2131
                        ip->ip_sum = ip_checksum(ip, hlen);
2132
                        DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2133
                    }
2134
                }
2135

    
2136
                if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2137
                {
2138
#if defined (DEBUG_RTL8139)
2139
                    int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2140
#endif
2141
                    DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
2142
                                 ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
2143

    
2144
                    int tcp_send_offset = 0;
2145
                    int send_count = 0;
2146

    
2147
                    /* maximum IP header length is 60 bytes */
2148
                    uint8_t saved_ip_header[60];
2149

    
2150
                    /* save IP header template; data area is used in tcp checksum calculation */
2151
                    memcpy(saved_ip_header, eth_payload_data, hlen);
2152

    
2153
                    /* a placeholder for checksum calculation routine in tcp case */
2154
                    uint8_t *data_to_checksum     = eth_payload_data + hlen - 12;
2155
                    //                    size_t   data_to_checksum_len = eth_payload_len  - hlen + 12;
2156

    
2157
                    /* pointer to TCP header */
2158
                    tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2159

    
2160
                    int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2161

    
2162
                    /* ETH_MTU = ip header len + tcp header len + payload */
2163
                    int tcp_data_len = ip_data_len - tcp_hlen;
2164
                    int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2165

    
2166
                    DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
2167
                                 ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
2168

    
2169
                    /* note the cycle below overwrites IP header data,
2170
                       but restores it from saved_ip_header before sending packet */
2171

    
2172
                    int is_last_frame = 0;
2173

    
2174
                    for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2175
                    {
2176
                        uint16_t chunk_size = tcp_chunk_size;
2177

    
2178
                        /* check if this is the last frame */
2179
                        if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2180
                        {
2181
                            is_last_frame = 1;
2182
                            chunk_size = tcp_data_len - tcp_send_offset;
2183
                        }
2184

    
2185
                        DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
2186

    
2187
                        /* add 4 TCP pseudoheader fields */
2188
                        /* copy IP source and destination fields */
2189
                        memcpy(data_to_checksum, saved_ip_header + 12, 8);
2190

    
2191
                        DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
2192

    
2193
                        if (tcp_send_offset)
2194
                        {
2195
                            memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2196
                        }
2197

    
2198
                        /* keep PUSH and FIN flags only for the last frame */
2199
                        if (!is_last_frame)
2200
                        {
2201
                            TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2202
                        }
2203

    
2204
                        /* recalculate TCP checksum */
2205
                        ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2206
                        p_tcpip_hdr->zeros      = 0;
2207
                        p_tcpip_hdr->ip_proto   = IP_PROTO_TCP;
2208
                        p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2209

    
2210
                        p_tcp_hdr->th_sum = 0;
2211

    
2212
                        int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2213
                        DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
2214

    
2215
                        p_tcp_hdr->th_sum = tcp_checksum;
2216

    
2217
                        /* restore IP header */
2218
                        memcpy(eth_payload_data, saved_ip_header, hlen);
2219

    
2220
                        /* set IP data length and recalculate IP checksum */
2221
                        ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2222

    
2223
                        /* increment IP id for subsequent frames */
2224
                        ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2225

    
2226
                        ip->ip_sum = 0;
2227
                        ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2228
                        DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
2229

    
2230
                        int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2231
                        DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
2232
                        rtl8139_transfer_frame(s, saved_buffer, tso_send_size, 0);
2233

    
2234
                        /* add transferred count to TCP sequence number */
2235
                        p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2236
                        ++send_count;
2237
                    }
2238

    
2239
                    /* Stop sending this frame */
2240
                    saved_size = 0;
2241
                }
2242
                else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2243
                {
2244
                    DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
2245

    
2246
                    /* maximum IP header length is 60 bytes */
2247
                    uint8_t saved_ip_header[60];
2248
                    memcpy(saved_ip_header, eth_payload_data, hlen);
2249

    
2250
                    uint8_t *data_to_checksum     = eth_payload_data + hlen - 12;
2251
                    //                    size_t   data_to_checksum_len = eth_payload_len  - hlen + 12;
2252

    
2253
                    /* add 4 TCP pseudoheader fields */
2254
                    /* copy IP source and destination fields */
2255
                    memcpy(data_to_checksum, saved_ip_header + 12, 8);
2256

    
2257
                    if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2258
                    {
2259
                        DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
2260

    
2261
                        ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2262
                        p_tcpip_hdr->zeros      = 0;
2263
                        p_tcpip_hdr->ip_proto   = IP_PROTO_TCP;
2264
                        p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2265

    
2266
                        tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2267

    
2268
                        p_tcp_hdr->th_sum = 0;
2269

    
2270
                        int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2271
                        DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
2272

    
2273
                        p_tcp_hdr->th_sum = tcp_checksum;
2274
                    }
2275
                    else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2276
                    {
2277
                        DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
2278

    
2279
                        ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2280
                        p_udpip_hdr->zeros      = 0;
2281
                        p_udpip_hdr->ip_proto   = IP_PROTO_UDP;
2282
                        p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2283

    
2284
                        udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2285

    
2286
                        p_udp_hdr->uh_sum = 0;
2287

    
2288
                        int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2289
                        DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
2290

    
2291
                        p_udp_hdr->uh_sum = udp_checksum;
2292
                    }
2293

    
2294
                    /* restore IP header */
2295
                    memcpy(eth_payload_data, saved_ip_header, hlen);
2296
                }
2297
            }
2298
        }
2299

    
2300
        /* update tally counter */
2301
        ++s->tally_counters.TxOk;
2302

    
2303
        DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
2304

    
2305
        rtl8139_transfer_frame(s, saved_buffer, saved_size, 1);
2306

    
2307
        /* restore card space if there was no recursion and reset offset */
2308
        if (!s->cplus_txbuffer)
2309
        {
2310
            s->cplus_txbuffer        = saved_buffer;
2311
            s->cplus_txbuffer_len    = saved_buffer_len;
2312
            s->cplus_txbuffer_offset = 0;
2313
        }
2314
        else
2315
        {
2316
            free(saved_buffer);
2317
        }
2318
    }
2319
    else
2320
    {
2321
        DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
2322
    }
2323

    
2324
    return 1;
2325
}
2326

    
2327
static void rtl8139_cplus_transmit(RTL8139State *s)
2328
{
2329
    int txcount = 0;
2330

    
2331
    while (rtl8139_cplus_transmit_one(s))
2332
    {
2333
        ++txcount;
2334
    }
2335

    
2336
    /* Mark transfer completed */
2337
    if (!txcount)
2338
    {
2339
        DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2340
                     s->currCPlusTxDesc));
2341
    }
2342
    else
2343
    {
2344
        /* update interrupt status */
2345
        s->IntrStatus |= TxOK;
2346
        rtl8139_update_irq(s);
2347
    }
2348
}
2349

    
2350
static void rtl8139_transmit(RTL8139State *s)
2351
{
2352
    int descriptor = s->currTxDesc, txcount = 0;
2353

    
2354
    /*while*/
2355
    if (rtl8139_transmit_one(s, descriptor))
2356
    {
2357
        ++s->currTxDesc;
2358
        s->currTxDesc %= 4;
2359
        ++txcount;
2360
    }
2361

    
2362
    /* Mark transfer completed */
2363
    if (!txcount)
2364
    {
2365
        DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
2366
    }
2367
}
2368

    
2369
static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2370
{
2371

    
2372
    int descriptor = txRegOffset/4;
2373

    
2374
    /* handle C+ transmit mode register configuration */
2375

    
2376
    if (s->cplus_enabled)
2377
    {
2378
        DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2379

    
2380
        /* handle Dump Tally Counters command */
2381
        s->TxStatus[descriptor] = val;
2382

    
2383
        if (descriptor == 0 && (val & 0x8))
2384
        {
2385
            target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2386

    
2387
            /* dump tally counters to specified memory location */
2388
            RTL8139TallyCounters_physical_memory_write( tc_addr, &s->tally_counters);
2389

    
2390
            /* mark dump completed */
2391
            s->TxStatus[0] &= ~0x8;
2392
        }
2393

    
2394
        return;
2395
    }
2396

    
2397
    DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
2398

    
2399
    /* mask only reserved bits */
2400
    val &= ~0xff00c000; /* these bits are reset on write */
2401
    val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2402

    
2403
    s->TxStatus[descriptor] = val;
2404

    
2405
    /* attempt to start transmission */
2406
    rtl8139_transmit(s);
2407
}
2408

    
2409
static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
2410
{
2411
    uint32_t ret = s->TxStatus[txRegOffset/4];
2412

    
2413
    DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
2414

    
2415
    return ret;
2416
}
2417

    
2418
static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2419
{
2420
    uint16_t ret = 0;
2421

    
2422
    /* Simulate TSAD, it is read only anyway */
2423

    
2424
    ret = ((s->TxStatus[3] & TxStatOK  )?TSAD_TOK3:0)
2425
         |((s->TxStatus[2] & TxStatOK  )?TSAD_TOK2:0)
2426
         |((s->TxStatus[1] & TxStatOK  )?TSAD_TOK1:0)
2427
         |((s->TxStatus[0] & TxStatOK  )?TSAD_TOK0:0)
2428

    
2429
         |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2430
         |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2431
         |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2432
         |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2433

    
2434
         |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2435
         |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2436
         |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2437
         |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2438

    
2439
         |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2440
         |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2441
         |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2442
         |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2443

    
2444

    
2445
    DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
2446

    
2447
    return ret;
2448
}
2449

    
2450
static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2451
{
2452
    uint16_t ret = s->CSCR;
2453

    
2454
    DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
2455

    
2456
    return ret;
2457
}
2458

    
2459
static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2460
{
2461
    DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
2462

    
2463
    s->TxAddr[txAddrOffset/4] = val;
2464
}
2465

    
2466
static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2467
{
2468
    uint32_t ret = s->TxAddr[txAddrOffset/4];
2469

    
2470
    DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
2471

    
2472
    return ret;
2473
}
2474

    
2475
static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2476
{
2477
    DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
2478

    
2479
    /* this value is off by 16 */
2480
    s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2481

    
2482
    DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2483
           s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
2484
}
2485

    
2486
static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2487
{
2488
    /* this value is off by 16 */
2489
    uint32_t ret = s->RxBufPtr - 0x10;
2490

    
2491
    DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
2492

    
2493
    return ret;
2494
}
2495

    
2496
static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2497
{
2498
    /* this value is NOT off by 16 */
2499
    uint32_t ret = s->RxBufAddr;
2500

    
2501
    DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
2502

    
2503
    return ret;
2504
}
2505

    
2506
static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2507
{
2508
    DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
2509

    
2510
    s->RxBuf = val;
2511

    
2512
    /* may need to reset rxring here */
2513
}
2514

    
2515
static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2516
{
2517
    uint32_t ret = s->RxBuf;
2518

    
2519
    DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
2520

    
2521
    return ret;
2522
}
2523

    
2524
static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2525
{
2526
    DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
2527

    
2528
    /* mask unwriteable bits */
2529
    val = SET_MASKED(val, 0x1e00, s->IntrMask);
2530

    
2531
    s->IntrMask = val;
2532

    
2533
    rtl8139_update_irq(s);
2534
}
2535

    
2536
static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2537
{
2538
    uint32_t ret = s->IntrMask;
2539

    
2540
    DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
2541

    
2542
    return ret;
2543
}
2544

    
2545
static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2546
{
2547
    DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
2548

    
2549
#if 0
2550

2551
    /* writing to ISR has no effect */
2552

2553
    return;
2554

2555
#else
2556
    uint16_t newStatus = s->IntrStatus & ~val;
2557

    
2558
    /* mask unwriteable bits */
2559
    newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2560

    
2561
    /* writing 1 to interrupt status register bit clears it */
2562
    s->IntrStatus = 0;
2563
    rtl8139_update_irq(s);
2564

    
2565
    s->IntrStatus = newStatus;
2566
    rtl8139_update_irq(s);
2567
#endif
2568
}
2569

    
2570
static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2571
{
2572
    uint32_t ret = s->IntrStatus;
2573

    
2574
    DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
2575

    
2576
#if 0
2577

2578
    /* reading ISR clears all interrupts */
2579
    s->IntrStatus = 0;
2580

2581
    rtl8139_update_irq(s);
2582

2583
#endif
2584

    
2585
    return ret;
2586
}
2587

    
2588
static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2589
{
2590
    DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
2591

    
2592
    /* mask unwriteable bits */
2593
    val = SET_MASKED(val, 0xf000, s->MultiIntr);
2594

    
2595
    s->MultiIntr = val;
2596
}
2597

    
2598
static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2599
{
2600
    uint32_t ret = s->MultiIntr;
2601

    
2602
    DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
2603

    
2604
    return ret;
2605
}
2606

    
2607
static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2608
{
2609
    RTL8139State *s = opaque;
2610

    
2611
    addr &= 0xff;
2612

    
2613
    switch (addr)
2614
    {
2615
        case MAC0 ... MAC0+5:
2616
            s->phys[addr - MAC0] = val;
2617
            break;
2618
        case MAC0+6 ... MAC0+7:
2619
            /* reserved */
2620
            break;
2621
        case MAR0 ... MAR0+7:
2622
            s->mult[addr - MAR0] = val;
2623
            break;
2624
        case ChipCmd:
2625
            rtl8139_ChipCmd_write(s, val);
2626
            break;
2627
        case Cfg9346:
2628
            rtl8139_Cfg9346_write(s, val);
2629
            break;
2630
        case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2631
            rtl8139_TxConfig_writeb(s, val);
2632
            break;
2633
        case Config0:
2634
            rtl8139_Config0_write(s, val);
2635
            break;
2636
        case Config1:
2637
            rtl8139_Config1_write(s, val);
2638
            break;
2639
        case Config3:
2640
            rtl8139_Config3_write(s, val);
2641
            break;
2642
        case Config4:
2643
            rtl8139_Config4_write(s, val);
2644
            break;
2645
        case Config5:
2646
            rtl8139_Config5_write(s, val);
2647
            break;
2648
        case MediaStatus:
2649
            /* ignore */
2650
            DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
2651
            break;
2652

    
2653
        case HltClk:
2654
            DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
2655
            if (val == 'R')
2656
            {
2657
                s->clock_enabled = 1;
2658
            }
2659
            else if (val == 'H')
2660
            {
2661
                s->clock_enabled = 0;
2662
            }
2663
            break;
2664

    
2665
        case TxThresh:
2666
            DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
2667
            s->TxThresh = val;
2668
            break;
2669

    
2670
        case TxPoll:
2671
            DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
2672
            if (val & (1 << 7))
2673
            {
2674
                DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
2675
                //rtl8139_cplus_transmit(s);
2676
            }
2677
            if (val & (1 << 6))
2678
            {
2679
                DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
2680
                rtl8139_cplus_transmit(s);
2681
            }
2682

    
2683
            break;
2684

    
2685
        default:
2686
            DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
2687
            break;
2688
    }
2689
}
2690

    
2691
static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2692
{
2693
    RTL8139State *s = opaque;
2694

    
2695
    addr &= 0xfe;
2696

    
2697
    switch (addr)
2698
    {
2699
        case IntrMask:
2700
            rtl8139_IntrMask_write(s, val);
2701
            break;
2702

    
2703
        case IntrStatus:
2704
            rtl8139_IntrStatus_write(s, val);
2705
            break;
2706

    
2707
        case MultiIntr:
2708
            rtl8139_MultiIntr_write(s, val);
2709
            break;
2710

    
2711
        case RxBufPtr:
2712
            rtl8139_RxBufPtr_write(s, val);
2713
            break;
2714

    
2715
        case BasicModeCtrl:
2716
            rtl8139_BasicModeCtrl_write(s, val);
2717
            break;
2718
        case BasicModeStatus:
2719
            rtl8139_BasicModeStatus_write(s, val);
2720
            break;
2721
        case NWayAdvert:
2722
            DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
2723
            s->NWayAdvert = val;
2724
            break;
2725
        case NWayLPAR:
2726
            DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
2727
            break;
2728
        case NWayExpansion:
2729
            DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
2730
            s->NWayExpansion = val;
2731
            break;
2732

    
2733
        case CpCmd:
2734
            rtl8139_CpCmd_write(s, val);
2735
            break;
2736

    
2737
        case IntrMitigate:
2738
            rtl8139_IntrMitigate_write(s, val);
2739
            break;
2740

    
2741
        default:
2742
            DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
2743

    
2744
            rtl8139_io_writeb(opaque, addr, val & 0xff);
2745
            rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2746
            break;
2747
    }
2748
}
2749

    
2750
static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2751
{
2752
    RTL8139State *s = opaque;
2753

    
2754
    addr &= 0xfc;
2755

    
2756
    switch (addr)
2757
    {
2758
        case RxMissed:
2759
            DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
2760
            s->RxMissed = 0;
2761
            break;
2762

    
2763
        case TxConfig:
2764
            rtl8139_TxConfig_write(s, val);
2765
            break;
2766

    
2767
        case RxConfig:
2768
            rtl8139_RxConfig_write(s, val);
2769
            break;
2770

    
2771
        case TxStatus0 ... TxStatus0+4*4-1:
2772
            rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2773
            break;
2774

    
2775
        case TxAddr0 ... TxAddr0+4*4-1:
2776
            rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2777
            break;
2778

    
2779
        case RxBuf:
2780
            rtl8139_RxBuf_write(s, val);
2781
            break;
2782

    
2783
        case RxRingAddrLO:
2784
            DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
2785
            s->RxRingAddrLO = val;
2786
            break;
2787

    
2788
        case RxRingAddrHI:
2789
            DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
2790
            s->RxRingAddrHI = val;
2791
            break;
2792

    
2793
        case Timer:
2794
            DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
2795
            s->TCTR = 0;
2796
            s->TCTR_base = qemu_get_clock(vm_clock);
2797
            break;
2798

    
2799
        case FlashReg:
2800
            DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
2801
            s->TimerInt = val;
2802
            break;
2803

    
2804
        default:
2805
            DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
2806
            rtl8139_io_writeb(opaque, addr, val & 0xff);
2807
            rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2808
            rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2809
            rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2810
            break;
2811
    }
2812
}
2813

    
2814
static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2815
{
2816
    RTL8139State *s = opaque;
2817
    int ret;
2818

    
2819
    addr &= 0xff;
2820

    
2821
    switch (addr)
2822
    {
2823
        case MAC0 ... MAC0+5:
2824
            ret = s->phys[addr - MAC0];
2825
            break;
2826
        case MAC0+6 ... MAC0+7:
2827
            ret = 0;
2828
            break;
2829
        case MAR0 ... MAR0+7:
2830
            ret = s->mult[addr - MAR0];
2831
            break;
2832
        case ChipCmd:
2833
            ret = rtl8139_ChipCmd_read(s);
2834
            break;
2835
        case Cfg9346:
2836
            ret = rtl8139_Cfg9346_read(s);
2837
            break;
2838
        case Config0:
2839
            ret = rtl8139_Config0_read(s);
2840
            break;
2841
        case Config1:
2842
            ret = rtl8139_Config1_read(s);
2843
            break;
2844
        case Config3:
2845
            ret = rtl8139_Config3_read(s);
2846
            break;
2847
        case Config4:
2848
            ret = rtl8139_Config4_read(s);
2849
            break;
2850
        case Config5:
2851
            ret = rtl8139_Config5_read(s);
2852
            break;
2853

    
2854
        case MediaStatus:
2855
            ret = 0xd0;
2856
            DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
2857
            break;
2858

    
2859
        case HltClk:
2860
            ret = s->clock_enabled;
2861
            DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
2862
            break;
2863

    
2864
        case PCIRevisionID:
2865
            ret = RTL8139_PCI_REVID;
2866
            DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
2867
            break;
2868

    
2869
        case TxThresh:
2870
            ret = s->TxThresh;
2871
            DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
2872
            break;
2873

    
2874
        case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
2875
            ret = s->TxConfig >> 24;
2876
            DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
2877
            break;
2878

    
2879
        default:
2880
            DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
2881
            ret = 0;
2882
            break;
2883
    }
2884

    
2885
    return ret;
2886
}
2887

    
2888
static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
2889
{
2890
    RTL8139State *s = opaque;
2891
    uint32_t ret;
2892

    
2893
    addr &= 0xfe; /* mask lower bit */
2894

    
2895
    switch (addr)
2896
    {
2897
        case IntrMask:
2898
            ret = rtl8139_IntrMask_read(s);
2899
            break;
2900

    
2901
        case IntrStatus:
2902
            ret = rtl8139_IntrStatus_read(s);
2903
            break;
2904

    
2905
        case MultiIntr:
2906
            ret = rtl8139_MultiIntr_read(s);
2907
            break;
2908

    
2909
        case RxBufPtr:
2910
            ret = rtl8139_RxBufPtr_read(s);
2911
            break;
2912

    
2913
        case RxBufAddr:
2914
            ret = rtl8139_RxBufAddr_read(s);
2915
            break;
2916

    
2917
        case BasicModeCtrl:
2918
            ret = rtl8139_BasicModeCtrl_read(s);
2919
            break;
2920
        case BasicModeStatus:
2921
            ret = rtl8139_BasicModeStatus_read(s);
2922
            break;
2923
        case NWayAdvert:
2924
            ret = s->NWayAdvert;
2925
            DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
2926
            break;
2927
        case NWayLPAR:
2928
            ret = s->NWayLPAR;
2929
            DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
2930
            break;
2931
        case NWayExpansion:
2932
            ret = s->NWayExpansion;
2933
            DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
2934
            break;
2935

    
2936
        case CpCmd:
2937
            ret = rtl8139_CpCmd_read(s);
2938
            break;
2939

    
2940
        case IntrMitigate:
2941
            ret = rtl8139_IntrMitigate_read(s);
2942
            break;
2943

    
2944
        case TxSummary:
2945
            ret = rtl8139_TSAD_read(s);
2946
            break;
2947

    
2948
        case CSCR:
2949
            ret = rtl8139_CSCR_read(s);
2950
            break;
2951

    
2952
        default:
2953
            DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
2954

    
2955
            ret  = rtl8139_io_readb(opaque, addr);
2956
            ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
2957

    
2958
            DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
2959
            break;
2960
    }
2961

    
2962
    return ret;
2963
}
2964

    
2965
static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
2966
{
2967
    RTL8139State *s = opaque;
2968
    uint32_t ret;
2969

    
2970
    addr &= 0xfc; /* also mask low 2 bits */
2971

    
2972
    switch (addr)
2973
    {
2974
        case RxMissed:
2975
            ret = s->RxMissed;
2976

    
2977
            DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
2978
            break;
2979

    
2980
        case TxConfig:
2981
            ret = rtl8139_TxConfig_read(s);
2982
            break;
2983

    
2984
        case RxConfig:
2985
            ret = rtl8139_RxConfig_read(s);
2986
            break;
2987

    
2988
        case TxStatus0 ... TxStatus0+4*4-1:
2989
            ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
2990
            break;
2991

    
2992
        case TxAddr0 ... TxAddr0+4*4-1:
2993
            ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
2994
            break;
2995

    
2996
        case RxBuf:
2997
            ret = rtl8139_RxBuf_read(s);
2998
            break;
2999

    
3000
        case RxRingAddrLO:
3001
            ret = s->RxRingAddrLO;
3002
            DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
3003
            break;
3004

    
3005
        case RxRingAddrHI:
3006
            ret = s->RxRingAddrHI;
3007
            DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
3008
            break;
3009

    
3010
        case Timer:
3011
            ret = s->TCTR;
3012
            DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
3013
            break;
3014

    
3015
        case FlashReg:
3016
            ret = s->TimerInt;
3017
            DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
3018
            break;
3019

    
3020
        default:
3021
            DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
3022

    
3023
            ret  = rtl8139_io_readb(opaque, addr);
3024
            ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3025
            ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3026
            ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3027

    
3028
            DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
3029
            break;
3030
    }
3031

    
3032
    return ret;
3033
}
3034

    
3035
/* */
3036

    
3037
static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3038
{
3039
    rtl8139_io_writeb(opaque, addr & 0xFF, val);
3040
}
3041

    
3042
static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3043
{
3044
    rtl8139_io_writew(opaque, addr & 0xFF, val);
3045
}
3046

    
3047
static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3048
{
3049
    rtl8139_io_writel(opaque, addr & 0xFF, val);
3050
}
3051

    
3052
static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3053
{
3054
    return rtl8139_io_readb(opaque, addr & 0xFF);
3055
}
3056

    
3057
static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3058
{
3059
    return rtl8139_io_readw(opaque, addr & 0xFF);
3060
}
3061

    
3062
static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3063
{
3064
    return rtl8139_io_readl(opaque, addr & 0xFF);
3065
}
3066

    
3067
/* */
3068

    
3069
static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3070
{
3071
    rtl8139_io_writeb(opaque, addr & 0xFF, val);
3072
}
3073

    
3074
static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3075
{
3076
#ifdef TARGET_WORDS_BIGENDIAN
3077
    val = bswap16(val);
3078
#endif
3079
    rtl8139_io_writew(opaque, addr & 0xFF, val);
3080
}
3081

    
3082
static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3083
{
3084
#ifdef TARGET_WORDS_BIGENDIAN
3085
    val = bswap32(val);
3086
#endif
3087
    rtl8139_io_writel(opaque, addr & 0xFF, val);
3088
}
3089

    
3090
static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3091
{
3092
    return rtl8139_io_readb(opaque, addr & 0xFF);
3093
}
3094

    
3095
static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3096
{
3097
    uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
3098
#ifdef TARGET_WORDS_BIGENDIAN
3099
    val = bswap16(val);
3100
#endif
3101
    return val;
3102
}
3103

    
3104
static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3105
{
3106
    uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
3107
#ifdef TARGET_WORDS_BIGENDIAN
3108
    val = bswap32(val);
3109
#endif
3110
    return val;
3111
}
3112

    
3113
/* */
3114

    
3115
static void rtl8139_save(QEMUFile* f,void* opaque)
3116
{
3117
    RTL8139State* s=(RTL8139State*)opaque;
3118
    unsigned int i;
3119

    
3120
    pci_device_save(s->pci_dev, f);
3121

    
3122
    qemu_put_buffer(f, s->phys, 6);
3123
    qemu_put_buffer(f, s->mult, 8);
3124

    
3125
    for (i=0; i<4; ++i)
3126
    {
3127
        qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3128
    }
3129
    for (i=0; i<4; ++i)
3130
    {
3131
        qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3132
    }
3133

    
3134
    qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */
3135
    qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3136
    qemu_put_be32s(f, &s->RxBufPtr);
3137
    qemu_put_be32s(f, &s->RxBufAddr);
3138

    
3139
    qemu_put_be16s(f, &s->IntrStatus);
3140
    qemu_put_be16s(f, &s->IntrMask);
3141

    
3142
    qemu_put_be32s(f, &s->TxConfig);
3143
    qemu_put_be32s(f, &s->RxConfig);
3144
    qemu_put_be32s(f, &s->RxMissed);
3145
    qemu_put_be16s(f, &s->CSCR);
3146

    
3147
    qemu_put_8s(f, &s->Cfg9346);
3148
    qemu_put_8s(f, &s->Config0);
3149
    qemu_put_8s(f, &s->Config1);
3150
    qemu_put_8s(f, &s->Config3);
3151
    qemu_put_8s(f, &s->Config4);
3152
    qemu_put_8s(f, &s->Config5);
3153

    
3154
    qemu_put_8s(f, &s->clock_enabled);
3155
    qemu_put_8s(f, &s->bChipCmdState);
3156

    
3157
    qemu_put_be16s(f, &s->MultiIntr);
3158

    
3159
    qemu_put_be16s(f, &s->BasicModeCtrl);
3160
    qemu_put_be16s(f, &s->BasicModeStatus);
3161
    qemu_put_be16s(f, &s->NWayAdvert);
3162
    qemu_put_be16s(f, &s->NWayLPAR);
3163
    qemu_put_be16s(f, &s->NWayExpansion);
3164

    
3165
    qemu_put_be16s(f, &s->CpCmd);
3166
    qemu_put_8s(f, &s->TxThresh);
3167

    
3168
    i = 0;
3169
    qemu_put_be32s(f, &i); /* unused.  */
3170
    qemu_put_buffer(f, s->macaddr, 6);
3171
    qemu_put_be32(f, s->rtl8139_mmio_io_addr);
3172

    
3173
    qemu_put_be32s(f, &s->currTxDesc);
3174
    qemu_put_be32s(f, &s->currCPlusRxDesc);
3175
    qemu_put_be32s(f, &s->currCPlusTxDesc);
3176
    qemu_put_be32s(f, &s->RxRingAddrLO);
3177
    qemu_put_be32s(f, &s->RxRingAddrHI);
3178

    
3179
    for (i=0; i<EEPROM_9346_SIZE; ++i)
3180
    {
3181
        qemu_put_be16s(f, &s->eeprom.contents[i]);
3182
    }
3183
    qemu_put_be32(f, s->eeprom.mode);
3184
    qemu_put_be32s(f, &s->eeprom.tick);
3185
    qemu_put_8s(f, &s->eeprom.address);
3186
    qemu_put_be16s(f, &s->eeprom.input);
3187
    qemu_put_be16s(f, &s->eeprom.output);
3188

    
3189
    qemu_put_8s(f, &s->eeprom.eecs);
3190
    qemu_put_8s(f, &s->eeprom.eesk);
3191
    qemu_put_8s(f, &s->eeprom.eedi);
3192
    qemu_put_8s(f, &s->eeprom.eedo);
3193

    
3194
    qemu_put_be32s(f, &s->TCTR);
3195
    qemu_put_be32s(f, &s->TimerInt);
3196
    qemu_put_be64(f, s->TCTR_base);
3197

    
3198
    RTL8139TallyCounters_save(f, &s->tally_counters);
3199

    
3200
    qemu_put_be32s(f, &s->cplus_enabled);
3201
}
3202

    
3203
static int rtl8139_load(QEMUFile* f,void* opaque,int version_id)
3204
{
3205
    RTL8139State* s=(RTL8139State*)opaque;
3206
    unsigned int i;
3207
    int ret;
3208

    
3209
    /* just 2 versions for now */
3210
    if (version_id > 4)
3211
            return -EINVAL;
3212

    
3213
    if (version_id >= 3) {
3214
        ret = pci_device_load(s->pci_dev, f);
3215
        if (ret < 0)
3216
            return ret;
3217
    }
3218

    
3219
    /* saved since version 1 */
3220
    qemu_get_buffer(f, s->phys, 6);
3221
    qemu_get_buffer(f, s->mult, 8);
3222

    
3223
    for (i=0; i<4; ++i)
3224
    {
3225
        qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
3226
    }
3227
    for (i=0; i<4; ++i)
3228
    {
3229
        qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
3230
    }
3231

    
3232
    qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */
3233
    qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
3234
    qemu_get_be32s(f, &s->RxBufPtr);
3235
    qemu_get_be32s(f, &s->RxBufAddr);
3236

    
3237
    qemu_get_be16s(f, &s->IntrStatus);
3238
    qemu_get_be16s(f, &s->IntrMask);
3239

    
3240
    qemu_get_be32s(f, &s->TxConfig);
3241
    qemu_get_be32s(f, &s->RxConfig);
3242
    qemu_get_be32s(f, &s->RxMissed);
3243
    qemu_get_be16s(f, &s->CSCR);
3244

    
3245
    qemu_get_8s(f, &s->Cfg9346);
3246
    qemu_get_8s(f, &s->Config0);
3247
    qemu_get_8s(f, &s->Config1);
3248
    qemu_get_8s(f, &s->Config3);
3249
    qemu_get_8s(f, &s->Config4);
3250
    qemu_get_8s(f, &s->Config5);
3251

    
3252
    qemu_get_8s(f, &s->clock_enabled);
3253
    qemu_get_8s(f, &s->bChipCmdState);
3254

    
3255
    qemu_get_be16s(f, &s->MultiIntr);
3256

    
3257
    qemu_get_be16s(f, &s->BasicModeCtrl);
3258
    qemu_get_be16s(f, &s->BasicModeStatus);
3259
    qemu_get_be16s(f, &s->NWayAdvert);
3260
    qemu_get_be16s(f, &s->NWayLPAR);
3261
    qemu_get_be16s(f, &s->NWayExpansion);
3262

    
3263
    qemu_get_be16s(f, &s->CpCmd);
3264
    qemu_get_8s(f, &s->TxThresh);
3265

    
3266
    qemu_get_be32s(f, &i); /* unused.  */
3267
    qemu_get_buffer(f, s->macaddr, 6);
3268
    s->rtl8139_mmio_io_addr=qemu_get_be32(f);
3269

    
3270
    qemu_get_be32s(f, &s->currTxDesc);
3271
    qemu_get_be32s(f, &s->currCPlusRxDesc);
3272
    qemu_get_be32s(f, &s->currCPlusTxDesc);
3273
    qemu_get_be32s(f, &s->RxRingAddrLO);
3274
    qemu_get_be32s(f, &s->RxRingAddrHI);
3275

    
3276
    for (i=0; i<EEPROM_9346_SIZE; ++i)
3277
    {
3278
        qemu_get_be16s(f, &s->eeprom.contents[i]);
3279
    }
3280
    s->eeprom.mode=qemu_get_be32(f);
3281
    qemu_get_be32s(f, &s->eeprom.tick);
3282
    qemu_get_8s(f, &s->eeprom.address);
3283
    qemu_get_be16s(f, &s->eeprom.input);
3284
    qemu_get_be16s(f, &s->eeprom.output);
3285

    
3286
    qemu_get_8s(f, &s->eeprom.eecs);
3287
    qemu_get_8s(f, &s->eeprom.eesk);
3288
    qemu_get_8s(f, &s->eeprom.eedi);
3289
    qemu_get_8s(f, &s->eeprom.eedo);
3290

    
3291
    /* saved since version 2 */
3292
    if (version_id >= 2)
3293
    {
3294
        qemu_get_be32s(f, &s->TCTR);
3295
        qemu_get_be32s(f, &s->TimerInt);
3296
        s->TCTR_base=qemu_get_be64(f);
3297

    
3298
        RTL8139TallyCounters_load(f, &s->tally_counters);
3299
    }
3300
    else
3301
    {
3302
        /* not saved, use default */
3303
        s->TCTR = 0;
3304
        s->TimerInt = 0;
3305
        s->TCTR_base = 0;
3306

    
3307
        RTL8139TallyCounters_clear(&s->tally_counters);
3308
    }
3309

    
3310
    if (version_id >= 4) {
3311
        qemu_get_be32s(f, &s->cplus_enabled);
3312
    } else {
3313
        s->cplus_enabled = s->CpCmd != 0;
3314
    }
3315

    
3316
    return 0;
3317
}
3318

    
3319
/***********************************************************/
3320
/* PCI RTL8139 definitions */
3321

    
3322
typedef struct PCIRTL8139State {
3323
    PCIDevice dev;
3324
    RTL8139State rtl8139;
3325
} PCIRTL8139State;
3326

    
3327
static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
3328
                       uint32_t addr, uint32_t size, int type)
3329
{
3330
    PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3331
    RTL8139State *s = &d->rtl8139;
3332

    
3333
    cpu_register_physical_memory(addr + 0, 0x100, s->rtl8139_mmio_io_addr);
3334
}
3335

    
3336
static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
3337
                       uint32_t addr, uint32_t size, int type)
3338
{
3339
    PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
3340
    RTL8139State *s = &d->rtl8139;
3341

    
3342
    register_ioport_write(addr, 0x100, 1, rtl8139_ioport_writeb, s);
3343
    register_ioport_read( addr, 0x100, 1, rtl8139_ioport_readb,  s);
3344

    
3345
    register_ioport_write(addr, 0x100, 2, rtl8139_ioport_writew, s);
3346
    register_ioport_read( addr, 0x100, 2, rtl8139_ioport_readw,  s);
3347

    
3348
    register_ioport_write(addr, 0x100, 4, rtl8139_ioport_writel, s);
3349
    register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl,  s);
3350
}
3351

    
3352
static CPUReadMemoryFunc *rtl8139_mmio_read[3] = {
3353
    rtl8139_mmio_readb,
3354
    rtl8139_mmio_readw,
3355
    rtl8139_mmio_readl,
3356
};
3357

    
3358
static CPUWriteMemoryFunc *rtl8139_mmio_write[3] = {
3359
    rtl8139_mmio_writeb,
3360
    rtl8139_mmio_writew,
3361
    rtl8139_mmio_writel,
3362
};
3363

    
3364
static inline int64_t rtl8139_get_next_tctr_time(RTL8139State *s, int64_t current_time)
3365
{
3366
    int64_t next_time = current_time +
3367
        muldiv64(1, ticks_per_sec, PCI_FREQUENCY);
3368
    if (next_time <= current_time)
3369
        next_time = current_time + 1;
3370
    return next_time;
3371
}
3372

    
3373
#ifdef RTL8139_ONBOARD_TIMER
3374
static void rtl8139_timer(void *opaque)
3375
{
3376
    RTL8139State *s = opaque;
3377

    
3378
    int is_timeout = 0;
3379

    
3380
    int64_t  curr_time;
3381
    uint32_t curr_tick;
3382

    
3383
    if (!s->clock_enabled)
3384
    {
3385
        DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
3386
        return;
3387
    }
3388

    
3389
    curr_time = qemu_get_clock(vm_clock);
3390

    
3391
    curr_tick = muldiv64(curr_time - s->TCTR_base, PCI_FREQUENCY, ticks_per_sec);
3392

    
3393
    if (s->TimerInt && curr_tick >= s->TimerInt)
3394
    {
3395
        if (s->TCTR < s->TimerInt || curr_tick < s->TCTR)
3396
        {
3397
            is_timeout = 1;
3398
        }
3399
    }
3400

    
3401
    s->TCTR = curr_tick;
3402

    
3403
//  DEBUG_PRINT(("RTL8139: >>> timer: tick=%08u\n", s->TCTR));
3404

    
3405
    if (is_timeout)
3406
    {
3407
        DEBUG_PRINT(("RTL8139: >>> timer: timeout tick=%08u\n", s->TCTR));
3408
        s->IntrStatus |= PCSTimeout;
3409
        rtl8139_update_irq(s);
3410
    }
3411

    
3412
    qemu_mod_timer(s->timer,
3413
        rtl8139_get_next_tctr_time(s,curr_time));
3414
}
3415
#endif /* RTL8139_ONBOARD_TIMER */
3416

    
3417
static void rtl8139_cleanup(VLANClientState *vc)
3418
{
3419
    RTL8139State *s = vc->opaque;
3420

    
3421
    if (s->cplus_txbuffer) {
3422
        qemu_free(s->cplus_txbuffer);
3423
        s->cplus_txbuffer = NULL;
3424
    }
3425

    
3426
#ifdef RTL8139_ONBOARD_TIMER
3427
    qemu_del_timer(s->timer);
3428
    qemu_free_timer(s->timer);
3429
#endif
3430

    
3431
    unregister_savevm("rtl8139", s);
3432
}
3433

    
3434
static int pci_rtl8139_uninit(PCIDevice *dev)
3435
{
3436
    PCIRTL8139State *d = (PCIRTL8139State *)dev;
3437
    RTL8139State *s = &d->rtl8139;
3438

    
3439
    cpu_unregister_io_memory(s->rtl8139_mmio_io_addr);
3440

    
3441
    return 0;
3442
}
3443

    
3444
static void pci_rtl8139_init(PCIDevice *dev)
3445
{
3446
    PCIRTL8139State *d = (PCIRTL8139State *)dev;
3447
    RTL8139State *s;
3448
    uint8_t *pci_conf;
3449

    
3450
    d->dev.unregister = pci_rtl8139_uninit;
3451

    
3452
    pci_conf = d->dev.config;
3453
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
3454
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
3455
    pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
3456
    pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */
3457
    pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
3458
    pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* header_type */
3459
    pci_conf[0x3d] = 1;    /* interrupt pin 0 */
3460
    pci_conf[0x34] = 0xdc;
3461

    
3462
    s = &d->rtl8139;
3463

    
3464
    /* I/O handler for memory-mapped I/O */
3465
    s->rtl8139_mmio_io_addr =
3466
    cpu_register_io_memory(0, rtl8139_mmio_read, rtl8139_mmio_write, s);
3467

    
3468
    pci_register_io_region(&d->dev, 0, 0x100,
3469
                           PCI_ADDRESS_SPACE_IO,  rtl8139_ioport_map);
3470

    
3471
    pci_register_io_region(&d->dev, 1, 0x100,
3472
                           PCI_ADDRESS_SPACE_MEM, rtl8139_mmio_map);
3473

    
3474
    s->pci_dev = (PCIDevice *)d;
3475
    qdev_get_macaddr(&dev->qdev, s->macaddr);
3476
    rtl8139_reset(s);
3477
    s->vc = qdev_get_vlan_client(&dev->qdev,
3478
                                 rtl8139_can_receive, rtl8139_receive, NULL,
3479
                                 rtl8139_cleanup, s);
3480

    
3481
    qemu_format_nic_info_str(s->vc, s->macaddr);
3482

    
3483
    s->cplus_txbuffer = NULL;
3484
    s->cplus_txbuffer_len = 0;
3485
    s->cplus_txbuffer_offset = 0;
3486

    
3487
    register_savevm("rtl8139", -1, 4, rtl8139_save, rtl8139_load, s);
3488

    
3489
#ifdef RTL8139_ONBOARD_TIMER
3490
    s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
3491

    
3492
    qemu_mod_timer(s->timer,
3493
        rtl8139_get_next_tctr_time(s,qemu_get_clock(vm_clock)));
3494
#endif /* RTL8139_ONBOARD_TIMER */
3495
}
3496

    
3497
static void rtl8139_register_devices(void)
3498
{
3499
    pci_qdev_register("rtl8139", sizeof(PCIRTL8139State), pci_rtl8139_init);
3500
}
3501

    
3502
device_init(rtl8139_register_devices)