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/*
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* ARM Integrator CP System emulation.
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*
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* Copyright (c) 2005-2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL
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*/
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|
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#include "vl.h" |
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#include "arm_pic.h" |
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|
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#define KERNEL_ARGS_ADDR 0x100 |
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#define KERNEL_LOAD_ADDR 0x00010000 |
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#define INITRD_LOAD_ADDR 0x00800000 |
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|
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void DMA_run (void) |
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{ |
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} |
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|
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typedef struct { |
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uint32_t flash_offset; |
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uint32_t cm_osc; |
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uint32_t cm_ctrl; |
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uint32_t cm_lock; |
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uint32_t cm_auxosc; |
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uint32_t cm_sdram; |
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uint32_t cm_init; |
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uint32_t cm_flags; |
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uint32_t cm_nvflags; |
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uint32_t int_level; |
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uint32_t irq_enabled; |
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uint32_t fiq_enabled; |
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} integratorcm_state; |
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|
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static uint8_t integrator_spd[128] = { |
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128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1, |
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0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40 |
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}; |
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static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset) |
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{ |
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integratorcm_state *s = (integratorcm_state *)opaque; |
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offset -= 0x10000000;
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if (offset >= 0x100 && offset < 0x200) { |
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/* CM_SPD */
|
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if (offset >= 0x180) |
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return 0; |
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return integrator_spd[offset >> 2]; |
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} |
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switch (offset >> 2) { |
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case 0: /* CM_ID */ |
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return 0x411a3001; |
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case 1: /* CM_PROC */ |
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return 0; |
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case 2: /* CM_OSC */ |
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return s->cm_osc;
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case 3: /* CM_CTRL */ |
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return s->cm_ctrl;
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case 4: /* CM_STAT */ |
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return 0x00100000; |
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case 5: /* CM_LOCK */ |
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if (s->cm_lock == 0xa05f) { |
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return 0x1a05f; |
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} else {
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return s->cm_lock;
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} |
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case 6: /* CM_LMBUSCNT */ |
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/* ??? High frequency timer. */
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cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT");
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case 7: /* CM_AUXOSC */ |
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return s->cm_auxosc;
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case 8: /* CM_SDRAM */ |
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return s->cm_sdram;
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case 9: /* CM_INIT */ |
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return s->cm_init;
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case 10: /* CM_REFCT */ |
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/* ??? High frequency timer. */
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cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT");
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case 12: /* CM_FLAGS */ |
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return s->cm_flags;
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case 14: /* CM_NVFLAGS */ |
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return s->cm_nvflags;
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case 16: /* CM_IRQ_STAT */ |
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return s->int_level & s->irq_enabled;
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case 17: /* CM_IRQ_RSTAT */ |
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return s->int_level;
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case 18: /* CM_IRQ_ENSET */ |
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return s->irq_enabled;
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case 20: /* CM_SOFT_INTSET */ |
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return s->int_level & 1; |
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case 24: /* CM_FIQ_STAT */ |
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return s->int_level & s->fiq_enabled;
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case 25: /* CM_FIQ_RSTAT */ |
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return s->int_level;
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case 26: /* CM_FIQ_ENSET */ |
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return s->fiq_enabled;
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case 32: /* CM_VOLTAGE_CTL0 */ |
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case 33: /* CM_VOLTAGE_CTL1 */ |
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case 34: /* CM_VOLTAGE_CTL2 */ |
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case 35: /* CM_VOLTAGE_CTL3 */ |
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/* ??? Voltage control unimplemented. */
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return 0; |
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default:
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cpu_abort (cpu_single_env, |
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"integratorcm_read: Unimplemented offset 0x%x\n", offset);
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return 0; |
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} |
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} |
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|
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static void integratorcm_do_remap(integratorcm_state *s, int flash) |
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{ |
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if (flash) {
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cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM); |
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} else {
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cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM); |
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} |
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//??? tlb_flush (cpu_single_env, 1);
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} |
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|
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static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value) |
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{ |
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if (value & 8) { |
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cpu_abort(cpu_single_env, "Board reset\n");
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} |
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if ((s->cm_init ^ value) & 4) { |
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integratorcm_do_remap(s, (value & 4) == 0); |
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} |
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if ((s->cm_init ^ value) & 1) { |
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printf("Green LED %s\n", (value & 1) ? "on" : "off"); |
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} |
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s->cm_init = (s->cm_init & ~ 5) | (value ^ 5); |
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} |
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|
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static void integratorcm_update(integratorcm_state *s) |
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{ |
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/* ??? The CPU irq/fiq is raised when either the core module or base PIC
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are active. */
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if (s->int_level & (s->irq_enabled | s->fiq_enabled))
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cpu_abort(cpu_single_env, "Core module interrupt\n");
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} |
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|
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static void integratorcm_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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integratorcm_state *s = (integratorcm_state *)opaque; |
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offset -= 0x10000000;
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switch (offset >> 2) { |
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case 2: /* CM_OSC */ |
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if (s->cm_lock == 0xa05f) |
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s->cm_osc = value; |
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break;
|
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case 3: /* CM_CTRL */ |
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integratorcm_set_ctrl(s, value); |
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break;
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case 5: /* CM_LOCK */ |
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s->cm_lock = value & 0xffff;
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break;
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case 7: /* CM_AUXOSC */ |
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if (s->cm_lock == 0xa05f) |
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s->cm_auxosc = value; |
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break;
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case 8: /* CM_SDRAM */ |
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s->cm_sdram = value; |
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break;
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case 9: /* CM_INIT */ |
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/* ??? This can change the memory bus frequency. */
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s->cm_init = value; |
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break;
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case 12: /* CM_FLAGSS */ |
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s->cm_flags |= value; |
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break;
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case 13: /* CM_FLAGSC */ |
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s->cm_flags &= ~value; |
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break;
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case 14: /* CM_NVFLAGSS */ |
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s->cm_nvflags |= value; |
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break;
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case 15: /* CM_NVFLAGSS */ |
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s->cm_nvflags &= ~value; |
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break;
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case 18: /* CM_IRQ_ENSET */ |
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s->irq_enabled |= value; |
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integratorcm_update(s); |
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break;
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case 19: /* CM_IRQ_ENCLR */ |
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s->irq_enabled &= ~value; |
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integratorcm_update(s); |
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break;
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case 20: /* CM_SOFT_INTSET */ |
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s->int_level |= (value & 1);
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integratorcm_update(s); |
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break;
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case 21: /* CM_SOFT_INTCLR */ |
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s->int_level &= ~(value & 1);
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integratorcm_update(s); |
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break;
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case 26: /* CM_FIQ_ENSET */ |
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s->fiq_enabled |= value; |
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integratorcm_update(s); |
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break;
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case 27: /* CM_FIQ_ENCLR */ |
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s->fiq_enabled &= ~value; |
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integratorcm_update(s); |
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break;
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case 32: /* CM_VOLTAGE_CTL0 */ |
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case 33: /* CM_VOLTAGE_CTL1 */ |
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case 34: /* CM_VOLTAGE_CTL2 */ |
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case 35: /* CM_VOLTAGE_CTL3 */ |
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/* ??? Voltage control unimplemented. */
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break;
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default:
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cpu_abort (cpu_single_env, |
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"integratorcm_write: Unimplemented offset 0x%x\n", offset);
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break;
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} |
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} |
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|
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/* Integrator/CM control registers. */
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static CPUReadMemoryFunc *integratorcm_readfn[] = {
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integratorcm_read, |
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integratorcm_read, |
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integratorcm_read |
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}; |
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static CPUWriteMemoryFunc *integratorcm_writefn[] = {
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integratorcm_write, |
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integratorcm_write, |
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integratorcm_write |
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}; |
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static void integratorcm_init(int memsz, uint32_t flash_offset) |
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{ |
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int iomemtype;
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integratorcm_state *s; |
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s = (integratorcm_state *)qemu_mallocz(sizeof(integratorcm_state));
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s->cm_osc = 0x01000048;
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/* ??? What should the high bits of this value be? */
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s->cm_auxosc = 0x0007feff;
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s->cm_sdram = 0x00011122;
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if (memsz >= 256) { |
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integrator_spd[31] = 64; |
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s->cm_sdram |= 0x10;
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} else if (memsz >= 128) { |
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integrator_spd[31] = 32; |
248 |
s->cm_sdram |= 0x0c;
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} else if (memsz >= 64) { |
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integrator_spd[31] = 16; |
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s->cm_sdram |= 0x08;
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} else if (memsz >= 32) { |
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integrator_spd[31] = 4; |
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s->cm_sdram |= 0x04;
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} else {
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integrator_spd[31] = 2; |
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} |
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memcpy(integrator_spd + 73, "QEMU-MEMORY", 11); |
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s->cm_init = 0x00000112;
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s->flash_offset = flash_offset; |
261 |
|
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iomemtype = cpu_register_io_memory(0, integratorcm_readfn,
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integratorcm_writefn, s); |
264 |
cpu_register_physical_memory(0x10000000, 0x007fffff, iomemtype); |
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integratorcm_do_remap(s, 1);
|
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/* ??? Save/restore. */
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} |
268 |
|
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/* Integrator/CP hardware emulation. */
|
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/* Primary interrupt controller. */
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|
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typedef struct icp_pic_state |
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{ |
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arm_pic_handler handler; |
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uint32_t base; |
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uint32_t level; |
277 |
uint32_t irq_enabled; |
278 |
uint32_t fiq_enabled; |
279 |
void *parent;
|
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int parent_irq;
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int parent_fiq;
|
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} icp_pic_state; |
283 |
|
284 |
static void icp_pic_update(icp_pic_state *s) |
285 |
{ |
286 |
uint32_t flags; |
287 |
|
288 |
if (s->parent_irq != -1) { |
289 |
flags = (s->level & s->irq_enabled); |
290 |
pic_set_irq_new(s->parent, s->parent_irq, flags != 0);
|
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} |
292 |
if (s->parent_fiq != -1) { |
293 |
flags = (s->level & s->fiq_enabled); |
294 |
pic_set_irq_new(s->parent, s->parent_fiq, flags != 0);
|
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} |
296 |
} |
297 |
|
298 |
static void icp_pic_set_irq(void *opaque, int irq, int level) |
299 |
{ |
300 |
icp_pic_state *s = (icp_pic_state *)opaque; |
301 |
if (level)
|
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s->level |= 1 << irq;
|
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else
|
304 |
s->level &= ~(1 << irq);
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icp_pic_update(s); |
306 |
} |
307 |
|
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static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset) |
309 |
{ |
310 |
icp_pic_state *s = (icp_pic_state *)opaque; |
311 |
|
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offset -= s->base; |
313 |
switch (offset >> 2) { |
314 |
case 0: /* IRQ_STATUS */ |
315 |
return s->level & s->irq_enabled;
|
316 |
case 1: /* IRQ_RAWSTAT */ |
317 |
return s->level;
|
318 |
case 2: /* IRQ_ENABLESET */ |
319 |
return s->irq_enabled;
|
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case 4: /* INT_SOFTSET */ |
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return s->level & 1; |
322 |
case 8: /* FRQ_STATUS */ |
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return s->level & s->fiq_enabled;
|
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case 9: /* FRQ_RAWSTAT */ |
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return s->level;
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case 10: /* FRQ_ENABLESET */ |
327 |
return s->fiq_enabled;
|
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case 3: /* IRQ_ENABLECLR */ |
329 |
case 5: /* INT_SOFTCLR */ |
330 |
case 11: /* FRQ_ENABLECLR */ |
331 |
default:
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332 |
printf ("icp_pic_read: Bad register offset 0x%x\n", offset);
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return 0; |
334 |
} |
335 |
} |
336 |
|
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static void icp_pic_write(void *opaque, target_phys_addr_t offset, |
338 |
uint32_t value) |
339 |
{ |
340 |
icp_pic_state *s = (icp_pic_state *)opaque; |
341 |
offset -= s->base; |
342 |
|
343 |
switch (offset >> 2) { |
344 |
case 2: /* IRQ_ENABLESET */ |
345 |
s->irq_enabled |= value; |
346 |
break;
|
347 |
case 3: /* IRQ_ENABLECLR */ |
348 |
s->irq_enabled &= ~value; |
349 |
break;
|
350 |
case 4: /* INT_SOFTSET */ |
351 |
if (value & 1) |
352 |
pic_set_irq_new(s, 0, 1); |
353 |
break;
|
354 |
case 5: /* INT_SOFTCLR */ |
355 |
if (value & 1) |
356 |
pic_set_irq_new(s, 0, 0); |
357 |
break;
|
358 |
case 10: /* FRQ_ENABLESET */ |
359 |
s->fiq_enabled |= value; |
360 |
break;
|
361 |
case 11: /* FRQ_ENABLECLR */ |
362 |
s->fiq_enabled &= ~value; |
363 |
break;
|
364 |
case 0: /* IRQ_STATUS */ |
365 |
case 1: /* IRQ_RAWSTAT */ |
366 |
case 8: /* FRQ_STATUS */ |
367 |
case 9: /* FRQ_RAWSTAT */ |
368 |
default:
|
369 |
printf ("icp_pic_write: Bad register offset 0x%x\n", offset);
|
370 |
return;
|
371 |
} |
372 |
icp_pic_update(s); |
373 |
} |
374 |
|
375 |
static CPUReadMemoryFunc *icp_pic_readfn[] = {
|
376 |
icp_pic_read, |
377 |
icp_pic_read, |
378 |
icp_pic_read |
379 |
}; |
380 |
|
381 |
static CPUWriteMemoryFunc *icp_pic_writefn[] = {
|
382 |
icp_pic_write, |
383 |
icp_pic_write, |
384 |
icp_pic_write |
385 |
}; |
386 |
|
387 |
static icp_pic_state *icp_pic_init(uint32_t base, void *parent, |
388 |
int parent_irq, int parent_fiq) |
389 |
{ |
390 |
icp_pic_state *s; |
391 |
int iomemtype;
|
392 |
|
393 |
s = (icp_pic_state *)qemu_mallocz(sizeof(icp_pic_state));
|
394 |
if (!s)
|
395 |
return NULL; |
396 |
s->handler = icp_pic_set_irq; |
397 |
s->base = base; |
398 |
s->parent = parent; |
399 |
s->parent_irq = parent_irq; |
400 |
s->parent_fiq = parent_fiq; |
401 |
iomemtype = cpu_register_io_memory(0, icp_pic_readfn,
|
402 |
icp_pic_writefn, s); |
403 |
cpu_register_physical_memory(base, 0x007fffff, iomemtype);
|
404 |
/* ??? Save/restore. */
|
405 |
return s;
|
406 |
} |
407 |
|
408 |
/* CP control registers. */
|
409 |
typedef struct { |
410 |
uint32_t base; |
411 |
} icp_control_state; |
412 |
|
413 |
static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset) |
414 |
{ |
415 |
icp_control_state *s = (icp_control_state *)opaque; |
416 |
offset -= s->base; |
417 |
switch (offset >> 2) { |
418 |
case 0: /* CP_IDFIELD */ |
419 |
return 0x41034003; |
420 |
case 1: /* CP_FLASHPROG */ |
421 |
return 0; |
422 |
case 2: /* CP_INTREG */ |
423 |
return 0; |
424 |
case 3: /* CP_DECODE */ |
425 |
return 0x11; |
426 |
default:
|
427 |
cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n", offset);
|
428 |
return 0; |
429 |
} |
430 |
} |
431 |
|
432 |
static void icp_control_write(void *opaque, target_phys_addr_t offset, |
433 |
uint32_t value) |
434 |
{ |
435 |
icp_control_state *s = (icp_control_state *)opaque; |
436 |
offset -= s->base; |
437 |
switch (offset >> 2) { |
438 |
case 1: /* CP_FLASHPROG */ |
439 |
case 2: /* CP_INTREG */ |
440 |
case 3: /* CP_DECODE */ |
441 |
/* Nothing interesting implemented yet. */
|
442 |
break;
|
443 |
default:
|
444 |
cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n", offset);
|
445 |
} |
446 |
} |
447 |
static CPUReadMemoryFunc *icp_control_readfn[] = {
|
448 |
icp_control_read, |
449 |
icp_control_read, |
450 |
icp_control_read |
451 |
}; |
452 |
|
453 |
static CPUWriteMemoryFunc *icp_control_writefn[] = {
|
454 |
icp_control_write, |
455 |
icp_control_write, |
456 |
icp_control_write |
457 |
}; |
458 |
|
459 |
static void icp_control_init(uint32_t base) |
460 |
{ |
461 |
int iomemtype;
|
462 |
icp_control_state *s; |
463 |
|
464 |
s = (icp_control_state *)qemu_mallocz(sizeof(icp_control_state));
|
465 |
iomemtype = cpu_register_io_memory(0, icp_control_readfn,
|
466 |
icp_control_writefn, s); |
467 |
cpu_register_physical_memory(base, 0x007fffff, iomemtype);
|
468 |
s->base = base; |
469 |
/* ??? Save/restore. */
|
470 |
} |
471 |
|
472 |
|
473 |
/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
|
474 |
static uint32_t bootloader[] = {
|
475 |
0xe3a00000, /* mov r0, #0 */ |
476 |
0xe3a01013, /* mov r1, #0x13 */ |
477 |
0xe3811c01, /* orr r1, r1, #0x100 */ |
478 |
0xe59f2000, /* ldr r2, [pc, #0] */ |
479 |
0xe59ff000, /* ldr pc, [pc, #0] */ |
480 |
0, /* Address of kernel args. Set by integratorcp_init. */ |
481 |
0 /* Kernel entry point. Set by integratorcp_init. */ |
482 |
}; |
483 |
|
484 |
static void set_kernel_args(uint32_t ram_size, int initrd_size, |
485 |
const char *kernel_cmdline) |
486 |
{ |
487 |
uint32_t *p; |
488 |
|
489 |
p = (uint32_t *)(phys_ram_base + KERNEL_ARGS_ADDR); |
490 |
/* ATAG_CORE */
|
491 |
stl_raw(p++, 5);
|
492 |
stl_raw(p++, 0x54410001);
|
493 |
stl_raw(p++, 1);
|
494 |
stl_raw(p++, 0x1000);
|
495 |
stl_raw(p++, 0);
|
496 |
/* ATAG_MEM */
|
497 |
stl_raw(p++, 4);
|
498 |
stl_raw(p++, 0x54410002);
|
499 |
stl_raw(p++, ram_size); |
500 |
stl_raw(p++, 0);
|
501 |
if (initrd_size) {
|
502 |
/* ATAG_INITRD2 */
|
503 |
stl_raw(p++, 4);
|
504 |
stl_raw(p++, 0x54420005);
|
505 |
stl_raw(p++, INITRD_LOAD_ADDR); |
506 |
stl_raw(p++, initrd_size); |
507 |
} |
508 |
if (kernel_cmdline && *kernel_cmdline) {
|
509 |
/* ATAG_CMDLINE */
|
510 |
int cmdline_size;
|
511 |
|
512 |
cmdline_size = strlen(kernel_cmdline); |
513 |
memcpy (p + 2, kernel_cmdline, cmdline_size + 1); |
514 |
cmdline_size = (cmdline_size >> 2) + 1; |
515 |
stl_raw(p++, cmdline_size + 2);
|
516 |
stl_raw(p++, 0x54410009);
|
517 |
p += cmdline_size; |
518 |
} |
519 |
/* ATAG_END */
|
520 |
stl_raw(p++, 0);
|
521 |
stl_raw(p++, 0);
|
522 |
} |
523 |
|
524 |
/* Board init. */
|
525 |
|
526 |
static void integratorcp_init(int ram_size, int vga_ram_size, int boot_device, |
527 |
DisplayState *ds, const char **fd_filename, int snapshot, |
528 |
const char *kernel_filename, const char *kernel_cmdline, |
529 |
const char *initrd_filename, uint32_t cpuid) |
530 |
{ |
531 |
CPUState *env; |
532 |
uint32_t bios_offset; |
533 |
icp_pic_state *pic; |
534 |
void *cpu_pic;
|
535 |
int kernel_size;
|
536 |
int initrd_size;
|
537 |
int n;
|
538 |
|
539 |
env = cpu_init(); |
540 |
cpu_arm_set_model(env, cpuid); |
541 |
bios_offset = ram_size + vga_ram_size; |
542 |
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
|
543 |
/* ??? RAM shoud repeat to fill physical memory space. */
|
544 |
/* SDRAM at address zero*/
|
545 |
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
546 |
/* And again at address 0x80000000 */
|
547 |
cpu_register_physical_memory(0x80000000, ram_size, IO_MEM_RAM);
|
548 |
|
549 |
integratorcm_init(ram_size >> 20, bios_offset);
|
550 |
cpu_pic = arm_pic_init_cpu(env); |
551 |
pic = icp_pic_init(0x14000000, cpu_pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
|
552 |
icp_pic_init(0xca000000, pic, 26, -1); |
553 |
icp_pit_init(0x13000000, pic, 5); |
554 |
pl011_init(0x16000000, pic, 1, serial_hds[0]); |
555 |
pl011_init(0x17000000, pic, 2, serial_hds[1]); |
556 |
icp_control_init(0xcb000000);
|
557 |
pl050_init(0x18000000, pic, 3, 0); |
558 |
pl050_init(0x19000000, pic, 4, 1); |
559 |
if (nd_table[0].vlan) { |
560 |
if (nd_table[0].model == NULL |
561 |
|| strcmp(nd_table[0].model, "smc91c111") == 0) { |
562 |
smc91c111_init(&nd_table[0], 0xc8000000, pic, 27); |
563 |
} else {
|
564 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
565 |
exit (1);
|
566 |
} |
567 |
} |
568 |
pl110_init(ds, 0xc0000000, pic, 22, 0); |
569 |
|
570 |
/* Load the kernel. */
|
571 |
if (!kernel_filename) {
|
572 |
fprintf(stderr, "Kernel image must be specified\n");
|
573 |
exit(1);
|
574 |
} |
575 |
kernel_size = load_image(kernel_filename, |
576 |
phys_ram_base + KERNEL_LOAD_ADDR); |
577 |
if (kernel_size < 0) { |
578 |
fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
|
579 |
exit(1);
|
580 |
} |
581 |
if (initrd_filename) {
|
582 |
initrd_size = load_image(initrd_filename, |
583 |
phys_ram_base + INITRD_LOAD_ADDR); |
584 |
if (initrd_size < 0) { |
585 |
fprintf(stderr, "qemu: could not load initrd '%s'\n",
|
586 |
initrd_filename); |
587 |
exit(1);
|
588 |
} |
589 |
} else {
|
590 |
initrd_size = 0;
|
591 |
} |
592 |
bootloader[5] = KERNEL_ARGS_ADDR;
|
593 |
bootloader[6] = KERNEL_LOAD_ADDR;
|
594 |
for (n = 0; n < sizeof(bootloader) / 4; n++) |
595 |
stl_raw(phys_ram_base + (n * 4), bootloader[n]);
|
596 |
set_kernel_args(ram_size, initrd_size, kernel_cmdline); |
597 |
} |
598 |
|
599 |
static void integratorcp926_init(int ram_size, int vga_ram_size, |
600 |
int boot_device, DisplayState *ds, const char **fd_filename, int snapshot, |
601 |
const char *kernel_filename, const char *kernel_cmdline, |
602 |
const char *initrd_filename) |
603 |
{ |
604 |
integratorcp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename, |
605 |
snapshot, kernel_filename, kernel_cmdline, |
606 |
initrd_filename, ARM_CPUID_ARM926); |
607 |
} |
608 |
|
609 |
static void integratorcp1026_init(int ram_size, int vga_ram_size, |
610 |
int boot_device, DisplayState *ds, const char **fd_filename, int snapshot, |
611 |
const char *kernel_filename, const char *kernel_cmdline, |
612 |
const char *initrd_filename) |
613 |
{ |
614 |
integratorcp_init(ram_size, vga_ram_size, boot_device, ds, fd_filename, |
615 |
snapshot, kernel_filename, kernel_cmdline, |
616 |
initrd_filename, ARM_CPUID_ARM1026); |
617 |
} |
618 |
|
619 |
QEMUMachine integratorcp926_machine = { |
620 |
"integratorcp926",
|
621 |
"ARM Integrator/CP (ARM926EJ-S)",
|
622 |
integratorcp926_init, |
623 |
}; |
624 |
|
625 |
QEMUMachine integratorcp1026_machine = { |
626 |
"integratorcp1026",
|
627 |
"ARM Integrator/CP (ARM1026EJ-S)",
|
628 |
integratorcp1026_init, |
629 |
}; |