root / target-sh4 / cpu.h @ ce5232c5
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/*
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* SH4 emulation
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*
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* Copyright (c) 2005 Samuel Tardieu
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _CPU_SH4_H
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#define _CPU_SH4_H
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#include "config.h" |
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#define TARGET_LONG_BITS 32 |
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#define TARGET_HAS_ICE 1 |
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#define ELF_MACHINE EM_SH
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#include "cpu-defs.h" |
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#include "softfloat.h" |
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#define TARGET_PAGE_BITS 12 /* 4k XXXXX */ |
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#define SR_MD (1 << 30) |
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#define SR_RB (1 << 29) |
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#define SR_BL (1 << 28) |
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#define SR_FD (1 << 15) |
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#define SR_M (1 << 9) |
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#define SR_Q (1 << 8) |
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#define SR_S (1 << 1) |
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#define SR_T (1 << 0) |
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#define FPSCR_FR (1 << 21) |
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#define FPSCR_SZ (1 << 20) |
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#define FPSCR_PR (1 << 19) |
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#define FPSCR_DN (1 << 18) |
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#define DELAY_SLOT (1 << 0) |
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#define DELAY_SLOT_CONDITIONAL (1 << 1) |
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#define DELAY_SLOT_TRUE (1 << 2) |
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#define DELAY_SLOT_CLEARME (1 << 3) |
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/* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump
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* after the delay slot should be taken or not. It is calculated from SR_T.
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*
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* It is unclear if it is permitted to modify the SR_T flag in a delay slot.
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* The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification.
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*/
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/* XXXXX The structure could be made more compact */
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typedef struct tlb_t { |
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uint8_t asid; /* address space identifier */
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uint32_t vpn; /* virtual page number */
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uint8_t v; /* validity */
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uint32_t ppn; /* physical page number */
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uint8_t sz; /* page size */
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uint32_t size; /* cached page size in bytes */
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uint8_t sh; /* share status */
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uint8_t c; /* cacheability */
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uint8_t pr; /* protection key */
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uint8_t d; /* dirty */
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uint8_t wt; /* write through */
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uint8_t sa; /* space attribute (PCMCIA) */
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uint8_t tc; /* timing control */
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} tlb_t; |
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#define UTLB_SIZE 64 |
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#define ITLB_SIZE 4 |
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#define NB_MMU_MODES 2 |
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typedef struct CPUSH4State { |
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uint32_t flags; /* general execution flags */
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uint32_t gregs[24]; /* general registers */ |
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float32 fregs[32]; /* floating point registers */ |
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uint32_t sr; /* status register */
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uint32_t ssr; /* saved status register */
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uint32_t spc; /* saved program counter */
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uint32_t gbr; /* global base register */
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uint32_t vbr; /* vector base register */
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uint32_t sgr; /* saved global register 15 */
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uint32_t dbr; /* debug base register */
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uint32_t pc; /* program counter */
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uint32_t delayed_pc; /* target of delayed jump */
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uint32_t mach; /* multiply and accumulate high */
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uint32_t macl; /* multiply and accumulate low */
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uint32_t pr; /* procedure register */
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uint32_t fpscr; /* floating point status/control register */
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uint32_t fpul; /* floating point communication register */
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/* temporary float registers */
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float32 ft0, ft1; |
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float64 dt0, dt1; |
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float_status fp_status; |
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/* Those belong to the specific unit (SH7750) but are handled here */
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uint32_t mmucr; /* MMU control register */
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uint32_t pteh; /* page table entry high register */
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uint32_t ptel; /* page table entry low register */
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uint32_t ptea; /* page table entry assistance register */
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uint32_t ttb; /* tranlation table base register */
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uint32_t tea; /* TLB exception address register */
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uint32_t tra; /* TRAPA exception register */
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uint32_t expevt; /* exception event register */
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uint32_t intevt; /* interrupt event register */
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jmp_buf jmp_env; |
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int user_mode_only;
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int interrupt_request;
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int exception_index;
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CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
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tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
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void *intc_handle;
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} CPUSH4State; |
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CPUSH4State *cpu_sh4_init(const char *cpu_model); |
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int cpu_sh4_exec(CPUSH4State * s);
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int cpu_sh4_signal_handler(int host_signum, void *pinfo, |
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void *puc);
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#include "softfloat.h" |
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#define CPUState CPUSH4State
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#define cpu_init cpu_sh4_init
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#define cpu_exec cpu_sh4_exec
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#define cpu_gen_code cpu_sh4_gen_code
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#define cpu_signal_handler cpu_sh4_signal_handler
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
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#define MMU_USER_IDX 1 |
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static inline int cpu_mmu_index (CPUState *env) |
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{ |
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return (env->sr & SR_MD) == 0 ? 1 : 0; |
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} |
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#include "cpu-all.h" |
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/* Memory access type */
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enum {
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/* Privilege */
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ACCESS_PRIV = 0x01,
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/* Direction */
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ACCESS_WRITE = 0x02,
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/* Type of instruction */
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ACCESS_CODE = 0x10,
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ACCESS_INT = 0x20
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}; |
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/* MMU control register */
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#define MMUCR 0x1F000010 |
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#define MMUCR_AT (1<<0) |
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#define MMUCR_SV (1<<8) |
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#define MMUCR_URC_BITS (6) |
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#define MMUCR_URC_OFFSET (10) |
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#define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS) |
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#define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET) |
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static inline int cpu_mmucr_urc (uint32_t mmucr) |
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{ |
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return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET);
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} |
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/* PTEH : Page Translation Entry High register */
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#define PTEH_ASID_BITS (8) |
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#define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS) |
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#define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1) |
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#define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK)
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#define PTEH_VPN_BITS (22) |
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#define PTEH_VPN_OFFSET (10) |
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#define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS) |
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#define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET) |
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static inline int cpu_pteh_vpn (uint32_t pteh) |
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{ |
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return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET);
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} |
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/* PTEL : Page Translation Entry Low register */
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#define PTEL_V (1 << 8) |
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#define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8) |
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#define PTEL_C (1 << 3) |
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#define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3) |
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#define PTEL_D (1 << 2) |
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#define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2) |
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#define PTEL_SH (1 << 1) |
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#define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1) |
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#define PTEL_WT (1 << 0) |
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#define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT)
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#define PTEL_SZ_HIGH_OFFSET (7) |
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#define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET) |
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#define PTEL_SZ_LOW_OFFSET (4) |
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#define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET) |
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static inline int cpu_ptel_sz (uint32_t ptel) |
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{ |
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int sz;
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sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET; |
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sz <<= 1;
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sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET; |
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return sz;
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} |
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#define PTEL_PPN_BITS (19) |
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#define PTEL_PPN_OFFSET (10) |
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#define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS) |
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#define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET) |
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static inline int cpu_ptel_ppn (uint32_t ptel) |
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{ |
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return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET);
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} |
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#define PTEL_PR_BITS (2) |
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#define PTEL_PR_OFFSET (5) |
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#define PTEL_PR_SIZE (1 << PTEL_PR_BITS) |
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#define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET) |
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static inline int cpu_ptel_pr (uint32_t ptel) |
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{ |
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return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET);
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} |
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/* PTEA : Page Translation Entry Assistance register */
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#define PTEA_SA_BITS (3) |
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#define PTEA_SA_SIZE (1 << PTEA_SA_BITS) |
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#define PTEA_SA_MASK (PTEA_SA_SIZE - 1) |
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#define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK)
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#define PTEA_TC (1 << 3) |
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#define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) |
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#endif /* _CPU_SH4_H */ |