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1	7a3f1944	bellard	/*
2	7a3f1944	bellard	SPARC translation
3	7a3f1944	bellard
4	7a3f1944	bellard	Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5	3475187d	bellard	Copyright (C) 2003-2005 Fabrice Bellard
6	7a3f1944	bellard
7	7a3f1944	bellard	This library is free software; you can redistribute it and/or
8	7a3f1944	bellard	modify it under the terms of the GNU Lesser General Public
9	7a3f1944	bellard	License as published by the Free Software Foundation; either
10	7a3f1944	bellard	version 2 of the License, or (at your option) any later version.
11	7a3f1944	bellard
12	7a3f1944	bellard	This library is distributed in the hope that it will be useful,
13	7a3f1944	bellard	but WITHOUT ANY WARRANTY; without even the implied warranty of
14	7a3f1944	bellard	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15	7a3f1944	bellard	Lesser General Public License for more details.
16	7a3f1944	bellard
17	7a3f1944	bellard	You should have received a copy of the GNU Lesser General Public
18	7a3f1944	bellard	License along with this library; if not, write to the Free Software
19	7a3f1944	bellard	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20	7a3f1944	bellard	*/
21	7a3f1944	bellard
22	7a3f1944	bellard	/*
23	7a3f1944	bellard	TODO-list:
24	7a3f1944	bellard
25	3475187d	bellard	Rest of V9 instructions, VIS instructions
26	bd497938	bellard	NPC/PC static optimisations (use JUMP_TB when possible)
27	7a3f1944	bellard	Optimize synthetic instructions
28	3475187d	bellard	128-bit float
29	bd497938	bellard	*/
30	7a3f1944	bellard
31	7a3f1944	bellard	#include <stdarg.h>
32	7a3f1944	bellard	#include <stdlib.h>
33	7a3f1944	bellard	#include <stdio.h>
34	7a3f1944	bellard	#include <string.h>
35	7a3f1944	bellard	#include <inttypes.h>
36	7a3f1944	bellard
37	7a3f1944	bellard	#include "cpu.h"
38	7a3f1944	bellard	#include "exec-all.h"
39	7a3f1944	bellard	#include "disas.h"
40	7a3f1944	bellard
41	7a3f1944	bellard	#define DEBUG_DISAS
42	7a3f1944	bellard
43	72cbca10	bellard	#define DYNAMIC_PC 1 /* dynamic pc value */
44	72cbca10	bellard	#define JUMP_PC 2 /* dynamic pc value which takes only two values
45	72cbca10	bellard	according to jump_pc[T2] */
46	72cbca10	bellard
47	7a3f1944	bellard	typedef struct DisasContext {
48	72cbca10	bellard	target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
49	72cbca10	bellard	target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
50	72cbca10	bellard	target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
51	cf495bcf	bellard	int is_br;
52	e8af50a3	bellard	int mem_idx;
53	a80dde08	bellard	int fpu_enabled;
54	cf495bcf	bellard	struct TranslationBlock *tb;
55	7a3f1944	bellard	} DisasContext;
56	7a3f1944	bellard
57	62724a37	blueswir1	struct sparc_def_t {
58	62724a37	blueswir1	const unsigned char *name;
59	62724a37	blueswir1	target_ulong iu_version;
60	62724a37	blueswir1	uint32_t fpu_version;
61	62724a37	blueswir1	uint32_t mmu_version;
62	62724a37	blueswir1	};
63	62724a37	blueswir1
64	7a3f1944	bellard	static uint16_t *gen_opc_ptr;
65	7a3f1944	bellard	static uint32_t *gen_opparam_ptr;
66	7a3f1944	bellard	extern FILE *logfile;
67	7a3f1944	bellard	extern int loglevel;
68	7a3f1944	bellard
69	7a3f1944	bellard	enum {
70	7a3f1944	bellard	#define DEF(s,n,copy_size) INDEX_op_ ## s,
71	7a3f1944	bellard	#include "opc.h"
72	7a3f1944	bellard	#undef DEF
73	cf495bcf	bellard	NB_OPS
74	7a3f1944	bellard	};
75	7a3f1944	bellard
76	7a3f1944	bellard	#include "gen-op.h"
77	7a3f1944	bellard
78	3475187d	bellard	// This function uses non-native bit order
79	7a3f1944	bellard	#define GET_FIELD(X, FROM, TO) \
80	7a3f1944	bellard	((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
81	7a3f1944	bellard
82	3475187d	bellard	// This function uses the order in the manuals, i.e. bit 0 is 2^0
83	3475187d	bellard	#define GET_FIELD_SP(X, FROM, TO) \
84	3475187d	bellard	GET_FIELD(X, 31 - (TO), 31 - (FROM))
85	3475187d	bellard
86	3475187d	bellard	#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
87	46d38ba8	blueswir1	#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
88	3475187d	bellard
89	3475187d	bellard	#ifdef TARGET_SPARC64
90	3475187d	bellard	#define DFPREG(r) (((r & 1) << 6) \| (r & 0x1e))
91	3475187d	bellard	#else
92	c185970a	blueswir1	#define DFPREG(r) (r & 0x1e)
93	3475187d	bellard	#endif
94	3475187d	bellard
95	83469015	bellard	#ifdef USE_DIRECT_JUMP
96	83469015	bellard	#define TBPARAM(x)
97	83469015	bellard	#else
98	83469015	bellard	#define TBPARAM(x) (long)(x)
99	83469015	bellard	#endif
100	83469015	bellard
101	3475187d	bellard	static int sign_extend(int x, int len)
102	3475187d	bellard	{
103	3475187d	bellard	len = 32 - len;
104	3475187d	bellard	return (x << len) >> len;
105	3475187d	bellard	}
106	3475187d	bellard
107	7a3f1944	bellard	#define IS_IMM (insn & (1<<13))
108	7a3f1944	bellard
109	cf495bcf	bellard	static void disas_sparc_insn(DisasContext * dc);
110	7a3f1944	bellard
111	a68156d0	blueswir1	static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {
112	cf495bcf	bellard	{
113	cf495bcf	bellard	gen_op_movl_g0_T0,
114	cf495bcf	bellard	gen_op_movl_g1_T0,
115	cf495bcf	bellard	gen_op_movl_g2_T0,
116	cf495bcf	bellard	gen_op_movl_g3_T0,
117	cf495bcf	bellard	gen_op_movl_g4_T0,
118	cf495bcf	bellard	gen_op_movl_g5_T0,
119	cf495bcf	bellard	gen_op_movl_g6_T0,
120	cf495bcf	bellard	gen_op_movl_g7_T0,
121	cf495bcf	bellard	gen_op_movl_o0_T0,
122	cf495bcf	bellard	gen_op_movl_o1_T0,
123	cf495bcf	bellard	gen_op_movl_o2_T0,
124	cf495bcf	bellard	gen_op_movl_o3_T0,
125	cf495bcf	bellard	gen_op_movl_o4_T0,
126	cf495bcf	bellard	gen_op_movl_o5_T0,
127	cf495bcf	bellard	gen_op_movl_o6_T0,
128	cf495bcf	bellard	gen_op_movl_o7_T0,
129	cf495bcf	bellard	gen_op_movl_l0_T0,
130	cf495bcf	bellard	gen_op_movl_l1_T0,
131	cf495bcf	bellard	gen_op_movl_l2_T0,
132	cf495bcf	bellard	gen_op_movl_l3_T0,
133	cf495bcf	bellard	gen_op_movl_l4_T0,
134	cf495bcf	bellard	gen_op_movl_l5_T0,
135	cf495bcf	bellard	gen_op_movl_l6_T0,
136	cf495bcf	bellard	gen_op_movl_l7_T0,
137	cf495bcf	bellard	gen_op_movl_i0_T0,
138	cf495bcf	bellard	gen_op_movl_i1_T0,
139	cf495bcf	bellard	gen_op_movl_i2_T0,
140	cf495bcf	bellard	gen_op_movl_i3_T0,
141	cf495bcf	bellard	gen_op_movl_i4_T0,
142	cf495bcf	bellard	gen_op_movl_i5_T0,
143	cf495bcf	bellard	gen_op_movl_i6_T0,
144	cf495bcf	bellard	gen_op_movl_i7_T0,
145	cf495bcf	bellard	},
146	cf495bcf	bellard	{
147	cf495bcf	bellard	gen_op_movl_g0_T1,
148	cf495bcf	bellard	gen_op_movl_g1_T1,
149	cf495bcf	bellard	gen_op_movl_g2_T1,
150	cf495bcf	bellard	gen_op_movl_g3_T1,
151	cf495bcf	bellard	gen_op_movl_g4_T1,
152	cf495bcf	bellard	gen_op_movl_g5_T1,
153	cf495bcf	bellard	gen_op_movl_g6_T1,
154	cf495bcf	bellard	gen_op_movl_g7_T1,
155	cf495bcf	bellard	gen_op_movl_o0_T1,
156	cf495bcf	bellard	gen_op_movl_o1_T1,
157	cf495bcf	bellard	gen_op_movl_o2_T1,
158	cf495bcf	bellard	gen_op_movl_o3_T1,
159	cf495bcf	bellard	gen_op_movl_o4_T1,
160	cf495bcf	bellard	gen_op_movl_o5_T1,
161	cf495bcf	bellard	gen_op_movl_o6_T1,
162	cf495bcf	bellard	gen_op_movl_o7_T1,
163	cf495bcf	bellard	gen_op_movl_l0_T1,
164	cf495bcf	bellard	gen_op_movl_l1_T1,
165	cf495bcf	bellard	gen_op_movl_l2_T1,
166	cf495bcf	bellard	gen_op_movl_l3_T1,
167	cf495bcf	bellard	gen_op_movl_l4_T1,
168	cf495bcf	bellard	gen_op_movl_l5_T1,
169	cf495bcf	bellard	gen_op_movl_l6_T1,
170	cf495bcf	bellard	gen_op_movl_l7_T1,
171	cf495bcf	bellard	gen_op_movl_i0_T1,
172	cf495bcf	bellard	gen_op_movl_i1_T1,
173	cf495bcf	bellard	gen_op_movl_i2_T1,
174	cf495bcf	bellard	gen_op_movl_i3_T1,
175	cf495bcf	bellard	gen_op_movl_i4_T1,
176	cf495bcf	bellard	gen_op_movl_i5_T1,
177	cf495bcf	bellard	gen_op_movl_i6_T1,
178	cf495bcf	bellard	gen_op_movl_i7_T1,
179	cf495bcf	bellard	}
180	7a3f1944	bellard	};
181	7a3f1944	bellard
182	a68156d0	blueswir1	static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {
183	cf495bcf	bellard	{
184	cf495bcf	bellard	gen_op_movl_T0_g0,
185	cf495bcf	bellard	gen_op_movl_T0_g1,
186	cf495bcf	bellard	gen_op_movl_T0_g2,
187	cf495bcf	bellard	gen_op_movl_T0_g3,
188	cf495bcf	bellard	gen_op_movl_T0_g4,
189	cf495bcf	bellard	gen_op_movl_T0_g5,
190	cf495bcf	bellard	gen_op_movl_T0_g6,
191	cf495bcf	bellard	gen_op_movl_T0_g7,
192	cf495bcf	bellard	gen_op_movl_T0_o0,
193	cf495bcf	bellard	gen_op_movl_T0_o1,
194	cf495bcf	bellard	gen_op_movl_T0_o2,
195	cf495bcf	bellard	gen_op_movl_T0_o3,
196	cf495bcf	bellard	gen_op_movl_T0_o4,
197	cf495bcf	bellard	gen_op_movl_T0_o5,
198	cf495bcf	bellard	gen_op_movl_T0_o6,
199	cf495bcf	bellard	gen_op_movl_T0_o7,
200	cf495bcf	bellard	gen_op_movl_T0_l0,
201	cf495bcf	bellard	gen_op_movl_T0_l1,
202	cf495bcf	bellard	gen_op_movl_T0_l2,
203	cf495bcf	bellard	gen_op_movl_T0_l3,
204	cf495bcf	bellard	gen_op_movl_T0_l4,
205	cf495bcf	bellard	gen_op_movl_T0_l5,
206	cf495bcf	bellard	gen_op_movl_T0_l6,
207	cf495bcf	bellard	gen_op_movl_T0_l7,
208	cf495bcf	bellard	gen_op_movl_T0_i0,
209	cf495bcf	bellard	gen_op_movl_T0_i1,
210	cf495bcf	bellard	gen_op_movl_T0_i2,
211	cf495bcf	bellard	gen_op_movl_T0_i3,
212	cf495bcf	bellard	gen_op_movl_T0_i4,
213	cf495bcf	bellard	gen_op_movl_T0_i5,
214	cf495bcf	bellard	gen_op_movl_T0_i6,
215	cf495bcf	bellard	gen_op_movl_T0_i7,
216	cf495bcf	bellard	},
217	cf495bcf	bellard	{
218	cf495bcf	bellard	gen_op_movl_T1_g0,
219	cf495bcf	bellard	gen_op_movl_T1_g1,
220	cf495bcf	bellard	gen_op_movl_T1_g2,
221	cf495bcf	bellard	gen_op_movl_T1_g3,
222	cf495bcf	bellard	gen_op_movl_T1_g4,
223	cf495bcf	bellard	gen_op_movl_T1_g5,
224	cf495bcf	bellard	gen_op_movl_T1_g6,
225	cf495bcf	bellard	gen_op_movl_T1_g7,
226	cf495bcf	bellard	gen_op_movl_T1_o0,
227	cf495bcf	bellard	gen_op_movl_T1_o1,
228	cf495bcf	bellard	gen_op_movl_T1_o2,
229	cf495bcf	bellard	gen_op_movl_T1_o3,
230	cf495bcf	bellard	gen_op_movl_T1_o4,
231	cf495bcf	bellard	gen_op_movl_T1_o5,
232	cf495bcf	bellard	gen_op_movl_T1_o6,
233	cf495bcf	bellard	gen_op_movl_T1_o7,
234	cf495bcf	bellard	gen_op_movl_T1_l0,
235	cf495bcf	bellard	gen_op_movl_T1_l1,
236	cf495bcf	bellard	gen_op_movl_T1_l2,
237	cf495bcf	bellard	gen_op_movl_T1_l3,
238	cf495bcf	bellard	gen_op_movl_T1_l4,
239	cf495bcf	bellard	gen_op_movl_T1_l5,
240	cf495bcf	bellard	gen_op_movl_T1_l6,
241	cf495bcf	bellard	gen_op_movl_T1_l7,
242	cf495bcf	bellard	gen_op_movl_T1_i0,
243	cf495bcf	bellard	gen_op_movl_T1_i1,
244	cf495bcf	bellard	gen_op_movl_T1_i2,
245	cf495bcf	bellard	gen_op_movl_T1_i3,
246	cf495bcf	bellard	gen_op_movl_T1_i4,
247	cf495bcf	bellard	gen_op_movl_T1_i5,
248	cf495bcf	bellard	gen_op_movl_T1_i6,
249	cf495bcf	bellard	gen_op_movl_T1_i7,
250	cf495bcf	bellard	},
251	cf495bcf	bellard	{
252	cf495bcf	bellard	gen_op_movl_T2_g0,
253	cf495bcf	bellard	gen_op_movl_T2_g1,
254	cf495bcf	bellard	gen_op_movl_T2_g2,
255	cf495bcf	bellard	gen_op_movl_T2_g3,
256	cf495bcf	bellard	gen_op_movl_T2_g4,
257	cf495bcf	bellard	gen_op_movl_T2_g5,
258	cf495bcf	bellard	gen_op_movl_T2_g6,
259	cf495bcf	bellard	gen_op_movl_T2_g7,
260	cf495bcf	bellard	gen_op_movl_T2_o0,
261	cf495bcf	bellard	gen_op_movl_T2_o1,
262	cf495bcf	bellard	gen_op_movl_T2_o2,
263	cf495bcf	bellard	gen_op_movl_T2_o3,
264	cf495bcf	bellard	gen_op_movl_T2_o4,
265	cf495bcf	bellard	gen_op_movl_T2_o5,
266	cf495bcf	bellard	gen_op_movl_T2_o6,
267	cf495bcf	bellard	gen_op_movl_T2_o7,
268	cf495bcf	bellard	gen_op_movl_T2_l0,
269	cf495bcf	bellard	gen_op_movl_T2_l1,
270	cf495bcf	bellard	gen_op_movl_T2_l2,
271	cf495bcf	bellard	gen_op_movl_T2_l3,
272	cf495bcf	bellard	gen_op_movl_T2_l4,
273	cf495bcf	bellard	gen_op_movl_T2_l5,
274	cf495bcf	bellard	gen_op_movl_T2_l6,
275	cf495bcf	bellard	gen_op_movl_T2_l7,
276	cf495bcf	bellard	gen_op_movl_T2_i0,
277	cf495bcf	bellard	gen_op_movl_T2_i1,
278	cf495bcf	bellard	gen_op_movl_T2_i2,
279	cf495bcf	bellard	gen_op_movl_T2_i3,
280	cf495bcf	bellard	gen_op_movl_T2_i4,
281	cf495bcf	bellard	gen_op_movl_T2_i5,
282	cf495bcf	bellard	gen_op_movl_T2_i6,
283	cf495bcf	bellard	gen_op_movl_T2_i7,
284	cf495bcf	bellard	}
285	7a3f1944	bellard	};
286	7a3f1944	bellard
287	a68156d0	blueswir1	static GenOpFunc1 * const gen_op_movl_TN_im[3] = {
288	cf495bcf	bellard	gen_op_movl_T0_im,
289	cf495bcf	bellard	gen_op_movl_T1_im,
290	cf495bcf	bellard	gen_op_movl_T2_im
291	7a3f1944	bellard	};
292	7a3f1944	bellard
293	3475187d	bellard	// Sign extending version
294	3475187d	bellard	static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
295	3475187d	bellard	gen_op_movl_T0_sim,
296	3475187d	bellard	gen_op_movl_T1_sim,
297	3475187d	bellard	gen_op_movl_T2_sim
298	3475187d	bellard	};
299	3475187d	bellard
300	3475187d	bellard	#ifdef TARGET_SPARC64
301	3475187d	bellard	#define GEN32(func, NAME) \
302	a68156d0	blueswir1	static GenOpFunc * const NAME ## _table [64] = { \
303	3475187d	bellard	NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
304	3475187d	bellard	NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
305	3475187d	bellard	NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
306	3475187d	bellard	NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
307	3475187d	bellard	NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
308	3475187d	bellard	NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
309	3475187d	bellard	NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
310	3475187d	bellard	NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
311	3475187d	bellard	NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
312	3475187d	bellard	NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
313	3475187d	bellard	NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
314	3475187d	bellard	NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
315	3475187d	bellard	}; \
316	3475187d	bellard	static inline void func(int n) \
317	3475187d	bellard	{ \
318	3475187d	bellard	NAME ## _table[n](); \
319	3475187d	bellard	}
320	3475187d	bellard	#else
321	e8af50a3	bellard	#define GEN32(func, NAME) \
322	a68156d0	blueswir1	static GenOpFunc *const NAME ## _table [32] = { \
323	e8af50a3	bellard	NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
324	e8af50a3	bellard	NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
325	e8af50a3	bellard	NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
326	e8af50a3	bellard	NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
327	e8af50a3	bellard	NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
328	e8af50a3	bellard	NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
329	e8af50a3	bellard	NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
330	e8af50a3	bellard	NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
331	e8af50a3	bellard	}; \
332	e8af50a3	bellard	static inline void func(int n) \
333	e8af50a3	bellard	{ \
334	e8af50a3	bellard	NAME ## _table[n](); \
335	e8af50a3	bellard	}
336	3475187d	bellard	#endif
337	e8af50a3	bellard
338	e8af50a3	bellard	/* floating point registers moves */
339	e8af50a3	bellard	GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
340	e8af50a3	bellard	GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
341	e8af50a3	bellard	GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
342	e8af50a3	bellard	GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
343	e8af50a3	bellard
344	e8af50a3	bellard	GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
345	e8af50a3	bellard	GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
346	e8af50a3	bellard	GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
347	e8af50a3	bellard	GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
348	e8af50a3	bellard
349	6ea4a6c8	blueswir1	#ifdef ALIGN_7_BUGS_FIXED
350	6ea4a6c8	blueswir1	#else
351	6ea4a6c8	blueswir1	#ifndef CONFIG_USER_ONLY
352	6ea4a6c8	blueswir1	#define gen_op_check_align_T0_7()
353	6ea4a6c8	blueswir1	#endif
354	6ea4a6c8	blueswir1	#endif
355	6ea4a6c8	blueswir1
356	3475187d	bellard	#ifdef TARGET_SPARC64
357	3475187d	bellard	// 'a' versions allowed to user depending on asi
358	3475187d	bellard	#if defined(CONFIG_USER_ONLY)
359	3475187d	bellard	#define supervisor(dc) 0
360	e9ebed4d	blueswir1	#define hypervisor(dc) 0
361	3475187d	bellard	#define gen_op_ldst(name) gen_op_##name##_raw()
362	3475187d	bellard	#define OP_LD_TABLE(width) \
363	3475187d	bellard	static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
364	3475187d	bellard	{ \
365	3475187d	bellard	int asi, offset; \
366	3475187d	bellard	\
367	3475187d	bellard	if (IS_IMM) { \
368	3475187d	bellard	offset = GET_FIELD(insn, 25, 31); \
369	3475187d	bellard	if (is_ld) \
370	3475187d	bellard	gen_op_ld_asi_reg(offset, size, sign); \
371	3475187d	bellard	else \
372	3475187d	bellard	gen_op_st_asi_reg(offset, size, sign); \
373	3475187d	bellard	return; \
374	3475187d	bellard	} \
375	3475187d	bellard	asi = GET_FIELD(insn, 19, 26); \
376	3475187d	bellard	switch (asi) { \
377	3475187d	bellard	case 0x80: /* Primary address space */ \
378	3475187d	bellard	gen_op_##width##_raw(); \
379	3475187d	bellard	break; \
380	725cb90b	bellard	case 0x82: /* Primary address space, non-faulting load */ \
381	725cb90b	bellard	gen_op_##width##_raw(); \
382	725cb90b	bellard	break; \
383	3475187d	bellard	default: \
384	3475187d	bellard	break; \
385	3475187d	bellard	} \
386	3475187d	bellard	}
387	3475187d	bellard
388	3475187d	bellard	#else
389	3475187d	bellard	#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
390	3475187d	bellard	#define OP_LD_TABLE(width) \
391	a68156d0	blueswir1	static GenOpFunc * const gen_op_##width[] = { \
392	3475187d	bellard	&gen_op_##width##_user, \
393	3475187d	bellard	&gen_op_##width##_kernel, \
394	3475187d	bellard	}; \
395	3475187d	bellard	\
396	3475187d	bellard	static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
397	3475187d	bellard	{ \
398	3475187d	bellard	int asi, offset; \
399	3475187d	bellard	\
400	3475187d	bellard	if (IS_IMM) { \
401	3475187d	bellard	offset = GET_FIELD(insn, 25, 31); \
402	3475187d	bellard	if (is_ld) \
403	3475187d	bellard	gen_op_ld_asi_reg(offset, size, sign); \
404	3475187d	bellard	else \
405	3475187d	bellard	gen_op_st_asi_reg(offset, size, sign); \
406	3475187d	bellard	return; \
407	3475187d	bellard	} \
408	3475187d	bellard	asi = GET_FIELD(insn, 19, 26); \
409	3475187d	bellard	if (is_ld) \
410	3475187d	bellard	gen_op_ld_asi(asi, size, sign); \
411	3475187d	bellard	else \
412	3475187d	bellard	gen_op_st_asi(asi, size, sign); \
413	3475187d	bellard	}
414	3475187d	bellard
415	3475187d	bellard	#define supervisor(dc) (dc->mem_idx == 1)
416	e9ebed4d	blueswir1	#define hypervisor(dc) (dc->mem_idx == 2)
417	3475187d	bellard	#endif
418	3475187d	bellard	#else
419	e8af50a3	bellard	#if defined(CONFIG_USER_ONLY)
420	e8af50a3	bellard	#define gen_op_ldst(name) gen_op_##name##_raw()
421	0fa85d43	bellard	#define OP_LD_TABLE(width)
422	e8af50a3	bellard	#define supervisor(dc) 0
423	e8af50a3	bellard	#else
424	e8af50a3	bellard	#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
425	e8af50a3	bellard	#define OP_LD_TABLE(width) \
426	a68156d0	blueswir1	static GenOpFunc * const gen_op_##width[] = { \
427	e8af50a3	bellard	&gen_op_##width##_user, \
428	e8af50a3	bellard	&gen_op_##width##_kernel, \
429	e8af50a3	bellard	}; \
430	e8af50a3	bellard	\
431	e8af50a3	bellard	static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
432	e8af50a3	bellard	{ \
433	e8af50a3	bellard	int asi; \
434	e8af50a3	bellard	\
435	e8af50a3	bellard	asi = GET_FIELD(insn, 19, 26); \
436	e8af50a3	bellard	switch (asi) { \
437	e8af50a3	bellard	case 10: /* User data access */ \
438	e8af50a3	bellard	gen_op_##width##_user(); \
439	e8af50a3	bellard	break; \
440	e8af50a3	bellard	case 11: /* Supervisor data access */ \
441	e8af50a3	bellard	gen_op_##width##_kernel(); \
442	e8af50a3	bellard	break; \
443	e8af50a3	bellard	case 0x20 ... 0x2f: /* MMU passthrough */ \
444	e8af50a3	bellard	if (is_ld) \
445	e8af50a3	bellard	gen_op_ld_asi(asi, size, sign); \
446	e8af50a3	bellard	else \
447	e8af50a3	bellard	gen_op_st_asi(asi, size, sign); \
448	e8af50a3	bellard	break; \
449	e8af50a3	bellard	default: \
450	e8af50a3	bellard	if (is_ld) \
451	e8af50a3	bellard	gen_op_ld_asi(asi, size, sign); \
452	e8af50a3	bellard	else \
453	e8af50a3	bellard	gen_op_st_asi(asi, size, sign); \
454	e8af50a3	bellard	break; \
455	e8af50a3	bellard	} \
456	e8af50a3	bellard	}
457	e8af50a3	bellard
458	e8af50a3	bellard	#define supervisor(dc) (dc->mem_idx == 1)
459	e8af50a3	bellard	#endif
460	3475187d	bellard	#endif
461	e8af50a3	bellard
462	e8af50a3	bellard	OP_LD_TABLE(ld);
463	e8af50a3	bellard	OP_LD_TABLE(st);
464	e8af50a3	bellard	OP_LD_TABLE(ldub);
465	e8af50a3	bellard	OP_LD_TABLE(lduh);
466	e8af50a3	bellard	OP_LD_TABLE(ldsb);
467	e8af50a3	bellard	OP_LD_TABLE(ldsh);
468	e8af50a3	bellard	OP_LD_TABLE(stb);
469	e8af50a3	bellard	OP_LD_TABLE(sth);
470	e8af50a3	bellard	OP_LD_TABLE(std);
471	e8af50a3	bellard	OP_LD_TABLE(ldstub);
472	e8af50a3	bellard	OP_LD_TABLE(swap);
473	e8af50a3	bellard	OP_LD_TABLE(ldd);
474	e8af50a3	bellard	OP_LD_TABLE(stf);
475	e8af50a3	bellard	OP_LD_TABLE(stdf);
476	e8af50a3	bellard	OP_LD_TABLE(ldf);
477	e8af50a3	bellard	OP_LD_TABLE(lddf);
478	e8af50a3	bellard
479	3475187d	bellard	#ifdef TARGET_SPARC64
480	dc011987	blueswir1	OP_LD_TABLE(lduw);
481	3475187d	bellard	OP_LD_TABLE(ldsw);
482	3475187d	bellard	OP_LD_TABLE(ldx);
483	3475187d	bellard	OP_LD_TABLE(stx);
484	3475187d	bellard	OP_LD_TABLE(cas);
485	3475187d	bellard	OP_LD_TABLE(casx);
486	3475187d	bellard	#endif
487	3475187d	bellard
488	3475187d	bellard	static inline void gen_movl_imm_TN(int reg, uint32_t imm)
489	7a3f1944	bellard	{
490	83469015	bellard	gen_op_movl_TN_im[reg](imm);
491	7a3f1944	bellard	}
492	7a3f1944	bellard
493	3475187d	bellard	static inline void gen_movl_imm_T1(uint32_t val)
494	7a3f1944	bellard	{
495	cf495bcf	bellard	gen_movl_imm_TN(1, val);
496	7a3f1944	bellard	}
497	7a3f1944	bellard
498	3475187d	bellard	static inline void gen_movl_imm_T0(uint32_t val)
499	7a3f1944	bellard	{
500	cf495bcf	bellard	gen_movl_imm_TN(0, val);
501	7a3f1944	bellard	}
502	7a3f1944	bellard
503	3475187d	bellard	static inline void gen_movl_simm_TN(int reg, int32_t imm)
504	3475187d	bellard	{
505	3475187d	bellard	gen_op_movl_TN_sim[reg](imm);
506	3475187d	bellard	}
507	3475187d	bellard
508	3475187d	bellard	static inline void gen_movl_simm_T1(int32_t val)
509	3475187d	bellard	{
510	3475187d	bellard	gen_movl_simm_TN(1, val);
511	3475187d	bellard	}
512	3475187d	bellard
513	3475187d	bellard	static inline void gen_movl_simm_T0(int32_t val)
514	3475187d	bellard	{
515	3475187d	bellard	gen_movl_simm_TN(0, val);
516	3475187d	bellard	}
517	3475187d	bellard
518	cf495bcf	bellard	static inline void gen_movl_reg_TN(int reg, int t)
519	7a3f1944	bellard	{
520	cf495bcf	bellard	if (reg)
521	cf495bcf	bellard	gen_op_movl_reg_TN[t][reg] ();
522	cf495bcf	bellard	else
523	cf495bcf	bellard	gen_movl_imm_TN(t, 0);
524	7a3f1944	bellard	}
525	7a3f1944	bellard
526	cf495bcf	bellard	static inline void gen_movl_reg_T0(int reg)
527	7a3f1944	bellard	{
528	cf495bcf	bellard	gen_movl_reg_TN(reg, 0);
529	7a3f1944	bellard	}
530	7a3f1944	bellard
531	cf495bcf	bellard	static inline void gen_movl_reg_T1(int reg)
532	7a3f1944	bellard	{
533	cf495bcf	bellard	gen_movl_reg_TN(reg, 1);
534	7a3f1944	bellard	}
535	7a3f1944	bellard
536	cf495bcf	bellard	static inline void gen_movl_reg_T2(int reg)
537	7a3f1944	bellard	{
538	cf495bcf	bellard	gen_movl_reg_TN(reg, 2);
539	7a3f1944	bellard	}
540	7a3f1944	bellard
541	cf495bcf	bellard	static inline void gen_movl_TN_reg(int reg, int t)
542	7a3f1944	bellard	{
543	cf495bcf	bellard	if (reg)
544	cf495bcf	bellard	gen_op_movl_TN_reg[t][reg] ();
545	7a3f1944	bellard	}
546	7a3f1944	bellard
547	cf495bcf	bellard	static inline void gen_movl_T0_reg(int reg)
548	7a3f1944	bellard	{
549	cf495bcf	bellard	gen_movl_TN_reg(reg, 0);
550	7a3f1944	bellard	}
551	7a3f1944	bellard
552	cf495bcf	bellard	static inline void gen_movl_T1_reg(int reg)
553	7a3f1944	bellard	{
554	cf495bcf	bellard	gen_movl_TN_reg(reg, 1);
555	7a3f1944	bellard	}
556	7a3f1944	bellard
557	3475187d	bellard	static inline void gen_jmp_im(target_ulong pc)
558	3475187d	bellard	{
559	3475187d	bellard	#ifdef TARGET_SPARC64
560	3475187d	bellard	if (pc == (uint32_t)pc) {
561	3475187d	bellard	gen_op_jmp_im(pc);
562	3475187d	bellard	} else {
563	3475187d	bellard	gen_op_jmp_im64(pc >> 32, pc);
564	3475187d	bellard	}
565	3475187d	bellard	#else
566	3475187d	bellard	gen_op_jmp_im(pc);
567	3475187d	bellard	#endif
568	3475187d	bellard	}
569	3475187d	bellard
570	3475187d	bellard	static inline void gen_movl_npc_im(target_ulong npc)
571	3475187d	bellard	{
572	3475187d	bellard	#ifdef TARGET_SPARC64
573	3475187d	bellard	if (npc == (uint32_t)npc) {
574	3475187d	bellard	gen_op_movl_npc_im(npc);
575	3475187d	bellard	} else {
576	3475187d	bellard	gen_op_movq_npc_im64(npc >> 32, npc);
577	3475187d	bellard	}
578	3475187d	bellard	#else
579	3475187d	bellard	gen_op_movl_npc_im(npc);
580	3475187d	bellard	#endif
581	3475187d	bellard	}
582	3475187d	bellard
583	6e256c93	bellard	static inline void gen_goto_tb(DisasContext *s, int tb_num,
584	6e256c93	bellard	target_ulong pc, target_ulong npc)
585	6e256c93	bellard	{
586	6e256c93	bellard	TranslationBlock *tb;
587	6e256c93	bellard
588	6e256c93	bellard	tb = s->tb;
589	6e256c93	bellard	if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
590	6e256c93	bellard	(npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
591	6e256c93	bellard	/* jump to same page: we can use a direct jump */
592	6e256c93	bellard	if (tb_num == 0)
593	6e256c93	bellard	gen_op_goto_tb0(TBPARAM(tb));
594	6e256c93	bellard	else
595	6e256c93	bellard	gen_op_goto_tb1(TBPARAM(tb));
596	6e256c93	bellard	gen_jmp_im(pc);
597	6e256c93	bellard	gen_movl_npc_im(npc);
598	6e256c93	bellard	gen_op_movl_T0_im((long)tb + tb_num);
599	6e256c93	bellard	gen_op_exit_tb();
600	6e256c93	bellard	} else {
601	6e256c93	bellard	/* jump to another page: currently not optimized */
602	6e256c93	bellard	gen_jmp_im(pc);
603	6e256c93	bellard	gen_movl_npc_im(npc);
604	6e256c93	bellard	gen_op_movl_T0_0();
605	6e256c93	bellard	gen_op_exit_tb();
606	6e256c93	bellard	}
607	6e256c93	bellard	}
608	6e256c93	bellard
609	46525e1f	blueswir1	static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
610	46525e1f	blueswir1	target_ulong pc2)
611	83469015	bellard	{
612	83469015	bellard	int l1;
613	83469015	bellard
614	83469015	bellard	l1 = gen_new_label();
615	83469015	bellard
616	83469015	bellard	gen_op_jz_T2_label(l1);
617	83469015	bellard
618	6e256c93	bellard	gen_goto_tb(dc, 0, pc1, pc1 + 4);
619	83469015	bellard
620	83469015	bellard	gen_set_label(l1);
621	6e256c93	bellard	gen_goto_tb(dc, 1, pc2, pc2 + 4);
622	83469015	bellard	}
623	83469015	bellard
624	46525e1f	blueswir1	static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
625	46525e1f	blueswir1	target_ulong pc2)
626	83469015	bellard	{
627	83469015	bellard	int l1;
628	83469015	bellard
629	83469015	bellard	l1 = gen_new_label();
630	83469015	bellard
631	83469015	bellard	gen_op_jz_T2_label(l1);
632	83469015	bellard
633	6e256c93	bellard	gen_goto_tb(dc, 0, pc2, pc1);
634	83469015	bellard
635	83469015	bellard	gen_set_label(l1);
636	6e256c93	bellard	gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
637	83469015	bellard	}
638	83469015	bellard
639	46525e1f	blueswir1	static inline void gen_branch(DisasContext *dc, target_ulong pc,
640	46525e1f	blueswir1	target_ulong npc)
641	83469015	bellard	{
642	6e256c93	bellard	gen_goto_tb(dc, 0, pc, npc);
643	83469015	bellard	}
644	83469015	bellard
645	46525e1f	blueswir1	static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)
646	83469015	bellard	{
647	83469015	bellard	int l1, l2;
648	83469015	bellard
649	83469015	bellard	l1 = gen_new_label();
650	83469015	bellard	l2 = gen_new_label();
651	83469015	bellard	gen_op_jz_T2_label(l1);
652	83469015	bellard
653	83469015	bellard	gen_movl_npc_im(npc1);
654	83469015	bellard	gen_op_jmp_label(l2);
655	83469015	bellard
656	83469015	bellard	gen_set_label(l1);
657	83469015	bellard	gen_movl_npc_im(npc2);
658	83469015	bellard	gen_set_label(l2);
659	83469015	bellard	}
660	83469015	bellard
661	83469015	bellard	/* call this function before using T2 as it may have been set for a jump */
662	83469015	bellard	static inline void flush_T2(DisasContext * dc)
663	83469015	bellard	{
664	83469015	bellard	if (dc->npc == JUMP_PC) {
665	46525e1f	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
666	83469015	bellard	dc->npc = DYNAMIC_PC;
667	83469015	bellard	}
668	83469015	bellard	}
669	83469015	bellard
670	72cbca10	bellard	static inline void save_npc(DisasContext * dc)
671	72cbca10	bellard	{
672	72cbca10	bellard	if (dc->npc == JUMP_PC) {
673	46525e1f	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
674	72cbca10	bellard	dc->npc = DYNAMIC_PC;
675	72cbca10	bellard	} else if (dc->npc != DYNAMIC_PC) {
676	3475187d	bellard	gen_movl_npc_im(dc->npc);
677	72cbca10	bellard	}
678	72cbca10	bellard	}
679	72cbca10	bellard
680	72cbca10	bellard	static inline void save_state(DisasContext * dc)
681	72cbca10	bellard	{
682	3475187d	bellard	gen_jmp_im(dc->pc);
683	72cbca10	bellard	save_npc(dc);
684	72cbca10	bellard	}
685	72cbca10	bellard
686	0bee699e	bellard	static inline void gen_mov_pc_npc(DisasContext * dc)
687	0bee699e	bellard	{
688	0bee699e	bellard	if (dc->npc == JUMP_PC) {
689	46525e1f	blueswir1	gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
690	0bee699e	bellard	gen_op_mov_pc_npc();
691	0bee699e	bellard	dc->pc = DYNAMIC_PC;
692	0bee699e	bellard	} else if (dc->npc == DYNAMIC_PC) {
693	0bee699e	bellard	gen_op_mov_pc_npc();
694	0bee699e	bellard	dc->pc = DYNAMIC_PC;
695	0bee699e	bellard	} else {
696	0bee699e	bellard	dc->pc = dc->npc;
697	0bee699e	bellard	}
698	0bee699e	bellard	}
699	0bee699e	bellard
700	3475187d	bellard	static GenOpFunc * const gen_cond[2][16] = {
701	3475187d	bellard	{
702	9bad0425	blueswir1	gen_op_eval_bn,
703	3475187d	bellard	gen_op_eval_be,
704	3475187d	bellard	gen_op_eval_ble,
705	3475187d	bellard	gen_op_eval_bl,
706	3475187d	bellard	gen_op_eval_bleu,
707	3475187d	bellard	gen_op_eval_bcs,
708	3475187d	bellard	gen_op_eval_bneg,
709	3475187d	bellard	gen_op_eval_bvs,
710	9bad0425	blueswir1	gen_op_eval_ba,
711	3475187d	bellard	gen_op_eval_bne,
712	3475187d	bellard	gen_op_eval_bg,
713	3475187d	bellard	gen_op_eval_bge,
714	3475187d	bellard	gen_op_eval_bgu,
715	3475187d	bellard	gen_op_eval_bcc,
716	3475187d	bellard	gen_op_eval_bpos,
717	3475187d	bellard	gen_op_eval_bvc,
718	3475187d	bellard	},
719	3475187d	bellard	{
720	3475187d	bellard	#ifdef TARGET_SPARC64
721	9bad0425	blueswir1	gen_op_eval_bn,
722	3475187d	bellard	gen_op_eval_xbe,
723	3475187d	bellard	gen_op_eval_xble,
724	3475187d	bellard	gen_op_eval_xbl,
725	3475187d	bellard	gen_op_eval_xbleu,
726	3475187d	bellard	gen_op_eval_xbcs,
727	3475187d	bellard	gen_op_eval_xbneg,
728	3475187d	bellard	gen_op_eval_xbvs,
729	9bad0425	blueswir1	gen_op_eval_ba,
730	3475187d	bellard	gen_op_eval_xbne,
731	3475187d	bellard	gen_op_eval_xbg,
732	3475187d	bellard	gen_op_eval_xbge,
733	3475187d	bellard	gen_op_eval_xbgu,
734	3475187d	bellard	gen_op_eval_xbcc,
735	3475187d	bellard	gen_op_eval_xbpos,
736	3475187d	bellard	gen_op_eval_xbvc,
737	3475187d	bellard	#endif
738	3475187d	bellard	},
739	3475187d	bellard	};
740	3475187d	bellard
741	3475187d	bellard	static GenOpFunc * const gen_fcond[4][16] = {
742	3475187d	bellard	{
743	9bad0425	blueswir1	gen_op_eval_bn,
744	3475187d	bellard	gen_op_eval_fbne,
745	3475187d	bellard	gen_op_eval_fblg,
746	3475187d	bellard	gen_op_eval_fbul,
747	3475187d	bellard	gen_op_eval_fbl,
748	3475187d	bellard	gen_op_eval_fbug,
749	3475187d	bellard	gen_op_eval_fbg,
750	3475187d	bellard	gen_op_eval_fbu,
751	9bad0425	blueswir1	gen_op_eval_ba,
752	3475187d	bellard	gen_op_eval_fbe,
753	3475187d	bellard	gen_op_eval_fbue,
754	3475187d	bellard	gen_op_eval_fbge,
755	3475187d	bellard	gen_op_eval_fbuge,
756	3475187d	bellard	gen_op_eval_fble,
757	3475187d	bellard	gen_op_eval_fbule,
758	3475187d	bellard	gen_op_eval_fbo,
759	3475187d	bellard	},
760	3475187d	bellard	#ifdef TARGET_SPARC64
761	3475187d	bellard	{
762	9bad0425	blueswir1	gen_op_eval_bn,
763	3475187d	bellard	gen_op_eval_fbne_fcc1,
764	3475187d	bellard	gen_op_eval_fblg_fcc1,
765	3475187d	bellard	gen_op_eval_fbul_fcc1,
766	3475187d	bellard	gen_op_eval_fbl_fcc1,
767	3475187d	bellard	gen_op_eval_fbug_fcc1,
768	3475187d	bellard	gen_op_eval_fbg_fcc1,
769	3475187d	bellard	gen_op_eval_fbu_fcc1,
770	9bad0425	blueswir1	gen_op_eval_ba,
771	3475187d	bellard	gen_op_eval_fbe_fcc1,
772	3475187d	bellard	gen_op_eval_fbue_fcc1,
773	3475187d	bellard	gen_op_eval_fbge_fcc1,
774	3475187d	bellard	gen_op_eval_fbuge_fcc1,
775	3475187d	bellard	gen_op_eval_fble_fcc1,
776	3475187d	bellard	gen_op_eval_fbule_fcc1,
777	3475187d	bellard	gen_op_eval_fbo_fcc1,
778	3475187d	bellard	},
779	3475187d	bellard	{
780	9bad0425	blueswir1	gen_op_eval_bn,
781	3475187d	bellard	gen_op_eval_fbne_fcc2,
782	3475187d	bellard	gen_op_eval_fblg_fcc2,
783	3475187d	bellard	gen_op_eval_fbul_fcc2,
784	3475187d	bellard	gen_op_eval_fbl_fcc2,
785	3475187d	bellard	gen_op_eval_fbug_fcc2,
786	3475187d	bellard	gen_op_eval_fbg_fcc2,
787	3475187d	bellard	gen_op_eval_fbu_fcc2,
788	9bad0425	blueswir1	gen_op_eval_ba,
789	3475187d	bellard	gen_op_eval_fbe_fcc2,
790	3475187d	bellard	gen_op_eval_fbue_fcc2,
791	3475187d	bellard	gen_op_eval_fbge_fcc2,
792	3475187d	bellard	gen_op_eval_fbuge_fcc2,
793	3475187d	bellard	gen_op_eval_fble_fcc2,
794	3475187d	bellard	gen_op_eval_fbule_fcc2,
795	3475187d	bellard	gen_op_eval_fbo_fcc2,
796	3475187d	bellard	},
797	3475187d	bellard	{
798	9bad0425	blueswir1	gen_op_eval_bn,
799	3475187d	bellard	gen_op_eval_fbne_fcc3,
800	3475187d	bellard	gen_op_eval_fblg_fcc3,
801	3475187d	bellard	gen_op_eval_fbul_fcc3,
802	3475187d	bellard	gen_op_eval_fbl_fcc3,
803	3475187d	bellard	gen_op_eval_fbug_fcc3,
804	3475187d	bellard	gen_op_eval_fbg_fcc3,
805	3475187d	bellard	gen_op_eval_fbu_fcc3,
806	9bad0425	blueswir1	gen_op_eval_ba,
807	3475187d	bellard	gen_op_eval_fbe_fcc3,
808	3475187d	bellard	gen_op_eval_fbue_fcc3,
809	3475187d	bellard	gen_op_eval_fbge_fcc3,
810	3475187d	bellard	gen_op_eval_fbuge_fcc3,
811	3475187d	bellard	gen_op_eval_fble_fcc3,
812	3475187d	bellard	gen_op_eval_fbule_fcc3,
813	3475187d	bellard	gen_op_eval_fbo_fcc3,
814	3475187d	bellard	},
815	3475187d	bellard	#else
816	3475187d	bellard	{}, {}, {},
817	3475187d	bellard	#endif
818	3475187d	bellard	};
819	7a3f1944	bellard
820	3475187d	bellard	#ifdef TARGET_SPARC64
821	3475187d	bellard	static void gen_cond_reg(int cond)
822	e8af50a3	bellard	{
823	e8af50a3	bellard	switch (cond) {
824	e8af50a3	bellard	case 0x1:
825	3475187d	bellard	gen_op_eval_brz();
826	e8af50a3	bellard	break;
827	e8af50a3	bellard	case 0x2:
828	3475187d	bellard	gen_op_eval_brlez();
829	e8af50a3	bellard	break;
830	e8af50a3	bellard	case 0x3:
831	3475187d	bellard	gen_op_eval_brlz();
832	e8af50a3	bellard	break;
833	e8af50a3	bellard	case 0x5:
834	3475187d	bellard	gen_op_eval_brnz();
835	e8af50a3	bellard	break;
836	e8af50a3	bellard	case 0x6:
837	3475187d	bellard	gen_op_eval_brgz();
838	e8af50a3	bellard	break;
839	e8af50a3	bellard	default:
840	3475187d	bellard	case 0x7:
841	3475187d	bellard	gen_op_eval_brgez();
842	e8af50a3	bellard	break;
843	e8af50a3	bellard	}
844	e8af50a3	bellard	}
845	3475187d	bellard	#endif
846	cf495bcf	bellard
847	0bee699e	bellard	/* XXX: potentially incorrect if dynamic npc */
848	3475187d	bellard	static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
849	7a3f1944	bellard	{
850	cf495bcf	bellard	unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
851	af7bf89b	bellard	target_ulong target = dc->pc + offset;
852	3475187d	bellard
853	cf495bcf	bellard	if (cond == 0x0) {
854	cf495bcf	bellard	/* unconditional not taken */
855	cf495bcf	bellard	if (a) {
856	0bee699e	bellard	dc->pc = dc->npc + 4;
857	cf495bcf	bellard	dc->npc = dc->pc + 4;
858	cf495bcf	bellard	} else {
859	cf495bcf	bellard	dc->pc = dc->npc;
860	cf495bcf	bellard	dc->npc = dc->pc + 4;
861	cf495bcf	bellard	}
862	cf495bcf	bellard	} else if (cond == 0x8) {
863	cf495bcf	bellard	/* unconditional taken */
864	cf495bcf	bellard	if (a) {
865	72cbca10	bellard	dc->pc = target;
866	cf495bcf	bellard	dc->npc = dc->pc + 4;
867	cf495bcf	bellard	} else {
868	cf495bcf	bellard	dc->pc = dc->npc;
869	72cbca10	bellard	dc->npc = target;
870	cf495bcf	bellard	}
871	cf495bcf	bellard	} else {
872	72cbca10	bellard	flush_T2(dc);
873	3475187d	bellard	gen_cond[cc][cond]();
874	cf495bcf	bellard	if (a) {
875	46525e1f	blueswir1	gen_branch_a(dc, target, dc->npc);
876	cf495bcf	bellard	dc->is_br = 1;
877	cf495bcf	bellard	} else {
878	cf495bcf	bellard	dc->pc = dc->npc;
879	72cbca10	bellard	dc->jump_pc[0] = target;
880	72cbca10	bellard	dc->jump_pc[1] = dc->npc + 4;
881	72cbca10	bellard	dc->npc = JUMP_PC;
882	cf495bcf	bellard	}
883	cf495bcf	bellard	}
884	7a3f1944	bellard	}
885	7a3f1944	bellard
886	0bee699e	bellard	/* XXX: potentially incorrect if dynamic npc */
887	3475187d	bellard	static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
888	e8af50a3	bellard	{
889	e8af50a3	bellard	unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
890	af7bf89b	bellard	target_ulong target = dc->pc + offset;
891	af7bf89b	bellard
892	e8af50a3	bellard	if (cond == 0x0) {
893	e8af50a3	bellard	/* unconditional not taken */
894	e8af50a3	bellard	if (a) {
895	e8af50a3	bellard	dc->pc = dc->npc + 4;
896	e8af50a3	bellard	dc->npc = dc->pc + 4;
897	e8af50a3	bellard	} else {
898	e8af50a3	bellard	dc->pc = dc->npc;
899	e8af50a3	bellard	dc->npc = dc->pc + 4;
900	e8af50a3	bellard	}
901	e8af50a3	bellard	} else if (cond == 0x8) {
902	e8af50a3	bellard	/* unconditional taken */
903	e8af50a3	bellard	if (a) {
904	e8af50a3	bellard	dc->pc = target;
905	e8af50a3	bellard	dc->npc = dc->pc + 4;
906	e8af50a3	bellard	} else {
907	e8af50a3	bellard	dc->pc = dc->npc;
908	e8af50a3	bellard	dc->npc = target;
909	e8af50a3	bellard	}
910	e8af50a3	bellard	} else {
911	e8af50a3	bellard	flush_T2(dc);
912	3475187d	bellard	gen_fcond[cc][cond]();
913	e8af50a3	bellard	if (a) {
914	46525e1f	blueswir1	gen_branch_a(dc, target, dc->npc);
915	e8af50a3	bellard	dc->is_br = 1;
916	e8af50a3	bellard	} else {
917	e8af50a3	bellard	dc->pc = dc->npc;
918	e8af50a3	bellard	dc->jump_pc[0] = target;
919	e8af50a3	bellard	dc->jump_pc[1] = dc->npc + 4;
920	e8af50a3	bellard	dc->npc = JUMP_PC;
921	e8af50a3	bellard	}
922	e8af50a3	bellard	}
923	e8af50a3	bellard	}
924	e8af50a3	bellard
925	3475187d	bellard	#ifdef TARGET_SPARC64
926	3475187d	bellard	/* XXX: potentially incorrect if dynamic npc */
927	3475187d	bellard	static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
928	7a3f1944	bellard	{
929	3475187d	bellard	unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
930	3475187d	bellard	target_ulong target = dc->pc + offset;
931	3475187d	bellard
932	3475187d	bellard	flush_T2(dc);
933	3475187d	bellard	gen_cond_reg(cond);
934	3475187d	bellard	if (a) {
935	46525e1f	blueswir1	gen_branch_a(dc, target, dc->npc);
936	3475187d	bellard	dc->is_br = 1;
937	3475187d	bellard	} else {
938	3475187d	bellard	dc->pc = dc->npc;
939	3475187d	bellard	dc->jump_pc[0] = target;
940	3475187d	bellard	dc->jump_pc[1] = dc->npc + 4;
941	3475187d	bellard	dc->npc = JUMP_PC;
942	3475187d	bellard	}
943	7a3f1944	bellard	}
944	7a3f1944	bellard
945	3475187d	bellard	static GenOpFunc * const gen_fcmps[4] = {
946	3475187d	bellard	gen_op_fcmps,
947	3475187d	bellard	gen_op_fcmps_fcc1,
948	3475187d	bellard	gen_op_fcmps_fcc2,
949	3475187d	bellard	gen_op_fcmps_fcc3,
950	3475187d	bellard	};
951	3475187d	bellard
952	3475187d	bellard	static GenOpFunc * const gen_fcmpd[4] = {
953	3475187d	bellard	gen_op_fcmpd,
954	3475187d	bellard	gen_op_fcmpd_fcc1,
955	3475187d	bellard	gen_op_fcmpd_fcc2,
956	3475187d	bellard	gen_op_fcmpd_fcc3,
957	3475187d	bellard	};
958	417454b0	blueswir1
959	417454b0	blueswir1	static GenOpFunc * const gen_fcmpes[4] = {
960	417454b0	blueswir1	gen_op_fcmpes,
961	417454b0	blueswir1	gen_op_fcmpes_fcc1,
962	417454b0	blueswir1	gen_op_fcmpes_fcc2,
963	417454b0	blueswir1	gen_op_fcmpes_fcc3,
964	417454b0	blueswir1	};
965	417454b0	blueswir1
966	417454b0	blueswir1	static GenOpFunc * const gen_fcmped[4] = {
967	417454b0	blueswir1	gen_op_fcmped,
968	417454b0	blueswir1	gen_op_fcmped_fcc1,
969	417454b0	blueswir1	gen_op_fcmped_fcc2,
970	417454b0	blueswir1	gen_op_fcmped_fcc3,
971	417454b0	blueswir1	};
972	417454b0	blueswir1
973	3475187d	bellard	#endif
974	3475187d	bellard
975	a80dde08	bellard	static int gen_trap_ifnofpu(DisasContext * dc)
976	a80dde08	bellard	{
977	a80dde08	bellard	#if !defined(CONFIG_USER_ONLY)
978	a80dde08	bellard	if (!dc->fpu_enabled) {
979	a80dde08	bellard	save_state(dc);
980	a80dde08	bellard	gen_op_exception(TT_NFPU_INSN);
981	a80dde08	bellard	dc->is_br = 1;
982	a80dde08	bellard	return 1;
983	a80dde08	bellard	}
984	a80dde08	bellard	#endif
985	a80dde08	bellard	return 0;
986	a80dde08	bellard	}
987	a80dde08	bellard
988	0bee699e	bellard	/* before an instruction, dc->pc must be static */
989	cf495bcf	bellard	static void disas_sparc_insn(DisasContext * dc)
990	cf495bcf	bellard	{
991	cf495bcf	bellard	unsigned int insn, opc, rs1, rs2, rd;
992	7a3f1944	bellard
993	0fa85d43	bellard	insn = ldl_code(dc->pc);
994	cf495bcf	bellard	opc = GET_FIELD(insn, 0, 1);
995	7a3f1944	bellard
996	cf495bcf	bellard	rd = GET_FIELD(insn, 2, 6);
997	cf495bcf	bellard	switch (opc) {
998	cf495bcf	bellard	case 0: /* branches/sethi */
999	cf495bcf	bellard	{
1000	cf495bcf	bellard	unsigned int xop = GET_FIELD(insn, 7, 9);
1001	af7bf89b	bellard	int32_t target;
1002	cf495bcf	bellard	switch (xop) {
1003	3475187d	bellard	#ifdef TARGET_SPARC64
1004	af7bf89b	bellard	case 0x1: /* V9 BPcc */
1005	3475187d	bellard	{
1006	3475187d	bellard	int cc;
1007	3475187d	bellard
1008	3475187d	bellard	target = GET_FIELD_SP(insn, 0, 18);
1009	3475187d	bellard	target = sign_extend(target, 18);
1010	ee6c0b51	bellard	target <<= 2;
1011	3475187d	bellard	cc = GET_FIELD_SP(insn, 20, 21);
1012	3475187d	bellard	if (cc == 0)
1013	3475187d	bellard	do_branch(dc, target, insn, 0);
1014	3475187d	bellard	else if (cc == 2)
1015	3475187d	bellard	do_branch(dc, target, insn, 1);
1016	3475187d	bellard	else
1017	3475187d	bellard	goto illegal_insn;
1018	3475187d	bellard	goto jmp_insn;
1019	3475187d	bellard	}
1020	af7bf89b	bellard	case 0x3: /* V9 BPr */
1021	3475187d	bellard	{
1022	3475187d	bellard	target = GET_FIELD_SP(insn, 0, 13) \|
1023	13846e70	bellard	(GET_FIELD_SP(insn, 20, 21) << 14);
1024	3475187d	bellard	target = sign_extend(target, 16);
1025	ee6c0b51	bellard	target <<= 2;
1026	3475187d	bellard	rs1 = GET_FIELD(insn, 13, 17);
1027	83469015	bellard	gen_movl_reg_T0(rs1);
1028	3475187d	bellard	do_branch_reg(dc, target, insn);
1029	3475187d	bellard	goto jmp_insn;
1030	3475187d	bellard	}
1031	af7bf89b	bellard	case 0x5: /* V9 FBPcc */
1032	3475187d	bellard	{
1033	3475187d	bellard	int cc = GET_FIELD_SP(insn, 20, 21);
1034	a80dde08	bellard	if (gen_trap_ifnofpu(dc))
1035	a80dde08	bellard	goto jmp_insn;
1036	3475187d	bellard	target = GET_FIELD_SP(insn, 0, 18);
1037	3475187d	bellard	target = sign_extend(target, 19);
1038	ee6c0b51	bellard	target <<= 2;
1039	3475187d	bellard	do_fbranch(dc, target, insn, cc);
1040	3475187d	bellard	goto jmp_insn;
1041	3475187d	bellard	}
1042	a4d17f19	blueswir1	#else
1043	a4d17f19	blueswir1	case 0x7: /* CBN+x */
1044	a4d17f19	blueswir1	{
1045	a4d17f19	blueswir1	goto ncp_insn;
1046	a4d17f19	blueswir1	}
1047	3475187d	bellard	#endif
1048	cf495bcf	bellard	case 0x2: /* BN+x */
1049	7a3f1944	bellard	{
1050	3475187d	bellard	target = GET_FIELD(insn, 10, 31);
1051	cf495bcf	bellard	target = sign_extend(target, 22);
1052	ee6c0b51	bellard	target <<= 2;
1053	3475187d	bellard	do_branch(dc, target, insn, 0);
1054	cf495bcf	bellard	goto jmp_insn;
1055	7a3f1944	bellard	}
1056	e8af50a3	bellard	case 0x6: /* FBN+x */
1057	e8af50a3	bellard	{
1058	a80dde08	bellard	if (gen_trap_ifnofpu(dc))
1059	a80dde08	bellard	goto jmp_insn;
1060	3475187d	bellard	target = GET_FIELD(insn, 10, 31);
1061	e8af50a3	bellard	target = sign_extend(target, 22);
1062	ee6c0b51	bellard	target <<= 2;
1063	3475187d	bellard	do_fbranch(dc, target, insn, 0);
1064	e8af50a3	bellard	goto jmp_insn;
1065	e8af50a3	bellard	}
1066	cf495bcf	bellard	case 0x4: /* SETHI */
1067	e80cfcfc	bellard	#define OPTIM
1068	e80cfcfc	bellard	#if defined(OPTIM)
1069	e80cfcfc	bellard	if (rd) { // nop
1070	e80cfcfc	bellard	#endif
1071	3475187d	bellard	uint32_t value = GET_FIELD(insn, 10, 31);
1072	3475187d	bellard	gen_movl_imm_T0(value << 10);
1073	e80cfcfc	bellard	gen_movl_T0_reg(rd);
1074	e80cfcfc	bellard	#if defined(OPTIM)
1075	e80cfcfc	bellard	}
1076	e80cfcfc	bellard	#endif
1077	cf495bcf	bellard	break;
1078	3475187d	bellard	case 0x0: /* UNIMPL */
1079	3475187d	bellard	default:
1080	3475187d	bellard	goto illegal_insn;
1081	cf495bcf	bellard	}
1082	cf495bcf	bellard	break;
1083	cf495bcf	bellard	}
1084	af7bf89b	bellard	break;
1085	cf495bcf	bellard	case 1:
1086	cf495bcf	bellard	/CALL/ {
1087	af7bf89b	bellard	target_long target = GET_FIELDs(insn, 2, 31) << 2;
1088	cf495bcf	bellard
1089	83469015	bellard	#ifdef TARGET_SPARC64
1090	83469015	bellard	if (dc->pc == (uint32_t)dc->pc) {
1091	83469015	bellard	gen_op_movl_T0_im(dc->pc);
1092	83469015	bellard	} else {
1093	83469015	bellard	gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1094	83469015	bellard	}
1095	83469015	bellard	#else
1096	af7bf89b	bellard	gen_op_movl_T0_im(dc->pc);
1097	83469015	bellard	#endif
1098	cf495bcf	bellard	gen_movl_T0_reg(15);
1099	af7bf89b	bellard	target += dc->pc;
1100	0bee699e	bellard	gen_mov_pc_npc(dc);
1101	72cbca10	bellard	dc->npc = target;
1102	cf495bcf	bellard	}
1103	cf495bcf	bellard	goto jmp_insn;
1104	cf495bcf	bellard	case 2: /* FPU & Logical Operations */
1105	cf495bcf	bellard	{
1106	cf495bcf	bellard	unsigned int xop = GET_FIELD(insn, 7, 12);
1107	cf495bcf	bellard	if (xop == 0x3a) { /* generate trap */
1108	cf495bcf	bellard	int cond;
1109	3475187d	bellard
1110	cf495bcf	bellard	rs1 = GET_FIELD(insn, 13, 17);
1111	cf495bcf	bellard	gen_movl_reg_T0(rs1);
1112	cf495bcf	bellard	if (IS_IMM) {
1113	e8af50a3	bellard	rs2 = GET_FIELD(insn, 25, 31);
1114	e80cfcfc	bellard	#if defined(OPTIM)
1115	e8af50a3	bellard	if (rs2 != 0) {
1116	e80cfcfc	bellard	#endif
1117	3475187d	bellard	gen_movl_simm_T1(rs2);
1118	e80cfcfc	bellard	gen_op_add_T1_T0();
1119	e80cfcfc	bellard	#if defined(OPTIM)
1120	e8af50a3	bellard	}
1121	e80cfcfc	bellard	#endif
1122	cf495bcf	bellard	} else {
1123	cf495bcf	bellard	rs2 = GET_FIELD(insn, 27, 31);
1124	e80cfcfc	bellard	#if defined(OPTIM)
1125	e80cfcfc	bellard	if (rs2 != 0) {
1126	e80cfcfc	bellard	#endif
1127	e80cfcfc	bellard	gen_movl_reg_T1(rs2);
1128	e80cfcfc	bellard	gen_op_add_T1_T0();
1129	e80cfcfc	bellard	#if defined(OPTIM)
1130	e80cfcfc	bellard	}
1131	e80cfcfc	bellard	#endif
1132	cf495bcf	bellard	}
1133	cf495bcf	bellard	cond = GET_FIELD(insn, 3, 6);
1134	cf495bcf	bellard	if (cond == 0x8) {
1135	a80dde08	bellard	save_state(dc);
1136	cf495bcf	bellard	gen_op_trap_T0();
1137	af7bf89b	bellard	} else if (cond != 0) {
1138	3475187d	bellard	#ifdef TARGET_SPARC64
1139	3475187d	bellard	/* V9 icc/xcc */
1140	3475187d	bellard	int cc = GET_FIELD_SP(insn, 11, 12);
1141	a80dde08	bellard	flush_T2(dc);
1142	a80dde08	bellard	save_state(dc);
1143	3475187d	bellard	if (cc == 0)
1144	3475187d	bellard	gen_cond[0][cond]();
1145	3475187d	bellard	else if (cc == 2)
1146	3475187d	bellard	gen_cond[1][cond]();
1147	3475187d	bellard	else
1148	3475187d	bellard	goto illegal_insn;
1149	3475187d	bellard	#else
1150	a80dde08	bellard	flush_T2(dc);
1151	a80dde08	bellard	save_state(dc);
1152	3475187d	bellard	gen_cond[0][cond]();
1153	3475187d	bellard	#endif
1154	cf495bcf	bellard	gen_op_trapcc_T0();
1155	cf495bcf	bellard	}
1156	a80dde08	bellard	gen_op_next_insn();
1157	a80dde08	bellard	gen_op_movl_T0_0();
1158	a80dde08	bellard	gen_op_exit_tb();
1159	a80dde08	bellard	dc->is_br = 1;
1160	a80dde08	bellard	goto jmp_insn;
1161	cf495bcf	bellard	} else if (xop == 0x28) {
1162	cf495bcf	bellard	rs1 = GET_FIELD(insn, 13, 17);
1163	cf495bcf	bellard	switch(rs1) {
1164	cf495bcf	bellard	case 0: /* rdy */
1165	65fe7b09	blueswir1	#ifndef TARGET_SPARC64
1166	65fe7b09	blueswir1	case 0x01 ... 0x0e: /* undefined in the SPARCv8
1167	65fe7b09	blueswir1	manual, rdy on the microSPARC
1168	65fe7b09	blueswir1	II */
1169	65fe7b09	blueswir1	case 0x0f: /* stbar in the SPARCv8 manual,
1170	65fe7b09	blueswir1	rdy on the microSPARC II */
1171	65fe7b09	blueswir1	case 0x10 ... 0x1f: /* implementation-dependent in the
1172	65fe7b09	blueswir1	SPARCv8 manual, rdy on the
1173	65fe7b09	blueswir1	microSPARC II */
1174	65fe7b09	blueswir1	#endif
1175	65fe7b09	blueswir1	gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
1176	cf495bcf	bellard	gen_movl_T0_reg(rd);
1177	cf495bcf	bellard	break;
1178	3475187d	bellard	#ifdef TARGET_SPARC64
1179	af7bf89b	bellard	case 0x2: /* V9 rdccr */
1180	3475187d	bellard	gen_op_rdccr();
1181	3475187d	bellard	gen_movl_T0_reg(rd);
1182	3475187d	bellard	break;
1183	af7bf89b	bellard	case 0x3: /* V9 rdasi */
1184	3475187d	bellard	gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1185	3475187d	bellard	gen_movl_T0_reg(rd);
1186	3475187d	bellard	break;
1187	af7bf89b	bellard	case 0x4: /* V9 rdtick */
1188	3475187d	bellard	gen_op_rdtick();
1189	3475187d	bellard	gen_movl_T0_reg(rd);
1190	3475187d	bellard	break;
1191	af7bf89b	bellard	case 0x5: /* V9 rdpc */
1192	ded3ab80	pbrook	if (dc->pc == (uint32_t)dc->pc) {
1193	ded3ab80	pbrook	gen_op_movl_T0_im(dc->pc);
1194	ded3ab80	pbrook	} else {
1195	ded3ab80	pbrook	gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1196	ded3ab80	pbrook	}
1197	3475187d	bellard	gen_movl_T0_reg(rd);
1198	3475187d	bellard	break;
1199	af7bf89b	bellard	case 0x6: /* V9 rdfprs */
1200	3475187d	bellard	gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1201	3475187d	bellard	gen_movl_T0_reg(rd);
1202	3475187d	bellard	break;
1203	65fe7b09	blueswir1	case 0xf: /* V9 membar */
1204	65fe7b09	blueswir1	break; /* no effect */
1205	725cb90b	bellard	case 0x13: /* Graphics Status */
1206	725cb90b	bellard	if (gen_trap_ifnofpu(dc))
1207	725cb90b	bellard	goto jmp_insn;
1208	725cb90b	bellard	gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1209	725cb90b	bellard	gen_movl_T0_reg(rd);
1210	725cb90b	bellard	break;
1211	83469015	bellard	case 0x17: /* Tick compare */
1212	83469015	bellard	gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1213	83469015	bellard	gen_movl_T0_reg(rd);
1214	83469015	bellard	break;
1215	83469015	bellard	case 0x18: /* System tick */
1216	20c9f095	blueswir1	gen_op_rdstick();
1217	83469015	bellard	gen_movl_T0_reg(rd);
1218	83469015	bellard	break;
1219	83469015	bellard	case 0x19: /* System tick compare */
1220	83469015	bellard	gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1221	83469015	bellard	gen_movl_T0_reg(rd);
1222	83469015	bellard	break;
1223	83469015	bellard	case 0x10: /* Performance Control */
1224	83469015	bellard	case 0x11: /* Performance Instrumentation Counter */
1225	83469015	bellard	case 0x12: /* Dispatch Control */
1226	83469015	bellard	case 0x14: /* Softint set, WO */
1227	83469015	bellard	case 0x15: /* Softint clear, WO */
1228	83469015	bellard	case 0x16: /* Softint write */
1229	3475187d	bellard	#endif
1230	3475187d	bellard	default:
1231	cf495bcf	bellard	goto illegal_insn;
1232	cf495bcf	bellard	}
1233	e8af50a3	bellard	#if !defined(CONFIG_USER_ONLY)
1234	e9ebed4d	blueswir1	} else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
1235	3475187d	bellard	#ifndef TARGET_SPARC64
1236	e8af50a3	bellard	if (!supervisor(dc))
1237	e8af50a3	bellard	goto priv_insn;
1238	e8af50a3	bellard	gen_op_rdpsr();
1239	e9ebed4d	blueswir1	#else
1240	e9ebed4d	blueswir1	if (!hypervisor(dc))
1241	e9ebed4d	blueswir1	goto priv_insn;
1242	e9ebed4d	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
1243	e9ebed4d	blueswir1	switch (rs1) {
1244	e9ebed4d	blueswir1	case 0: // hpstate
1245	e9ebed4d	blueswir1	// gen_op_rdhpstate();
1246	e9ebed4d	blueswir1	break;
1247	e9ebed4d	blueswir1	case 1: // htstate
1248	e9ebed4d	blueswir1	// gen_op_rdhtstate();
1249	e9ebed4d	blueswir1	break;
1250	e9ebed4d	blueswir1	case 3: // hintp
1251	e9ebed4d	blueswir1	gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
1252	e9ebed4d	blueswir1	break;
1253	e9ebed4d	blueswir1	case 5: // htba
1254	e9ebed4d	blueswir1	gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
1255	e9ebed4d	blueswir1	break;
1256	e9ebed4d	blueswir1	case 6: // hver
1257	e9ebed4d	blueswir1	gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
1258	e9ebed4d	blueswir1	break;
1259	e9ebed4d	blueswir1	case 31: // hstick_cmpr
1260	e9ebed4d	blueswir1	gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
1261	e9ebed4d	blueswir1	break;
1262	e9ebed4d	blueswir1	default:
1263	e9ebed4d	blueswir1	goto illegal_insn;
1264	e9ebed4d	blueswir1	}
1265	e9ebed4d	blueswir1	#endif
1266	e8af50a3	bellard	gen_movl_T0_reg(rd);
1267	e8af50a3	bellard	break;
1268	3475187d	bellard	} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1269	e8af50a3	bellard	if (!supervisor(dc))
1270	e8af50a3	bellard	goto priv_insn;
1271	3475187d	bellard	#ifdef TARGET_SPARC64
1272	3475187d	bellard	rs1 = GET_FIELD(insn, 13, 17);
1273	3475187d	bellard	switch (rs1) {
1274	3475187d	bellard	case 0: // tpc
1275	3475187d	bellard	gen_op_rdtpc();
1276	3475187d	bellard	break;
1277	3475187d	bellard	case 1: // tnpc
1278	3475187d	bellard	gen_op_rdtnpc();
1279	3475187d	bellard	break;
1280	3475187d	bellard	case 2: // tstate
1281	3475187d	bellard	gen_op_rdtstate();
1282	3475187d	bellard	break;
1283	3475187d	bellard	case 3: // tt
1284	3475187d	bellard	gen_op_rdtt();
1285	3475187d	bellard	break;
1286	3475187d	bellard	case 4: // tick
1287	3475187d	bellard	gen_op_rdtick();
1288	3475187d	bellard	break;
1289	3475187d	bellard	case 5: // tba
1290	3475187d	bellard	gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1291	3475187d	bellard	break;
1292	3475187d	bellard	case 6: // pstate
1293	3475187d	bellard	gen_op_rdpstate();
1294	3475187d	bellard	break;
1295	3475187d	bellard	case 7: // tl
1296	3475187d	bellard	gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1297	3475187d	bellard	break;
1298	3475187d	bellard	case 8: // pil
1299	3475187d	bellard	gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1300	3475187d	bellard	break;
1301	3475187d	bellard	case 9: // cwp
1302	3475187d	bellard	gen_op_rdcwp();
1303	3475187d	bellard	break;
1304	3475187d	bellard	case 10: // cansave
1305	3475187d	bellard	gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1306	3475187d	bellard	break;
1307	3475187d	bellard	case 11: // canrestore
1308	3475187d	bellard	gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1309	3475187d	bellard	break;
1310	3475187d	bellard	case 12: // cleanwin
1311	3475187d	bellard	gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1312	3475187d	bellard	break;
1313	3475187d	bellard	case 13: // otherwin
1314	3475187d	bellard	gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1315	3475187d	bellard	break;
1316	3475187d	bellard	case 14: // wstate
1317	3475187d	bellard	gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1318	3475187d	bellard	break;
1319	e9ebed4d	blueswir1	case 16: // UA2005 gl
1320	e9ebed4d	blueswir1	gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
1321	e9ebed4d	blueswir1	break;
1322	e9ebed4d	blueswir1	case 26: // UA2005 strand status
1323	e9ebed4d	blueswir1	if (!hypervisor(dc))
1324	e9ebed4d	blueswir1	goto priv_insn;
1325	e9ebed4d	blueswir1	gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
1326	e9ebed4d	blueswir1	break;
1327	3475187d	bellard	case 31: // ver
1328	3475187d	bellard	gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1329	3475187d	bellard	break;
1330	3475187d	bellard	case 15: // fq
1331	3475187d	bellard	default:
1332	3475187d	bellard	goto illegal_insn;
1333	3475187d	bellard	}
1334	3475187d	bellard	#else
1335	3475187d	bellard	gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1336	3475187d	bellard	#endif
1337	e8af50a3	bellard	gen_movl_T0_reg(rd);
1338	e8af50a3	bellard	break;
1339	3475187d	bellard	} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1340	3475187d	bellard	#ifdef TARGET_SPARC64
1341	3475187d	bellard	gen_op_flushw();
1342	3475187d	bellard	#else
1343	e8af50a3	bellard	if (!supervisor(dc))
1344	e8af50a3	bellard	goto priv_insn;
1345	3475187d	bellard	gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1346	e8af50a3	bellard	gen_movl_T0_reg(rd);
1347	3475187d	bellard	#endif
1348	e8af50a3	bellard	break;
1349	e8af50a3	bellard	#endif
1350	e80cfcfc	bellard	} else if (xop == 0x34) { /* FPU Operations */
1351	a80dde08	bellard	if (gen_trap_ifnofpu(dc))
1352	a80dde08	bellard	goto jmp_insn;
1353	417454b0	blueswir1	gen_op_clear_ieee_excp_and_FTT();
1354	e8af50a3	bellard	rs1 = GET_FIELD(insn, 13, 17);
1355	e8af50a3	bellard	rs2 = GET_FIELD(insn, 27, 31);
1356	e8af50a3	bellard	xop = GET_FIELD(insn, 18, 26);
1357	e8af50a3	bellard	switch (xop) {
1358	e8af50a3	bellard	case 0x1: /* fmovs */
1359	e8af50a3	bellard	gen_op_load_fpr_FT0(rs2);
1360	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
1361	e8af50a3	bellard	break;
1362	e8af50a3	bellard	case 0x5: /* fnegs */
1363	e8af50a3	bellard	gen_op_load_fpr_FT1(rs2);
1364	e8af50a3	bellard	gen_op_fnegs();
1365	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
1366	e8af50a3	bellard	break;
1367	e8af50a3	bellard	case 0x9: /* fabss */
1368	e8af50a3	bellard	gen_op_load_fpr_FT1(rs2);
1369	e8af50a3	bellard	gen_op_fabss();
1370	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
1371	e8af50a3	bellard	break;
1372	e8af50a3	bellard	case 0x29: /* fsqrts */
1373	e8af50a3	bellard	gen_op_load_fpr_FT1(rs2);
1374	e8af50a3	bellard	gen_op_fsqrts();
1375	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
1376	e8af50a3	bellard	break;
1377	e8af50a3	bellard	case 0x2a: /* fsqrtd */
1378	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1379	e8af50a3	bellard	gen_op_fsqrtd();
1380	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1381	e8af50a3	bellard	break;
1382	e80cfcfc	bellard	case 0x2b: /* fsqrtq */
1383	e80cfcfc	bellard	goto nfpu_insn;
1384	e8af50a3	bellard	case 0x41:
1385	e8af50a3	bellard	gen_op_load_fpr_FT0(rs1);
1386	e8af50a3	bellard	gen_op_load_fpr_FT1(rs2);
1387	e8af50a3	bellard	gen_op_fadds();
1388	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
1389	e8af50a3	bellard	break;
1390	e8af50a3	bellard	case 0x42:
1391	3475187d	bellard	gen_op_load_fpr_DT0(DFPREG(rs1));
1392	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1393	e8af50a3	bellard	gen_op_faddd();
1394	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1395	e8af50a3	bellard	break;
1396	e80cfcfc	bellard	case 0x43: /* faddq */
1397	e80cfcfc	bellard	goto nfpu_insn;
1398	e8af50a3	bellard	case 0x45:
1399	e8af50a3	bellard	gen_op_load_fpr_FT0(rs1);
1400	e8af50a3	bellard	gen_op_load_fpr_FT1(rs2);
1401	e8af50a3	bellard	gen_op_fsubs();
1402	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
1403	e8af50a3	bellard	break;
1404	e8af50a3	bellard	case 0x46:
1405	3475187d	bellard	gen_op_load_fpr_DT0(DFPREG(rs1));
1406	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1407	e8af50a3	bellard	gen_op_fsubd();
1408	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1409	e8af50a3	bellard	break;
1410	e80cfcfc	bellard	case 0x47: /* fsubq */
1411	e80cfcfc	bellard	goto nfpu_insn;
1412	e8af50a3	bellard	case 0x49:
1413	e8af50a3	bellard	gen_op_load_fpr_FT0(rs1);
1414	e8af50a3	bellard	gen_op_load_fpr_FT1(rs2);
1415	e8af50a3	bellard	gen_op_fmuls();
1416	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
1417	e8af50a3	bellard	break;
1418	e8af50a3	bellard	case 0x4a:
1419	3475187d	bellard	gen_op_load_fpr_DT0(DFPREG(rs1));
1420	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1421	e8af50a3	bellard	gen_op_fmuld();
1422	e8af50a3	bellard	gen_op_store_DT0_fpr(rd);
1423	e8af50a3	bellard	break;
1424	e80cfcfc	bellard	case 0x4b: /* fmulq */
1425	e80cfcfc	bellard	goto nfpu_insn;
1426	e8af50a3	bellard	case 0x4d:
1427	e8af50a3	bellard	gen_op_load_fpr_FT0(rs1);
1428	e8af50a3	bellard	gen_op_load_fpr_FT1(rs2);
1429	e8af50a3	bellard	gen_op_fdivs();
1430	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
1431	e8af50a3	bellard	break;
1432	e8af50a3	bellard	case 0x4e:
1433	3475187d	bellard	gen_op_load_fpr_DT0(DFPREG(rs1));
1434	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1435	e8af50a3	bellard	gen_op_fdivd();
1436	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1437	e8af50a3	bellard	break;
1438	e80cfcfc	bellard	case 0x4f: /* fdivq */
1439	e80cfcfc	bellard	goto nfpu_insn;
1440	e8af50a3	bellard	case 0x69:
1441	e8af50a3	bellard	gen_op_load_fpr_FT0(rs1);
1442	e8af50a3	bellard	gen_op_load_fpr_FT1(rs2);
1443	e8af50a3	bellard	gen_op_fsmuld();
1444	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1445	e8af50a3	bellard	break;
1446	e80cfcfc	bellard	case 0x6e: /* fdmulq */
1447	e80cfcfc	bellard	goto nfpu_insn;
1448	e8af50a3	bellard	case 0xc4:
1449	e8af50a3	bellard	gen_op_load_fpr_FT1(rs2);
1450	e8af50a3	bellard	gen_op_fitos();
1451	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
1452	e8af50a3	bellard	break;
1453	e8af50a3	bellard	case 0xc6:
1454	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1455	e8af50a3	bellard	gen_op_fdtos();
1456	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
1457	e8af50a3	bellard	break;
1458	e80cfcfc	bellard	case 0xc7: /* fqtos */
1459	e80cfcfc	bellard	goto nfpu_insn;
1460	e8af50a3	bellard	case 0xc8:
1461	e8af50a3	bellard	gen_op_load_fpr_FT1(rs2);
1462	e8af50a3	bellard	gen_op_fitod();
1463	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1464	e8af50a3	bellard	break;
1465	e8af50a3	bellard	case 0xc9:
1466	e8af50a3	bellard	gen_op_load_fpr_FT1(rs2);
1467	e8af50a3	bellard	gen_op_fstod();
1468	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1469	e8af50a3	bellard	break;
1470	e80cfcfc	bellard	case 0xcb: /* fqtod */
1471	e80cfcfc	bellard	goto nfpu_insn;
1472	e80cfcfc	bellard	case 0xcc: /* fitoq */
1473	e80cfcfc	bellard	goto nfpu_insn;
1474	e80cfcfc	bellard	case 0xcd: /* fstoq */
1475	e80cfcfc	bellard	goto nfpu_insn;
1476	e80cfcfc	bellard	case 0xce: /* fdtoq */
1477	e80cfcfc	bellard	goto nfpu_insn;
1478	e8af50a3	bellard	case 0xd1:
1479	e8af50a3	bellard	gen_op_load_fpr_FT1(rs2);
1480	e8af50a3	bellard	gen_op_fstoi();
1481	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
1482	e8af50a3	bellard	break;
1483	e8af50a3	bellard	case 0xd2:
1484	e8af50a3	bellard	gen_op_load_fpr_DT1(rs2);
1485	e8af50a3	bellard	gen_op_fdtoi();
1486	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
1487	e8af50a3	bellard	break;
1488	e80cfcfc	bellard	case 0xd3: /* fqtoi */
1489	e80cfcfc	bellard	goto nfpu_insn;
1490	3475187d	bellard	#ifdef TARGET_SPARC64
1491	af7bf89b	bellard	case 0x2: /* V9 fmovd */
1492	3475187d	bellard	gen_op_load_fpr_DT0(DFPREG(rs2));
1493	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1494	3475187d	bellard	break;
1495	af7bf89b	bellard	case 0x6: /* V9 fnegd */
1496	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1497	3475187d	bellard	gen_op_fnegd();
1498	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1499	3475187d	bellard	break;
1500	af7bf89b	bellard	case 0xa: /* V9 fabsd */
1501	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1502	3475187d	bellard	gen_op_fabsd();
1503	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1504	3475187d	bellard	break;
1505	af7bf89b	bellard	case 0x81: /* V9 fstox */
1506	3475187d	bellard	gen_op_load_fpr_FT1(rs2);
1507	3475187d	bellard	gen_op_fstox();
1508	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1509	3475187d	bellard	break;
1510	af7bf89b	bellard	case 0x82: /* V9 fdtox */
1511	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1512	3475187d	bellard	gen_op_fdtox();
1513	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1514	3475187d	bellard	break;
1515	af7bf89b	bellard	case 0x84: /* V9 fxtos */
1516	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1517	3475187d	bellard	gen_op_fxtos();
1518	3475187d	bellard	gen_op_store_FT0_fpr(rd);
1519	3475187d	bellard	break;
1520	af7bf89b	bellard	case 0x88: /* V9 fxtod */
1521	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1522	3475187d	bellard	gen_op_fxtod();
1523	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
1524	3475187d	bellard	break;
1525	af7bf89b	bellard	case 0x3: /* V9 fmovq */
1526	af7bf89b	bellard	case 0x7: /* V9 fnegq */
1527	af7bf89b	bellard	case 0xb: /* V9 fabsq */
1528	af7bf89b	bellard	case 0x83: /* V9 fqtox */
1529	af7bf89b	bellard	case 0x8c: /* V9 fxtoq */
1530	3475187d	bellard	goto nfpu_insn;
1531	3475187d	bellard	#endif
1532	3475187d	bellard	default:
1533	e8af50a3	bellard	goto illegal_insn;
1534	e8af50a3	bellard	}
1535	e80cfcfc	bellard	} else if (xop == 0x35) { /* FPU Operations */
1536	3475187d	bellard	#ifdef TARGET_SPARC64
1537	3475187d	bellard	int cond;
1538	3475187d	bellard	#endif
1539	a80dde08	bellard	if (gen_trap_ifnofpu(dc))
1540	a80dde08	bellard	goto jmp_insn;
1541	417454b0	blueswir1	gen_op_clear_ieee_excp_and_FTT();
1542	cf495bcf	bellard	rs1 = GET_FIELD(insn, 13, 17);
1543	e80cfcfc	bellard	rs2 = GET_FIELD(insn, 27, 31);
1544	e80cfcfc	bellard	xop = GET_FIELD(insn, 18, 26);
1545	3475187d	bellard	#ifdef TARGET_SPARC64
1546	3475187d	bellard	if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1547	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1548	3475187d	bellard	gen_op_load_fpr_FT0(rd);
1549	3475187d	bellard	gen_op_load_fpr_FT1(rs2);
1550	3475187d	bellard	rs1 = GET_FIELD(insn, 13, 17);
1551	3475187d	bellard	gen_movl_reg_T0(rs1);
1552	3475187d	bellard	flush_T2(dc);
1553	3475187d	bellard	gen_cond_reg(cond);
1554	3475187d	bellard	gen_op_fmovs_cc();
1555	3475187d	bellard	gen_op_store_FT0_fpr(rd);
1556	3475187d	bellard	break;
1557	3475187d	bellard	} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1558	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1559	3475187d	bellard	gen_op_load_fpr_DT0(rd);
1560	3475187d	bellard	gen_op_load_fpr_DT1(rs2);
1561	3475187d	bellard	flush_T2(dc);
1562	3475187d	bellard	rs1 = GET_FIELD(insn, 13, 17);
1563	3475187d	bellard	gen_movl_reg_T0(rs1);
1564	3475187d	bellard	gen_cond_reg(cond);
1565	3475187d	bellard	gen_op_fmovs_cc();
1566	3475187d	bellard	gen_op_store_DT0_fpr(rd);
1567	3475187d	bellard	break;
1568	3475187d	bellard	} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1569	3475187d	bellard	goto nfpu_insn;
1570	3475187d	bellard	}
1571	3475187d	bellard	#endif
1572	e80cfcfc	bellard	switch (xop) {
1573	3475187d	bellard	#ifdef TARGET_SPARC64
1574	3475187d	bellard	case 0x001: /* V9 fmovscc %fcc0 */
1575	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1576	3475187d	bellard	gen_op_load_fpr_FT0(rd);
1577	3475187d	bellard	gen_op_load_fpr_FT1(rs2);
1578	3475187d	bellard	flush_T2(dc);
1579	3475187d	bellard	gen_fcond[0][cond]();
1580	3475187d	bellard	gen_op_fmovs_cc();
1581	3475187d	bellard	gen_op_store_FT0_fpr(rd);
1582	3475187d	bellard	break;
1583	3475187d	bellard	case 0x002: /* V9 fmovdcc %fcc0 */
1584	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1585	3475187d	bellard	gen_op_load_fpr_DT0(rd);
1586	3475187d	bellard	gen_op_load_fpr_DT1(rs2);
1587	3475187d	bellard	flush_T2(dc);
1588	3475187d	bellard	gen_fcond[0][cond]();
1589	3475187d	bellard	gen_op_fmovd_cc();
1590	3475187d	bellard	gen_op_store_DT0_fpr(rd);
1591	3475187d	bellard	break;
1592	3475187d	bellard	case 0x003: /* V9 fmovqcc %fcc0 */
1593	3475187d	bellard	goto nfpu_insn;
1594	3475187d	bellard	case 0x041: /* V9 fmovscc %fcc1 */
1595	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1596	3475187d	bellard	gen_op_load_fpr_FT0(rd);
1597	3475187d	bellard	gen_op_load_fpr_FT1(rs2);
1598	3475187d	bellard	flush_T2(dc);
1599	3475187d	bellard	gen_fcond[1][cond]();
1600	3475187d	bellard	gen_op_fmovs_cc();
1601	3475187d	bellard	gen_op_store_FT0_fpr(rd);
1602	3475187d	bellard	break;
1603	3475187d	bellard	case 0x042: /* V9 fmovdcc %fcc1 */
1604	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1605	3475187d	bellard	gen_op_load_fpr_DT0(rd);
1606	3475187d	bellard	gen_op_load_fpr_DT1(rs2);
1607	3475187d	bellard	flush_T2(dc);
1608	3475187d	bellard	gen_fcond[1][cond]();
1609	3475187d	bellard	gen_op_fmovd_cc();
1610	3475187d	bellard	gen_op_store_DT0_fpr(rd);
1611	3475187d	bellard	break;
1612	3475187d	bellard	case 0x043: /* V9 fmovqcc %fcc1 */
1613	3475187d	bellard	goto nfpu_insn;
1614	3475187d	bellard	case 0x081: /* V9 fmovscc %fcc2 */
1615	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1616	3475187d	bellard	gen_op_load_fpr_FT0(rd);
1617	3475187d	bellard	gen_op_load_fpr_FT1(rs2);
1618	3475187d	bellard	flush_T2(dc);
1619	3475187d	bellard	gen_fcond[2][cond]();
1620	3475187d	bellard	gen_op_fmovs_cc();
1621	3475187d	bellard	gen_op_store_FT0_fpr(rd);
1622	3475187d	bellard	break;
1623	3475187d	bellard	case 0x082: /* V9 fmovdcc %fcc2 */
1624	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1625	3475187d	bellard	gen_op_load_fpr_DT0(rd);
1626	3475187d	bellard	gen_op_load_fpr_DT1(rs2);
1627	3475187d	bellard	flush_T2(dc);
1628	3475187d	bellard	gen_fcond[2][cond]();
1629	3475187d	bellard	gen_op_fmovd_cc();
1630	3475187d	bellard	gen_op_store_DT0_fpr(rd);
1631	3475187d	bellard	break;
1632	3475187d	bellard	case 0x083: /* V9 fmovqcc %fcc2 */
1633	3475187d	bellard	goto nfpu_insn;
1634	3475187d	bellard	case 0x0c1: /* V9 fmovscc %fcc3 */
1635	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1636	3475187d	bellard	gen_op_load_fpr_FT0(rd);
1637	3475187d	bellard	gen_op_load_fpr_FT1(rs2);
1638	3475187d	bellard	flush_T2(dc);
1639	3475187d	bellard	gen_fcond[3][cond]();
1640	3475187d	bellard	gen_op_fmovs_cc();
1641	3475187d	bellard	gen_op_store_FT0_fpr(rd);
1642	3475187d	bellard	break;
1643	3475187d	bellard	case 0x0c2: /* V9 fmovdcc %fcc3 */
1644	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1645	3475187d	bellard	gen_op_load_fpr_DT0(rd);
1646	3475187d	bellard	gen_op_load_fpr_DT1(rs2);
1647	3475187d	bellard	flush_T2(dc);
1648	3475187d	bellard	gen_fcond[3][cond]();
1649	3475187d	bellard	gen_op_fmovd_cc();
1650	3475187d	bellard	gen_op_store_DT0_fpr(rd);
1651	3475187d	bellard	break;
1652	3475187d	bellard	case 0x0c3: /* V9 fmovqcc %fcc3 */
1653	3475187d	bellard	goto nfpu_insn;
1654	3475187d	bellard	case 0x101: /* V9 fmovscc %icc */
1655	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1656	3475187d	bellard	gen_op_load_fpr_FT0(rd);
1657	3475187d	bellard	gen_op_load_fpr_FT1(rs2);
1658	3475187d	bellard	flush_T2(dc);
1659	3475187d	bellard	gen_cond[0][cond]();
1660	3475187d	bellard	gen_op_fmovs_cc();
1661	3475187d	bellard	gen_op_store_FT0_fpr(rd);
1662	3475187d	bellard	break;
1663	3475187d	bellard	case 0x102: /* V9 fmovdcc %icc */
1664	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1665	3475187d	bellard	gen_op_load_fpr_DT0(rd);
1666	3475187d	bellard	gen_op_load_fpr_DT1(rs2);
1667	3475187d	bellard	flush_T2(dc);
1668	3475187d	bellard	gen_cond[0][cond]();
1669	3475187d	bellard	gen_op_fmovd_cc();
1670	3475187d	bellard	gen_op_store_DT0_fpr(rd);
1671	3475187d	bellard	break;
1672	3475187d	bellard	case 0x103: /* V9 fmovqcc %icc */
1673	3475187d	bellard	goto nfpu_insn;
1674	3475187d	bellard	case 0x181: /* V9 fmovscc %xcc */
1675	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1676	3475187d	bellard	gen_op_load_fpr_FT0(rd);
1677	3475187d	bellard	gen_op_load_fpr_FT1(rs2);
1678	3475187d	bellard	flush_T2(dc);
1679	3475187d	bellard	gen_cond[1][cond]();
1680	3475187d	bellard	gen_op_fmovs_cc();
1681	3475187d	bellard	gen_op_store_FT0_fpr(rd);
1682	3475187d	bellard	break;
1683	3475187d	bellard	case 0x182: /* V9 fmovdcc %xcc */
1684	3475187d	bellard	cond = GET_FIELD_SP(insn, 14, 17);
1685	3475187d	bellard	gen_op_load_fpr_DT0(rd);
1686	3475187d	bellard	gen_op_load_fpr_DT1(rs2);
1687	3475187d	bellard	flush_T2(dc);
1688	3475187d	bellard	gen_cond[1][cond]();
1689	3475187d	bellard	gen_op_fmovd_cc();
1690	3475187d	bellard	gen_op_store_DT0_fpr(rd);
1691	3475187d	bellard	break;
1692	3475187d	bellard	case 0x183: /* V9 fmovqcc %xcc */
1693	3475187d	bellard	goto nfpu_insn;
1694	3475187d	bellard	#endif
1695	3475187d	bellard	case 0x51: /* V9 %fcc */
1696	e80cfcfc	bellard	gen_op_load_fpr_FT0(rs1);
1697	e80cfcfc	bellard	gen_op_load_fpr_FT1(rs2);
1698	3475187d	bellard	#ifdef TARGET_SPARC64
1699	3475187d	bellard	gen_fcmps[rd & 3]();
1700	3475187d	bellard	#else
1701	e80cfcfc	bellard	gen_op_fcmps();
1702	3475187d	bellard	#endif
1703	e80cfcfc	bellard	break;
1704	3475187d	bellard	case 0x52: /* V9 %fcc */
1705	3475187d	bellard	gen_op_load_fpr_DT0(DFPREG(rs1));
1706	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1707	3475187d	bellard	#ifdef TARGET_SPARC64
1708	3475187d	bellard	gen_fcmpd[rd & 3]();
1709	3475187d	bellard	#else
1710	e80cfcfc	bellard	gen_op_fcmpd();
1711	3475187d	bellard	#endif
1712	e80cfcfc	bellard	break;
1713	e80cfcfc	bellard	case 0x53: /* fcmpq */
1714	e80cfcfc	bellard	goto nfpu_insn;
1715	3475187d	bellard	case 0x55: /* fcmpes, V9 %fcc */
1716	e80cfcfc	bellard	gen_op_load_fpr_FT0(rs1);
1717	e80cfcfc	bellard	gen_op_load_fpr_FT1(rs2);
1718	3475187d	bellard	#ifdef TARGET_SPARC64
1719	417454b0	blueswir1	gen_fcmpes[rd & 3]();
1720	3475187d	bellard	#else
1721	417454b0	blueswir1	gen_op_fcmpes();
1722	3475187d	bellard	#endif
1723	e80cfcfc	bellard	break;
1724	3475187d	bellard	case 0x56: /* fcmped, V9 %fcc */
1725	3475187d	bellard	gen_op_load_fpr_DT0(DFPREG(rs1));
1726	3475187d	bellard	gen_op_load_fpr_DT1(DFPREG(rs2));
1727	3475187d	bellard	#ifdef TARGET_SPARC64
1728	417454b0	blueswir1	gen_fcmped[rd & 3]();
1729	3475187d	bellard	#else
1730	417454b0	blueswir1	gen_op_fcmped();
1731	3475187d	bellard	#endif
1732	e80cfcfc	bellard	break;
1733	e80cfcfc	bellard	case 0x57: /* fcmpeq */
1734	e80cfcfc	bellard	goto nfpu_insn;
1735	e80cfcfc	bellard	default:
1736	e80cfcfc	bellard	goto illegal_insn;
1737	e80cfcfc	bellard	}
1738	e80cfcfc	bellard	#if defined(OPTIM)
1739	e80cfcfc	bellard	} else if (xop == 0x2) {
1740	e80cfcfc	bellard	// clr/mov shortcut
1741	e80cfcfc	bellard
1742	e80cfcfc	bellard	rs1 = GET_FIELD(insn, 13, 17);
1743	e80cfcfc	bellard	if (rs1 == 0) {
1744	e80cfcfc	bellard	// or %g0, x, y -> mov T1, x; mov y, T1
1745	e80cfcfc	bellard	if (IS_IMM) { /* immediate */
1746	e80cfcfc	bellard	rs2 = GET_FIELDs(insn, 19, 31);
1747	3475187d	bellard	gen_movl_simm_T1(rs2);
1748	e80cfcfc	bellard	} else { /* register */
1749	e80cfcfc	bellard	rs2 = GET_FIELD(insn, 27, 31);
1750	e80cfcfc	bellard	gen_movl_reg_T1(rs2);
1751	e80cfcfc	bellard	}
1752	e80cfcfc	bellard	gen_movl_T1_reg(rd);
1753	e80cfcfc	bellard	} else {
1754	e80cfcfc	bellard	gen_movl_reg_T0(rs1);
1755	e80cfcfc	bellard	if (IS_IMM) { /* immediate */
1756	e80cfcfc	bellard	// or x, #0, y -> mov T1, x; mov y, T1
1757	e80cfcfc	bellard	rs2 = GET_FIELDs(insn, 19, 31);
1758	e80cfcfc	bellard	if (rs2 != 0) {
1759	3475187d	bellard	gen_movl_simm_T1(rs2);
1760	e80cfcfc	bellard	gen_op_or_T1_T0();
1761	e80cfcfc	bellard	}
1762	e80cfcfc	bellard	} else { /* register */
1763	e80cfcfc	bellard	// or x, %g0, y -> mov T1, x; mov y, T1
1764	e80cfcfc	bellard	rs2 = GET_FIELD(insn, 27, 31);
1765	e80cfcfc	bellard	if (rs2 != 0) {
1766	e80cfcfc	bellard	gen_movl_reg_T1(rs2);
1767	e80cfcfc	bellard	gen_op_or_T1_T0();
1768	e80cfcfc	bellard	}
1769	e80cfcfc	bellard	}
1770	e80cfcfc	bellard	gen_movl_T0_reg(rd);
1771	e80cfcfc	bellard	}
1772	e80cfcfc	bellard	#endif
1773	83469015	bellard	#ifdef TARGET_SPARC64
1774	8a08f9a8	blueswir1	} else if (xop == 0x25) { /* sll, V9 sllx */
1775	83469015	bellard	rs1 = GET_FIELD(insn, 13, 17);
1776	83469015	bellard	gen_movl_reg_T0(rs1);
1777	83469015	bellard	if (IS_IMM) { /* immediate */
1778	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
1779	83469015	bellard	gen_movl_simm_T1(rs2);
1780	83469015	bellard	} else { /* register */
1781	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
1782	83469015	bellard	gen_movl_reg_T1(rs2);
1783	83469015	bellard	}
1784	8a08f9a8	blueswir1	if (insn & (1 << 12))
1785	8a08f9a8	blueswir1	gen_op_sllx();
1786	8a08f9a8	blueswir1	else
1787	8a08f9a8	blueswir1	gen_op_sll();
1788	83469015	bellard	gen_movl_T0_reg(rd);
1789	83469015	bellard	} else if (xop == 0x26) { /* srl, V9 srlx */
1790	83469015	bellard	rs1 = GET_FIELD(insn, 13, 17);
1791	83469015	bellard	gen_movl_reg_T0(rs1);
1792	83469015	bellard	if (IS_IMM) { /* immediate */
1793	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
1794	83469015	bellard	gen_movl_simm_T1(rs2);
1795	83469015	bellard	} else { /* register */
1796	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
1797	83469015	bellard	gen_movl_reg_T1(rs2);
1798	83469015	bellard	}
1799	83469015	bellard	if (insn & (1 << 12))
1800	83469015	bellard	gen_op_srlx();
1801	83469015	bellard	else
1802	83469015	bellard	gen_op_srl();
1803	83469015	bellard	gen_movl_T0_reg(rd);
1804	83469015	bellard	} else if (xop == 0x27) { /* sra, V9 srax */
1805	83469015	bellard	rs1 = GET_FIELD(insn, 13, 17);
1806	83469015	bellard	gen_movl_reg_T0(rs1);
1807	83469015	bellard	if (IS_IMM) { /* immediate */
1808	83469015	bellard	rs2 = GET_FIELDs(insn, 20, 31);
1809	83469015	bellard	gen_movl_simm_T1(rs2);
1810	83469015	bellard	} else { /* register */
1811	83469015	bellard	rs2 = GET_FIELD(insn, 27, 31);
1812	83469015	bellard	gen_movl_reg_T1(rs2);
1813	83469015	bellard	}
1814	83469015	bellard	if (insn & (1 << 12))
1815	83469015	bellard	gen_op_srax();
1816	83469015	bellard	else
1817	83469015	bellard	gen_op_sra();
1818	83469015	bellard	gen_movl_T0_reg(rd);
1819	83469015	bellard	#endif
1820	fcc72045	blueswir1	} else if (xop < 0x36) {
1821	e80cfcfc	bellard	rs1 = GET_FIELD(insn, 13, 17);
1822	e80cfcfc	bellard	gen_movl_reg_T0(rs1);
1823	e80cfcfc	bellard	if (IS_IMM) { /* immediate */
1824	cf495bcf	bellard	rs2 = GET_FIELDs(insn, 19, 31);
1825	3475187d	bellard	gen_movl_simm_T1(rs2);
1826	cf495bcf	bellard	} else { /* register */
1827	cf495bcf	bellard	rs2 = GET_FIELD(insn, 27, 31);
1828	cf495bcf	bellard	gen_movl_reg_T1(rs2);
1829	cf495bcf	bellard	}
1830	cf495bcf	bellard	if (xop < 0x20) {
1831	cf495bcf	bellard	switch (xop & ~0x10) {
1832	cf495bcf	bellard	case 0x0:
1833	cf495bcf	bellard	if (xop & 0x10)
1834	cf495bcf	bellard	gen_op_add_T1_T0_cc();
1835	cf495bcf	bellard	else
1836	cf495bcf	bellard	gen_op_add_T1_T0();
1837	cf495bcf	bellard	break;
1838	cf495bcf	bellard	case 0x1:
1839	cf495bcf	bellard	gen_op_and_T1_T0();
1840	cf495bcf	bellard	if (xop & 0x10)
1841	cf495bcf	bellard	gen_op_logic_T0_cc();
1842	cf495bcf	bellard	break;
1843	cf495bcf	bellard	case 0x2:
1844	e80cfcfc	bellard	gen_op_or_T1_T0();
1845	e80cfcfc	bellard	if (xop & 0x10)
1846	e80cfcfc	bellard	gen_op_logic_T0_cc();
1847	e80cfcfc	bellard	break;
1848	cf495bcf	bellard	case 0x3:
1849	cf495bcf	bellard	gen_op_xor_T1_T0();
1850	cf495bcf	bellard	if (xop & 0x10)
1851	cf495bcf	bellard	gen_op_logic_T0_cc();
1852	cf495bcf	bellard	break;
1853	cf495bcf	bellard	case 0x4:
1854	cf495bcf	bellard	if (xop & 0x10)
1855	cf495bcf	bellard	gen_op_sub_T1_T0_cc();
1856	cf495bcf	bellard	else
1857	cf495bcf	bellard	gen_op_sub_T1_T0();
1858	cf495bcf	bellard	break;
1859	cf495bcf	bellard	case 0x5:
1860	cf495bcf	bellard	gen_op_andn_T1_T0();
1861	cf495bcf	bellard	if (xop & 0x10)
1862	cf495bcf	bellard	gen_op_logic_T0_cc();
1863	cf495bcf	bellard	break;
1864	cf495bcf	bellard	case 0x6:
1865	cf495bcf	bellard	gen_op_orn_T1_T0();
1866	cf495bcf	bellard	if (xop & 0x10)
1867	cf495bcf	bellard	gen_op_logic_T0_cc();
1868	cf495bcf	bellard	break;
1869	cf495bcf	bellard	case 0x7:
1870	cf495bcf	bellard	gen_op_xnor_T1_T0();
1871	cf495bcf	bellard	if (xop & 0x10)
1872	cf495bcf	bellard	gen_op_logic_T0_cc();
1873	cf495bcf	bellard	break;
1874	cf495bcf	bellard	case 0x8:
1875	cf495bcf	bellard	if (xop & 0x10)
1876	af7bf89b	bellard	gen_op_addx_T1_T0_cc();
1877	af7bf89b	bellard	else
1878	af7bf89b	bellard	gen_op_addx_T1_T0();
1879	cf495bcf	bellard	break;
1880	ded3ab80	pbrook	#ifdef TARGET_SPARC64
1881	ded3ab80	pbrook	case 0x9: /* V9 mulx */
1882	ded3ab80	pbrook	gen_op_mulx_T1_T0();
1883	ded3ab80	pbrook	break;
1884	ded3ab80	pbrook	#endif
1885	cf495bcf	bellard	case 0xa:
1886	cf495bcf	bellard	gen_op_umul_T1_T0();
1887	cf495bcf	bellard	if (xop & 0x10)
1888	cf495bcf	bellard	gen_op_logic_T0_cc();
1889	cf495bcf	bellard	break;
1890	cf495bcf	bellard	case 0xb:
1891	cf495bcf	bellard	gen_op_smul_T1_T0();
1892	cf495bcf	bellard	if (xop & 0x10)
1893	cf495bcf	bellard	gen_op_logic_T0_cc();
1894	cf495bcf	bellard	break;
1895	cf495bcf	bellard	case 0xc:
1896	cf495bcf	bellard	if (xop & 0x10)
1897	af7bf89b	bellard	gen_op_subx_T1_T0_cc();
1898	af7bf89b	bellard	else
1899	af7bf89b	bellard	gen_op_subx_T1_T0();
1900	cf495bcf	bellard	break;
1901	ded3ab80	pbrook	#ifdef TARGET_SPARC64
1902	ded3ab80	pbrook	case 0xd: /* V9 udivx */
1903	ded3ab80	pbrook	gen_op_udivx_T1_T0();
1904	ded3ab80	pbrook	break;
1905	ded3ab80	pbrook	#endif
1906	cf495bcf	bellard	case 0xe:
1907	cf495bcf	bellard	gen_op_udiv_T1_T0();
1908	cf495bcf	bellard	if (xop & 0x10)
1909	cf495bcf	bellard	gen_op_div_cc();
1910	cf495bcf	bellard	break;
1911	cf495bcf	bellard	case 0xf:
1912	cf495bcf	bellard	gen_op_sdiv_T1_T0();
1913	cf495bcf	bellard	if (xop & 0x10)
1914	cf495bcf	bellard	gen_op_div_cc();
1915	cf495bcf	bellard	break;
1916	cf495bcf	bellard	default:
1917	cf495bcf	bellard	goto illegal_insn;
1918	cf495bcf	bellard	}
1919	e80cfcfc	bellard	gen_movl_T0_reg(rd);
1920	cf495bcf	bellard	} else {
1921	cf495bcf	bellard	switch (xop) {
1922	e80cfcfc	bellard	case 0x20: /* taddcc */
1923	e32f879d	blueswir1	gen_op_tadd_T1_T0_cc();
1924	e32f879d	blueswir1	gen_movl_T0_reg(rd);
1925	e32f879d	blueswir1	break;
1926	e80cfcfc	bellard	case 0x21: /* tsubcc */
1927	e32f879d	blueswir1	gen_op_tsub_T1_T0_cc();
1928	e32f879d	blueswir1	gen_movl_T0_reg(rd);
1929	e32f879d	blueswir1	break;
1930	e80cfcfc	bellard	case 0x22: /* taddcctv */
1931	e32f879d	blueswir1	gen_op_tadd_T1_T0_ccTV();
1932	e32f879d	blueswir1	gen_movl_T0_reg(rd);
1933	e32f879d	blueswir1	break;
1934	e80cfcfc	bellard	case 0x23: /* tsubcctv */
1935	e32f879d	blueswir1	gen_op_tsub_T1_T0_ccTV();
1936	e32f879d	blueswir1	gen_movl_T0_reg(rd);
1937	e32f879d	blueswir1	break;
1938	cf495bcf	bellard	case 0x24: /* mulscc */
1939	cf495bcf	bellard	gen_op_mulscc_T1_T0();
1940	cf495bcf	bellard	gen_movl_T0_reg(rd);
1941	cf495bcf	bellard	break;
1942	83469015	bellard	#ifndef TARGET_SPARC64
1943	83469015	bellard	case 0x25: /* sll */
1944	3475187d	bellard	gen_op_sll();
1945	cf495bcf	bellard	gen_movl_T0_reg(rd);
1946	cf495bcf	bellard	break;
1947	83469015	bellard	case 0x26: /* srl */
1948	3475187d	bellard	gen_op_srl();
1949	cf495bcf	bellard	gen_movl_T0_reg(rd);
1950	cf495bcf	bellard	break;
1951	83469015	bellard	case 0x27: /* sra */
1952	3475187d	bellard	gen_op_sra();
1953	cf495bcf	bellard	gen_movl_T0_reg(rd);
1954	cf495bcf	bellard	break;
1955	83469015	bellard	#endif
1956	cf495bcf	bellard	case 0x30:
1957	cf495bcf	bellard	{
1958	cf495bcf	bellard	switch(rd) {
1959	3475187d	bellard	case 0: /* wry */
1960	3475187d	bellard	gen_op_xor_T1_T0();
1961	3475187d	bellard	gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
1962	cf495bcf	bellard	break;
1963	65fe7b09	blueswir1	#ifndef TARGET_SPARC64
1964	65fe7b09	blueswir1	case 0x01 ... 0x0f: /* undefined in the
1965	65fe7b09	blueswir1	SPARCv8 manual, nop
1966	65fe7b09	blueswir1	on the microSPARC
1967	65fe7b09	blueswir1	II */
1968	65fe7b09	blueswir1	case 0x10 ... 0x1f: /* implementation-dependent
1969	65fe7b09	blueswir1	in the SPARCv8
1970	65fe7b09	blueswir1	manual, nop on the
1971	65fe7b09	blueswir1	microSPARC II */
1972	65fe7b09	blueswir1	break;
1973	65fe7b09	blueswir1	#else
1974	af7bf89b	bellard	case 0x2: /* V9 wrccr */
1975	3475187d	bellard	gen_op_wrccr();
1976	3475187d	bellard	break;
1977	af7bf89b	bellard	case 0x3: /* V9 wrasi */
1978	3475187d	bellard	gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1979	3475187d	bellard	break;
1980	af7bf89b	bellard	case 0x6: /* V9 wrfprs */
1981	3299908c	blueswir1	gen_op_xor_T1_T0();
1982	3475187d	bellard	gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
1983	3299908c	blueswir1	save_state(dc);
1984	3299908c	blueswir1	gen_op_next_insn();
1985	3299908c	blueswir1	gen_op_movl_T0_0();
1986	3299908c	blueswir1	gen_op_exit_tb();
1987	3299908c	blueswir1	dc->is_br = 1;
1988	3475187d	bellard	break;
1989	3475187d	bellard	case 0xf: /* V9 sir, nop if user */
1990	3475187d	bellard	#if !defined(CONFIG_USER_ONLY)
1991	3475187d	bellard	if (supervisor(dc))
1992	3475187d	bellard	gen_op_sir();
1993	3475187d	bellard	#endif
1994	3475187d	bellard	break;
1995	725cb90b	bellard	case 0x13: /* Graphics Status */
1996	725cb90b	bellard	if (gen_trap_ifnofpu(dc))
1997	725cb90b	bellard	goto jmp_insn;
1998	725cb90b	bellard	gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
1999	725cb90b	bellard	break;
2000	83469015	bellard	case 0x17: /* Tick compare */
2001	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
2002	83469015	bellard	if (!supervisor(dc))
2003	83469015	bellard	goto illegal_insn;
2004	83469015	bellard	#endif
2005	20c9f095	blueswir1	gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
2006	20c9f095	blueswir1	gen_op_wrtick_cmpr();
2007	83469015	bellard	break;
2008	83469015	bellard	case 0x18: /* System tick */
2009	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
2010	83469015	bellard	if (!supervisor(dc))
2011	83469015	bellard	goto illegal_insn;
2012	83469015	bellard	#endif
2013	20c9f095	blueswir1	gen_op_wrstick();
2014	83469015	bellard	break;
2015	83469015	bellard	case 0x19: /* System tick compare */
2016	83469015	bellard	#if !defined(CONFIG_USER_ONLY)
2017	83469015	bellard	if (!supervisor(dc))
2018	83469015	bellard	goto illegal_insn;
2019	3475187d	bellard	#endif
2020	20c9f095	blueswir1	gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
2021	20c9f095	blueswir1	gen_op_wrstick_cmpr();
2022	83469015	bellard	break;
2023	83469015	bellard
2024	3475187d	bellard	case 0x10: /* Performance Control */
2025	3475187d	bellard	case 0x11: /* Performance Instrumentation Counter */
2026	3475187d	bellard	case 0x12: /* Dispatch Control */
2027	3475187d	bellard	case 0x14: /* Softint set */
2028	3475187d	bellard	case 0x15: /* Softint clear */
2029	3475187d	bellard	case 0x16: /* Softint write */
2030	83469015	bellard	#endif
2031	3475187d	bellard	default:
2032	cf495bcf	bellard	goto illegal_insn;
2033	cf495bcf	bellard	}
2034	cf495bcf	bellard	}
2035	cf495bcf	bellard	break;
2036	e8af50a3	bellard	#if !defined(CONFIG_USER_ONLY)
2037	af7bf89b	bellard	case 0x31: /* wrpsr, V9 saved, restored */
2038	e8af50a3	bellard	{
2039	e8af50a3	bellard	if (!supervisor(dc))
2040	e8af50a3	bellard	goto priv_insn;
2041	3475187d	bellard	#ifdef TARGET_SPARC64
2042	3475187d	bellard	switch (rd) {
2043	3475187d	bellard	case 0:
2044	3475187d	bellard	gen_op_saved();
2045	3475187d	bellard	break;
2046	3475187d	bellard	case 1:
2047	3475187d	bellard	gen_op_restored();
2048	3475187d	bellard	break;
2049	e9ebed4d	blueswir1	case 2: /* UA2005 allclean */
2050	e9ebed4d	blueswir1	case 3: /* UA2005 otherw */
2051	e9ebed4d	blueswir1	case 4: /* UA2005 normalw */
2052	e9ebed4d	blueswir1	case 5: /* UA2005 invalw */
2053	e9ebed4d	blueswir1	// XXX
2054	3475187d	bellard	default:
2055	3475187d	bellard	goto illegal_insn;
2056	3475187d	bellard	}
2057	3475187d	bellard	#else
2058	e8af50a3	bellard	gen_op_xor_T1_T0();
2059	e8af50a3	bellard	gen_op_wrpsr();
2060	9e61bde5	bellard	save_state(dc);
2061	9e61bde5	bellard	gen_op_next_insn();
2062	9e61bde5	bellard	gen_op_movl_T0_0();
2063	9e61bde5	bellard	gen_op_exit_tb();
2064	9e61bde5	bellard	dc->is_br = 1;
2065	3475187d	bellard	#endif
2066	e8af50a3	bellard	}
2067	e8af50a3	bellard	break;
2068	af7bf89b	bellard	case 0x32: /* wrwim, V9 wrpr */
2069	e8af50a3	bellard	{
2070	e8af50a3	bellard	if (!supervisor(dc))
2071	e8af50a3	bellard	goto priv_insn;
2072	e8af50a3	bellard	gen_op_xor_T1_T0();
2073	3475187d	bellard	#ifdef TARGET_SPARC64
2074	3475187d	bellard	switch (rd) {
2075	3475187d	bellard	case 0: // tpc
2076	3475187d	bellard	gen_op_wrtpc();
2077	3475187d	bellard	break;
2078	3475187d	bellard	case 1: // tnpc
2079	3475187d	bellard	gen_op_wrtnpc();
2080	3475187d	bellard	break;
2081	3475187d	bellard	case 2: // tstate
2082	3475187d	bellard	gen_op_wrtstate();
2083	3475187d	bellard	break;
2084	3475187d	bellard	case 3: // tt
2085	3475187d	bellard	gen_op_wrtt();
2086	3475187d	bellard	break;
2087	3475187d	bellard	case 4: // tick
2088	3475187d	bellard	gen_op_wrtick();
2089	3475187d	bellard	break;
2090	3475187d	bellard	case 5: // tba
2091	83469015	bellard	gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2092	3475187d	bellard	break;
2093	3475187d	bellard	case 6: // pstate
2094	3475187d	bellard	gen_op_wrpstate();
2095	ded3ab80	pbrook	save_state(dc);
2096	ded3ab80	pbrook	gen_op_next_insn();
2097	ded3ab80	pbrook	gen_op_movl_T0_0();
2098	ded3ab80	pbrook	gen_op_exit_tb();
2099	ded3ab80	pbrook	dc->is_br = 1;
2100	3475187d	bellard	break;
2101	3475187d	bellard	case 7: // tl
2102	3475187d	bellard	gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
2103	3475187d	bellard	break;
2104	3475187d	bellard	case 8: // pil
2105	3475187d	bellard	gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
2106	3475187d	bellard	break;
2107	3475187d	bellard	case 9: // cwp
2108	3475187d	bellard	gen_op_wrcwp();
2109	3475187d	bellard	break;
2110	3475187d	bellard	case 10: // cansave
2111	3475187d	bellard	gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
2112	3475187d	bellard	break;
2113	3475187d	bellard	case 11: // canrestore
2114	3475187d	bellard	gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
2115	3475187d	bellard	break;
2116	3475187d	bellard	case 12: // cleanwin
2117	3475187d	bellard	gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
2118	3475187d	bellard	break;
2119	3475187d	bellard	case 13: // otherwin
2120	3475187d	bellard	gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
2121	3475187d	bellard	break;
2122	3475187d	bellard	case 14: // wstate
2123	3475187d	bellard	gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
2124	3475187d	bellard	break;
2125	e9ebed4d	blueswir1	case 16: // UA2005 gl
2126	e9ebed4d	blueswir1	gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
2127	e9ebed4d	blueswir1	break;
2128	e9ebed4d	blueswir1	case 26: // UA2005 strand status
2129	e9ebed4d	blueswir1	if (!hypervisor(dc))
2130	e9ebed4d	blueswir1	goto priv_insn;
2131	e9ebed4d	blueswir1	gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
2132	e9ebed4d	blueswir1	break;
2133	3475187d	bellard	default:
2134	3475187d	bellard	goto illegal_insn;
2135	3475187d	bellard	}
2136	3475187d	bellard	#else
2137	c688a6eb	bellard	gen_op_wrwim();
2138	3475187d	bellard	#endif
2139	e8af50a3	bellard	}
2140	e8af50a3	bellard	break;
2141	e9ebed4d	blueswir1	case 0x33: /* wrtbr, UA2005 wrhpr */
2142	e8af50a3	bellard	{
2143	e9ebed4d	blueswir1	#ifndef TARGET_SPARC64
2144	e8af50a3	bellard	if (!supervisor(dc))
2145	e8af50a3	bellard	goto priv_insn;
2146	e8af50a3	bellard	gen_op_xor_T1_T0();
2147	e9ebed4d	blueswir1	gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
2148	e9ebed4d	blueswir1	#else
2149	e9ebed4d	blueswir1	if (!hypervisor(dc))
2150	e9ebed4d	blueswir1	goto priv_insn;
2151	e9ebed4d	blueswir1	gen_op_xor_T1_T0();
2152	e9ebed4d	blueswir1	switch (rd) {
2153	e9ebed4d	blueswir1	case 0: // hpstate
2154	e9ebed4d	blueswir1	// XXX gen_op_wrhpstate();
2155	e9ebed4d	blueswir1	save_state(dc);
2156	e9ebed4d	blueswir1	gen_op_next_insn();
2157	e9ebed4d	blueswir1	gen_op_movl_T0_0();
2158	e9ebed4d	blueswir1	gen_op_exit_tb();
2159	e9ebed4d	blueswir1	dc->is_br = 1;
2160	e9ebed4d	blueswir1	break;
2161	e9ebed4d	blueswir1	case 1: // htstate
2162	e9ebed4d	blueswir1	// XXX gen_op_wrhtstate();
2163	e9ebed4d	blueswir1	break;
2164	e9ebed4d	blueswir1	case 3: // hintp
2165	e9ebed4d	blueswir1	gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
2166	e9ebed4d	blueswir1	break;
2167	e9ebed4d	blueswir1	case 5: // htba
2168	e9ebed4d	blueswir1	gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
2169	e9ebed4d	blueswir1	break;
2170	e9ebed4d	blueswir1	case 31: // hstick_cmpr
2171	20c9f095	blueswir1	gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2172	20c9f095	blueswir1	gen_op_wrhstick_cmpr();
2173	e9ebed4d	blueswir1	break;
2174	e9ebed4d	blueswir1	case 6: // hver readonly
2175	e9ebed4d	blueswir1	default:
2176	e9ebed4d	blueswir1	goto illegal_insn;
2177	e9ebed4d	blueswir1	}
2178	e9ebed4d	blueswir1	#endif
2179	e8af50a3	bellard	}
2180	e8af50a3	bellard	break;
2181	e8af50a3	bellard	#endif
2182	3475187d	bellard	#ifdef TARGET_SPARC64
2183	af7bf89b	bellard	case 0x2c: /* V9 movcc */
2184	3475187d	bellard	{
2185	3475187d	bellard	int cc = GET_FIELD_SP(insn, 11, 12);
2186	3475187d	bellard	int cond = GET_FIELD_SP(insn, 14, 17);
2187	3475187d	bellard	if (IS_IMM) { /* immediate */
2188	3475187d	bellard	rs2 = GET_FIELD_SPs(insn, 0, 10);
2189	3475187d	bellard	gen_movl_simm_T1(rs2);
2190	3475187d	bellard	}
2191	3475187d	bellard	else {
2192	3475187d	bellard	rs2 = GET_FIELD_SP(insn, 0, 4);
2193	3475187d	bellard	gen_movl_reg_T1(rs2);
2194	3475187d	bellard	}
2195	3475187d	bellard	gen_movl_reg_T0(rd);
2196	3475187d	bellard	flush_T2(dc);
2197	3475187d	bellard	if (insn & (1 << 18)) {
2198	3475187d	bellard	if (cc == 0)
2199	3475187d	bellard	gen_cond[0][cond]();
2200	3475187d	bellard	else if (cc == 2)
2201	3475187d	bellard	gen_cond[1][cond]();
2202	3475187d	bellard	else
2203	3475187d	bellard	goto illegal_insn;
2204	3475187d	bellard	} else {
2205	3475187d	bellard	gen_fcond[cc][cond]();
2206	3475187d	bellard	}
2207	3475187d	bellard	gen_op_mov_cc();
2208	3475187d	bellard	gen_movl_T0_reg(rd);
2209	3475187d	bellard	break;
2210	3475187d	bellard	}
2211	af7bf89b	bellard	case 0x2d: /* V9 sdivx */
2212	3475187d	bellard	gen_op_sdivx_T1_T0();
2213	3475187d	bellard	gen_movl_T0_reg(rd);
2214	3475187d	bellard	break;
2215	af7bf89b	bellard	case 0x2e: /* V9 popc */
2216	3475187d	bellard	{
2217	3475187d	bellard	if (IS_IMM) { /* immediate */
2218	3475187d	bellard	rs2 = GET_FIELD_SPs(insn, 0, 12);
2219	3475187d	bellard	gen_movl_simm_T1(rs2);
2220	3475187d	bellard	// XXX optimize: popc(constant)
2221	3475187d	bellard	}
2222	3475187d	bellard	else {
2223	3475187d	bellard	rs2 = GET_FIELD_SP(insn, 0, 4);
2224	3475187d	bellard	gen_movl_reg_T1(rs2);
2225	3475187d	bellard	}
2226	3475187d	bellard	gen_op_popc();
2227	3475187d	bellard	gen_movl_T0_reg(rd);
2228	3475187d	bellard	}
2229	af7bf89b	bellard	case 0x2f: /* V9 movr */
2230	3475187d	bellard	{
2231	3475187d	bellard	int cond = GET_FIELD_SP(insn, 10, 12);
2232	3475187d	bellard	rs1 = GET_FIELD(insn, 13, 17);
2233	3475187d	bellard	flush_T2(dc);
2234	3475187d	bellard	gen_movl_reg_T0(rs1);
2235	3475187d	bellard	gen_cond_reg(cond);
2236	3475187d	bellard	if (IS_IMM) { /* immediate */
2237	46d38ba8	blueswir1	rs2 = GET_FIELD_SPs(insn, 0, 9);
2238	3475187d	bellard	gen_movl_simm_T1(rs2);
2239	3475187d	bellard	}
2240	3475187d	bellard	else {
2241	3475187d	bellard	rs2 = GET_FIELD_SP(insn, 0, 4);
2242	3475187d	bellard	gen_movl_reg_T1(rs2);
2243	3475187d	bellard	}
2244	3475187d	bellard	gen_movl_reg_T0(rd);
2245	3475187d	bellard	gen_op_mov_cc();
2246	3475187d	bellard	gen_movl_T0_reg(rd);
2247	3475187d	bellard	break;
2248	3475187d	bellard	}
2249	3475187d	bellard	#endif
2250	3475187d	bellard	default:
2251	e80cfcfc	bellard	goto illegal_insn;
2252	e80cfcfc	bellard	}
2253	e80cfcfc	bellard	}
2254	3299908c	blueswir1	} else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
2255	3299908c	blueswir1	#ifdef TARGET_SPARC64
2256	3299908c	blueswir1	int opf = GET_FIELD_SP(insn, 5, 13);
2257	3299908c	blueswir1	rs1 = GET_FIELD(insn, 13, 17);
2258	3299908c	blueswir1	rs2 = GET_FIELD(insn, 27, 31);
2259	e9ebed4d	blueswir1	if (gen_trap_ifnofpu(dc))
2260	e9ebed4d	blueswir1	goto jmp_insn;
2261	3299908c	blueswir1
2262	3299908c	blueswir1	switch (opf) {
2263	e9ebed4d	blueswir1	case 0x000: /* VIS I edge8cc */
2264	e9ebed4d	blueswir1	case 0x001: /* VIS II edge8n */
2265	e9ebed4d	blueswir1	case 0x002: /* VIS I edge8lcc */
2266	e9ebed4d	blueswir1	case 0x003: /* VIS II edge8ln */
2267	e9ebed4d	blueswir1	case 0x004: /* VIS I edge16cc */
2268	e9ebed4d	blueswir1	case 0x005: /* VIS II edge16n */
2269	e9ebed4d	blueswir1	case 0x006: /* VIS I edge16lcc */
2270	e9ebed4d	blueswir1	case 0x007: /* VIS II edge16ln */
2271	e9ebed4d	blueswir1	case 0x008: /* VIS I edge32cc */
2272	e9ebed4d	blueswir1	case 0x009: /* VIS II edge32n */
2273	e9ebed4d	blueswir1	case 0x00a: /* VIS I edge32lcc */
2274	e9ebed4d	blueswir1	case 0x00b: /* VIS II edge32ln */
2275	e9ebed4d	blueswir1	// XXX
2276	e9ebed4d	blueswir1	goto illegal_insn;
2277	e9ebed4d	blueswir1	case 0x010: /* VIS I array8 */
2278	e9ebed4d	blueswir1	gen_movl_reg_T0(rs1);
2279	e9ebed4d	blueswir1	gen_movl_reg_T1(rs2);
2280	e9ebed4d	blueswir1	gen_op_array8();
2281	e9ebed4d	blueswir1	gen_movl_T0_reg(rd);
2282	e9ebed4d	blueswir1	break;
2283	e9ebed4d	blueswir1	case 0x012: /* VIS I array16 */
2284	e9ebed4d	blueswir1	gen_movl_reg_T0(rs1);
2285	e9ebed4d	blueswir1	gen_movl_reg_T1(rs2);
2286	e9ebed4d	blueswir1	gen_op_array16();
2287	e9ebed4d	blueswir1	gen_movl_T0_reg(rd);
2288	e9ebed4d	blueswir1	break;
2289	e9ebed4d	blueswir1	case 0x014: /* VIS I array32 */
2290	e9ebed4d	blueswir1	gen_movl_reg_T0(rs1);
2291	e9ebed4d	blueswir1	gen_movl_reg_T1(rs2);
2292	e9ebed4d	blueswir1	gen_op_array32();
2293	e9ebed4d	blueswir1	gen_movl_T0_reg(rd);
2294	e9ebed4d	blueswir1	break;
2295	3299908c	blueswir1	case 0x018: /* VIS I alignaddr */
2296	3299908c	blueswir1	gen_movl_reg_T0(rs1);
2297	3299908c	blueswir1	gen_movl_reg_T1(rs2);
2298	3299908c	blueswir1	gen_op_alignaddr();
2299	3299908c	blueswir1	gen_movl_T0_reg(rd);
2300	3299908c	blueswir1	break;
2301	e9ebed4d	blueswir1	case 0x019: /* VIS II bmask */
2302	3299908c	blueswir1	case 0x01a: /* VIS I alignaddrl */
2303	3299908c	blueswir1	// XXX
2304	e9ebed4d	blueswir1	goto illegal_insn;
2305	e9ebed4d	blueswir1	case 0x020: /* VIS I fcmple16 */
2306	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2307	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2308	e9ebed4d	blueswir1	gen_op_fcmple16();
2309	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2310	e9ebed4d	blueswir1	break;
2311	e9ebed4d	blueswir1	case 0x022: /* VIS I fcmpne16 */
2312	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2313	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2314	e9ebed4d	blueswir1	gen_op_fcmpne16();
2315	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2316	3299908c	blueswir1	break;
2317	e9ebed4d	blueswir1	case 0x024: /* VIS I fcmple32 */
2318	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2319	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2320	e9ebed4d	blueswir1	gen_op_fcmple32();
2321	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2322	e9ebed4d	blueswir1	break;
2323	e9ebed4d	blueswir1	case 0x026: /* VIS I fcmpne32 */
2324	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2325	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2326	e9ebed4d	blueswir1	gen_op_fcmpne32();
2327	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2328	e9ebed4d	blueswir1	break;
2329	e9ebed4d	blueswir1	case 0x028: /* VIS I fcmpgt16 */
2330	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2331	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2332	e9ebed4d	blueswir1	gen_op_fcmpgt16();
2333	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2334	e9ebed4d	blueswir1	break;
2335	e9ebed4d	blueswir1	case 0x02a: /* VIS I fcmpeq16 */
2336	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2337	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2338	e9ebed4d	blueswir1	gen_op_fcmpeq16();
2339	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2340	e9ebed4d	blueswir1	break;
2341	e9ebed4d	blueswir1	case 0x02c: /* VIS I fcmpgt32 */
2342	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2343	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2344	e9ebed4d	blueswir1	gen_op_fcmpgt32();
2345	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2346	e9ebed4d	blueswir1	break;
2347	e9ebed4d	blueswir1	case 0x02e: /* VIS I fcmpeq32 */
2348	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2349	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2350	e9ebed4d	blueswir1	gen_op_fcmpeq32();
2351	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2352	e9ebed4d	blueswir1	break;
2353	e9ebed4d	blueswir1	case 0x031: /* VIS I fmul8x16 */
2354	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2355	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2356	e9ebed4d	blueswir1	gen_op_fmul8x16();
2357	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2358	e9ebed4d	blueswir1	break;
2359	e9ebed4d	blueswir1	case 0x033: /* VIS I fmul8x16au */
2360	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2361	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2362	e9ebed4d	blueswir1	gen_op_fmul8x16au();
2363	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2364	e9ebed4d	blueswir1	break;
2365	e9ebed4d	blueswir1	case 0x035: /* VIS I fmul8x16al */
2366	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2367	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2368	e9ebed4d	blueswir1	gen_op_fmul8x16al();
2369	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2370	e9ebed4d	blueswir1	break;
2371	e9ebed4d	blueswir1	case 0x036: /* VIS I fmul8sux16 */
2372	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2373	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2374	e9ebed4d	blueswir1	gen_op_fmul8sux16();
2375	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2376	e9ebed4d	blueswir1	break;
2377	e9ebed4d	blueswir1	case 0x037: /* VIS I fmul8ulx16 */
2378	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2379	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2380	e9ebed4d	blueswir1	gen_op_fmul8ulx16();
2381	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2382	e9ebed4d	blueswir1	break;
2383	e9ebed4d	blueswir1	case 0x038: /* VIS I fmuld8sux16 */
2384	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2385	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2386	e9ebed4d	blueswir1	gen_op_fmuld8sux16();
2387	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2388	e9ebed4d	blueswir1	break;
2389	e9ebed4d	blueswir1	case 0x039: /* VIS I fmuld8ulx16 */
2390	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2391	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2392	e9ebed4d	blueswir1	gen_op_fmuld8ulx16();
2393	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2394	e9ebed4d	blueswir1	break;
2395	e9ebed4d	blueswir1	case 0x03a: /* VIS I fpack32 */
2396	e9ebed4d	blueswir1	case 0x03b: /* VIS I fpack16 */
2397	e9ebed4d	blueswir1	case 0x03d: /* VIS I fpackfix */
2398	e9ebed4d	blueswir1	case 0x03e: /* VIS I pdist */
2399	e9ebed4d	blueswir1	// XXX
2400	e9ebed4d	blueswir1	goto illegal_insn;
2401	3299908c	blueswir1	case 0x048: /* VIS I faligndata */
2402	3299908c	blueswir1	gen_op_load_fpr_DT0(rs1);
2403	3299908c	blueswir1	gen_op_load_fpr_DT1(rs2);
2404	3299908c	blueswir1	gen_op_faligndata();
2405	3299908c	blueswir1	gen_op_store_DT0_fpr(rd);
2406	3299908c	blueswir1	break;
2407	e9ebed4d	blueswir1	case 0x04b: /* VIS I fpmerge */
2408	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2409	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2410	e9ebed4d	blueswir1	gen_op_fpmerge();
2411	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2412	e9ebed4d	blueswir1	break;
2413	e9ebed4d	blueswir1	case 0x04c: /* VIS II bshuffle */
2414	e9ebed4d	blueswir1	// XXX
2415	e9ebed4d	blueswir1	goto illegal_insn;
2416	e9ebed4d	blueswir1	case 0x04d: /* VIS I fexpand */
2417	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2418	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2419	e9ebed4d	blueswir1	gen_op_fexpand();
2420	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2421	e9ebed4d	blueswir1	break;
2422	e9ebed4d	blueswir1	case 0x050: /* VIS I fpadd16 */
2423	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2424	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2425	e9ebed4d	blueswir1	gen_op_fpadd16();
2426	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2427	e9ebed4d	blueswir1	break;
2428	e9ebed4d	blueswir1	case 0x051: /* VIS I fpadd16s */
2429	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
2430	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2431	e9ebed4d	blueswir1	gen_op_fpadd16s();
2432	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2433	e9ebed4d	blueswir1	break;
2434	e9ebed4d	blueswir1	case 0x052: /* VIS I fpadd32 */
2435	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2436	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2437	e9ebed4d	blueswir1	gen_op_fpadd32();
2438	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2439	e9ebed4d	blueswir1	break;
2440	e9ebed4d	blueswir1	case 0x053: /* VIS I fpadd32s */
2441	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
2442	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2443	e9ebed4d	blueswir1	gen_op_fpadd32s();
2444	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2445	e9ebed4d	blueswir1	break;
2446	e9ebed4d	blueswir1	case 0x054: /* VIS I fpsub16 */
2447	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2448	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2449	e9ebed4d	blueswir1	gen_op_fpsub16();
2450	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2451	e9ebed4d	blueswir1	break;
2452	e9ebed4d	blueswir1	case 0x055: /* VIS I fpsub16s */
2453	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
2454	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2455	e9ebed4d	blueswir1	gen_op_fpsub16s();
2456	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2457	e9ebed4d	blueswir1	break;
2458	e9ebed4d	blueswir1	case 0x056: /* VIS I fpsub32 */
2459	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2460	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2461	e9ebed4d	blueswir1	gen_op_fpadd32();
2462	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2463	e9ebed4d	blueswir1	break;
2464	e9ebed4d	blueswir1	case 0x057: /* VIS I fpsub32s */
2465	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
2466	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2467	e9ebed4d	blueswir1	gen_op_fpsub32s();
2468	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2469	e9ebed4d	blueswir1	break;
2470	3299908c	blueswir1	case 0x060: /* VIS I fzero */
2471	3299908c	blueswir1	gen_op_movl_DT0_0();
2472	3299908c	blueswir1	gen_op_store_DT0_fpr(rd);
2473	3299908c	blueswir1	break;
2474	3299908c	blueswir1	case 0x061: /* VIS I fzeros */
2475	3299908c	blueswir1	gen_op_movl_FT0_0();
2476	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
2477	3299908c	blueswir1	break;
2478	e9ebed4d	blueswir1	case 0x062: /* VIS I fnor */
2479	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2480	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2481	e9ebed4d	blueswir1	gen_op_fnor();
2482	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2483	e9ebed4d	blueswir1	break;
2484	e9ebed4d	blueswir1	case 0x063: /* VIS I fnors */
2485	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
2486	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2487	e9ebed4d	blueswir1	gen_op_fnors();
2488	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2489	e9ebed4d	blueswir1	break;
2490	e9ebed4d	blueswir1	case 0x064: /* VIS I fandnot2 */
2491	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs1);
2492	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs2);
2493	e9ebed4d	blueswir1	gen_op_fandnot();
2494	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2495	e9ebed4d	blueswir1	break;
2496	e9ebed4d	blueswir1	case 0x065: /* VIS I fandnot2s */
2497	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
2498	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs2);
2499	e9ebed4d	blueswir1	gen_op_fandnots();
2500	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2501	e9ebed4d	blueswir1	break;
2502	e9ebed4d	blueswir1	case 0x066: /* VIS I fnot2 */
2503	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2504	e9ebed4d	blueswir1	gen_op_fnot();
2505	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2506	e9ebed4d	blueswir1	break;
2507	e9ebed4d	blueswir1	case 0x067: /* VIS I fnot2s */
2508	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2509	e9ebed4d	blueswir1	gen_op_fnot();
2510	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2511	e9ebed4d	blueswir1	break;
2512	e9ebed4d	blueswir1	case 0x068: /* VIS I fandnot1 */
2513	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2514	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2515	e9ebed4d	blueswir1	gen_op_fandnot();
2516	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2517	e9ebed4d	blueswir1	break;
2518	e9ebed4d	blueswir1	case 0x069: /* VIS I fandnot1s */
2519	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
2520	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2521	e9ebed4d	blueswir1	gen_op_fandnots();
2522	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2523	e9ebed4d	blueswir1	break;
2524	e9ebed4d	blueswir1	case 0x06a: /* VIS I fnot1 */
2525	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs1);
2526	e9ebed4d	blueswir1	gen_op_fnot();
2527	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2528	e9ebed4d	blueswir1	break;
2529	e9ebed4d	blueswir1	case 0x06b: /* VIS I fnot1s */
2530	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
2531	e9ebed4d	blueswir1	gen_op_fnot();
2532	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2533	e9ebed4d	blueswir1	break;
2534	e9ebed4d	blueswir1	case 0x06c: /* VIS I fxor */
2535	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2536	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2537	e9ebed4d	blueswir1	gen_op_fxor();
2538	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2539	e9ebed4d	blueswir1	break;
2540	e9ebed4d	blueswir1	case 0x06d: /* VIS I fxors */
2541	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
2542	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2543	e9ebed4d	blueswir1	gen_op_fxors();
2544	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2545	e9ebed4d	blueswir1	break;
2546	e9ebed4d	blueswir1	case 0x06e: /* VIS I fnand */
2547	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2548	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2549	e9ebed4d	blueswir1	gen_op_fnand();
2550	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2551	e9ebed4d	blueswir1	break;
2552	e9ebed4d	blueswir1	case 0x06f: /* VIS I fnands */
2553	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
2554	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2555	e9ebed4d	blueswir1	gen_op_fnands();
2556	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2557	e9ebed4d	blueswir1	break;
2558	e9ebed4d	blueswir1	case 0x070: /* VIS I fand */
2559	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2560	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2561	e9ebed4d	blueswir1	gen_op_fand();
2562	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2563	e9ebed4d	blueswir1	break;
2564	e9ebed4d	blueswir1	case 0x071: /* VIS I fands */
2565	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
2566	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2567	e9ebed4d	blueswir1	gen_op_fands();
2568	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2569	e9ebed4d	blueswir1	break;
2570	e9ebed4d	blueswir1	case 0x072: /* VIS I fxnor */
2571	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2572	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2573	e9ebed4d	blueswir1	gen_op_fxnor();
2574	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2575	e9ebed4d	blueswir1	break;
2576	e9ebed4d	blueswir1	case 0x073: /* VIS I fxnors */
2577	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
2578	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2579	e9ebed4d	blueswir1	gen_op_fxnors();
2580	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2581	e9ebed4d	blueswir1	break;
2582	3299908c	blueswir1	case 0x074: /* VIS I fsrc1 */
2583	3299908c	blueswir1	gen_op_load_fpr_DT0(rs1);
2584	3299908c	blueswir1	gen_op_store_DT0_fpr(rd);
2585	3299908c	blueswir1	break;
2586	3299908c	blueswir1	case 0x075: /* VIS I fsrc1s */
2587	3299908c	blueswir1	gen_op_load_fpr_FT0(rs1);
2588	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
2589	3299908c	blueswir1	break;
2590	e9ebed4d	blueswir1	case 0x076: /* VIS I fornot2 */
2591	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs1);
2592	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs2);
2593	e9ebed4d	blueswir1	gen_op_fornot();
2594	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2595	e9ebed4d	blueswir1	break;
2596	e9ebed4d	blueswir1	case 0x077: /* VIS I fornot2s */
2597	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs1);
2598	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs2);
2599	e9ebed4d	blueswir1	gen_op_fornots();
2600	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2601	e9ebed4d	blueswir1	break;
2602	3299908c	blueswir1	case 0x078: /* VIS I fsrc2 */
2603	3299908c	blueswir1	gen_op_load_fpr_DT0(rs2);
2604	3299908c	blueswir1	gen_op_store_DT0_fpr(rd);
2605	3299908c	blueswir1	break;
2606	3299908c	blueswir1	case 0x079: /* VIS I fsrc2s */
2607	3299908c	blueswir1	gen_op_load_fpr_FT0(rs2);
2608	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
2609	3299908c	blueswir1	break;
2610	e9ebed4d	blueswir1	case 0x07a: /* VIS I fornot1 */
2611	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2612	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2613	e9ebed4d	blueswir1	gen_op_fornot();
2614	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2615	e9ebed4d	blueswir1	break;
2616	e9ebed4d	blueswir1	case 0x07b: /* VIS I fornot1s */
2617	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
2618	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2619	e9ebed4d	blueswir1	gen_op_fornots();
2620	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2621	e9ebed4d	blueswir1	break;
2622	e9ebed4d	blueswir1	case 0x07c: /* VIS I for */
2623	e9ebed4d	blueswir1	gen_op_load_fpr_DT0(rs1);
2624	e9ebed4d	blueswir1	gen_op_load_fpr_DT1(rs2);
2625	e9ebed4d	blueswir1	gen_op_for();
2626	e9ebed4d	blueswir1	gen_op_store_DT0_fpr(rd);
2627	e9ebed4d	blueswir1	break;
2628	e9ebed4d	blueswir1	case 0x07d: /* VIS I fors */
2629	e9ebed4d	blueswir1	gen_op_load_fpr_FT0(rs1);
2630	e9ebed4d	blueswir1	gen_op_load_fpr_FT1(rs2);
2631	e9ebed4d	blueswir1	gen_op_fors();
2632	e9ebed4d	blueswir1	gen_op_store_FT0_fpr(rd);
2633	e9ebed4d	blueswir1	break;
2634	3299908c	blueswir1	case 0x07e: /* VIS I fone */
2635	3299908c	blueswir1	gen_op_movl_DT0_1();
2636	3299908c	blueswir1	gen_op_store_DT0_fpr(rd);
2637	3299908c	blueswir1	break;
2638	3299908c	blueswir1	case 0x07f: /* VIS I fones */
2639	3299908c	blueswir1	gen_op_movl_FT0_1();
2640	3299908c	blueswir1	gen_op_store_FT0_fpr(rd);
2641	3299908c	blueswir1	break;
2642	e9ebed4d	blueswir1	case 0x080: /* VIS I shutdown */
2643	e9ebed4d	blueswir1	case 0x081: /* VIS II siam */
2644	e9ebed4d	blueswir1	// XXX
2645	e9ebed4d	blueswir1	goto illegal_insn;
2646	3299908c	blueswir1	default:
2647	3299908c	blueswir1	goto illegal_insn;
2648	3299908c	blueswir1	}
2649	3299908c	blueswir1	#else
2650	3299908c	blueswir1	goto ncp_insn;
2651	3299908c	blueswir1	#endif
2652	3299908c	blueswir1	} else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
2653	fcc72045	blueswir1	#ifdef TARGET_SPARC64
2654	fcc72045	blueswir1	goto illegal_insn;
2655	fcc72045	blueswir1	#else
2656	fcc72045	blueswir1	goto ncp_insn;
2657	fcc72045	blueswir1	#endif
2658	3475187d	bellard	#ifdef TARGET_SPARC64
2659	3475187d	bellard	} else if (xop == 0x39) { /* V9 return */
2660	3475187d	bellard	rs1 = GET_FIELD(insn, 13, 17);
2661	1ad21e69	blueswir1	save_state(dc);
2662	3475187d	bellard	gen_movl_reg_T0(rs1);
2663	3475187d	bellard	if (IS_IMM) { /* immediate */
2664	3475187d	bellard	rs2 = GET_FIELDs(insn, 19, 31);
2665	3475187d	bellard	#if defined(OPTIM)
2666	3475187d	bellard	if (rs2) {
2667	3475187d	bellard	#endif
2668	3475187d	bellard	gen_movl_simm_T1(rs2);
2669	3475187d	bellard	gen_op_add_T1_T0();
2670	3475187d	bellard	#if defined(OPTIM)
2671	3475187d	bellard	}
2672	3475187d	bellard	#endif
2673	3475187d	bellard	} else { /* register */
2674	3475187d	bellard	rs2 = GET_FIELD(insn, 27, 31);
2675	3475187d	bellard	#if defined(OPTIM)
2676	3475187d	bellard	if (rs2) {
2677	3475187d	bellard	#endif
2678	3475187d	bellard	gen_movl_reg_T1(rs2);
2679	3475187d	bellard	gen_op_add_T1_T0();
2680	3475187d	bellard	#if defined(OPTIM)
2681	3475187d	bellard	}
2682	3475187d	bellard	#endif
2683	3475187d	bellard	}
2684	83469015	bellard	gen_op_restore();
2685	3475187d	bellard	gen_mov_pc_npc(dc);
2686	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
2687	3475187d	bellard	gen_op_movl_npc_T0();
2688	3475187d	bellard	dc->npc = DYNAMIC_PC;
2689	3475187d	bellard	goto jmp_insn;
2690	3475187d	bellard	#endif
2691	e80cfcfc	bellard	} else {
2692	e80cfcfc	bellard	rs1 = GET_FIELD(insn, 13, 17);
2693	e80cfcfc	bellard	gen_movl_reg_T0(rs1);
2694	e80cfcfc	bellard	if (IS_IMM) { /* immediate */
2695	e80cfcfc	bellard	rs2 = GET_FIELDs(insn, 19, 31);
2696	e80cfcfc	bellard	#if defined(OPTIM)
2697	e80cfcfc	bellard	if (rs2) {
2698	e8af50a3	bellard	#endif
2699	3475187d	bellard	gen_movl_simm_T1(rs2);
2700	e80cfcfc	bellard	gen_op_add_T1_T0();
2701	e80cfcfc	bellard	#if defined(OPTIM)
2702	e80cfcfc	bellard	}
2703	e8af50a3	bellard	#endif
2704	e80cfcfc	bellard	} else { /* register */
2705	e80cfcfc	bellard	rs2 = GET_FIELD(insn, 27, 31);
2706	e80cfcfc	bellard	#if defined(OPTIM)
2707	e80cfcfc	bellard	if (rs2) {
2708	e80cfcfc	bellard	#endif
2709	e80cfcfc	bellard	gen_movl_reg_T1(rs2);
2710	e80cfcfc	bellard	gen_op_add_T1_T0();
2711	e80cfcfc	bellard	#if defined(OPTIM)
2712	e80cfcfc	bellard	}
2713	e8af50a3	bellard	#endif
2714	cf495bcf	bellard	}
2715	e80cfcfc	bellard	switch (xop) {
2716	e80cfcfc	bellard	case 0x38: /* jmpl */
2717	e80cfcfc	bellard	{
2718	e80cfcfc	bellard	if (rd != 0) {
2719	ded3ab80	pbrook	#ifdef TARGET_SPARC64
2720	ded3ab80	pbrook	if (dc->pc == (uint32_t)dc->pc) {
2721	ded3ab80	pbrook	gen_op_movl_T1_im(dc->pc);
2722	ded3ab80	pbrook	} else {
2723	ded3ab80	pbrook	gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
2724	ded3ab80	pbrook	}
2725	ded3ab80	pbrook	#else
2726	0bee699e	bellard	gen_op_movl_T1_im(dc->pc);
2727	ded3ab80	pbrook	#endif
2728	0bee699e	bellard	gen_movl_T1_reg(rd);
2729	e80cfcfc	bellard	}
2730	0bee699e	bellard	gen_mov_pc_npc(dc);
2731	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
2732	0bee699e	bellard	gen_op_movl_npc_T0();
2733	e80cfcfc	bellard	dc->npc = DYNAMIC_PC;
2734	e80cfcfc	bellard	}
2735	e80cfcfc	bellard	goto jmp_insn;
2736	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
2737	af7bf89b	bellard	case 0x39: /* rett, V9 return */
2738	e80cfcfc	bellard	{
2739	e80cfcfc	bellard	if (!supervisor(dc))
2740	e80cfcfc	bellard	goto priv_insn;
2741	0bee699e	bellard	gen_mov_pc_npc(dc);
2742	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
2743	e80cfcfc	bellard	gen_op_movl_npc_T0();
2744	0bee699e	bellard	dc->npc = DYNAMIC_PC;
2745	e80cfcfc	bellard	gen_op_rett();
2746	e80cfcfc	bellard	}
2747	0bee699e	bellard	goto jmp_insn;
2748	e80cfcfc	bellard	#endif
2749	e80cfcfc	bellard	case 0x3b: /* flush */
2750	e80cfcfc	bellard	gen_op_flush_T0();
2751	e80cfcfc	bellard	break;
2752	e80cfcfc	bellard	case 0x3c: /* save */
2753	e80cfcfc	bellard	save_state(dc);
2754	e80cfcfc	bellard	gen_op_save();
2755	e80cfcfc	bellard	gen_movl_T0_reg(rd);
2756	e80cfcfc	bellard	break;
2757	e80cfcfc	bellard	case 0x3d: /* restore */
2758	e80cfcfc	bellard	save_state(dc);
2759	e80cfcfc	bellard	gen_op_restore();
2760	e80cfcfc	bellard	gen_movl_T0_reg(rd);
2761	e80cfcfc	bellard	break;
2762	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
2763	af7bf89b	bellard	case 0x3e: /* V9 done/retry */
2764	3475187d	bellard	{
2765	3475187d	bellard	switch (rd) {
2766	3475187d	bellard	case 0:
2767	3475187d	bellard	if (!supervisor(dc))
2768	3475187d	bellard	goto priv_insn;
2769	83469015	bellard	dc->npc = DYNAMIC_PC;
2770	83469015	bellard	dc->pc = DYNAMIC_PC;
2771	3475187d	bellard	gen_op_done();
2772	83469015	bellard	goto jmp_insn;
2773	3475187d	bellard	case 1:
2774	3475187d	bellard	if (!supervisor(dc))
2775	3475187d	bellard	goto priv_insn;
2776	83469015	bellard	dc->npc = DYNAMIC_PC;
2777	83469015	bellard	dc->pc = DYNAMIC_PC;
2778	3475187d	bellard	gen_op_retry();
2779	83469015	bellard	goto jmp_insn;
2780	3475187d	bellard	default:
2781	3475187d	bellard	goto illegal_insn;
2782	3475187d	bellard	}
2783	3475187d	bellard	}
2784	3475187d	bellard	break;
2785	3475187d	bellard	#endif
2786	3475187d	bellard	default:
2787	e80cfcfc	bellard	goto illegal_insn;
2788	e80cfcfc	bellard	}
2789	cf495bcf	bellard	}
2790	cf495bcf	bellard	break;
2791	cf495bcf	bellard	}
2792	af7bf89b	bellard	break;
2793	cf495bcf	bellard	case 3: /* load/store instructions */
2794	cf495bcf	bellard	{
2795	cf495bcf	bellard	unsigned int xop = GET_FIELD(insn, 7, 12);
2796	cf495bcf	bellard	rs1 = GET_FIELD(insn, 13, 17);
2797	2371aaa2	blueswir1	save_state(dc);
2798	cf495bcf	bellard	gen_movl_reg_T0(rs1);
2799	cf495bcf	bellard	if (IS_IMM) { /* immediate */
2800	cf495bcf	bellard	rs2 = GET_FIELDs(insn, 19, 31);
2801	e80cfcfc	bellard	#if defined(OPTIM)
2802	e8af50a3	bellard	if (rs2 != 0) {
2803	e80cfcfc	bellard	#endif
2804	3475187d	bellard	gen_movl_simm_T1(rs2);
2805	e8af50a3	bellard	gen_op_add_T1_T0();
2806	e80cfcfc	bellard	#if defined(OPTIM)
2807	e8af50a3	bellard	}
2808	e80cfcfc	bellard	#endif
2809	cf495bcf	bellard	} else { /* register */
2810	cf495bcf	bellard	rs2 = GET_FIELD(insn, 27, 31);
2811	e80cfcfc	bellard	#if defined(OPTIM)
2812	e80cfcfc	bellard	if (rs2 != 0) {
2813	e80cfcfc	bellard	#endif
2814	e80cfcfc	bellard	gen_movl_reg_T1(rs2);
2815	e80cfcfc	bellard	gen_op_add_T1_T0();
2816	e80cfcfc	bellard	#if defined(OPTIM)
2817	e80cfcfc	bellard	}
2818	e80cfcfc	bellard	#endif
2819	cf495bcf	bellard	}
2820	2f2ecb83	blueswir1	if (xop < 4 \|\| (xop > 7 && xop < 0x14 && xop != 0x0e) \|\|
2821	2f2ecb83	blueswir1	(xop > 0x17 && xop <= 0x1d ) \|\|
2822	2f2ecb83	blueswir1	(xop > 0x2c && xop <= 0x33) \|\| xop == 0x1f \|\| xop == 0x3d) {
2823	cf495bcf	bellard	switch (xop) {
2824	cf495bcf	bellard	case 0x0: /* load word */
2825	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
2826	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
2827	6ea4a6c8	blueswir1	#endif
2828	dc011987	blueswir1	#ifndef TARGET_SPARC64
2829	e8af50a3	bellard	gen_op_ldst(ld);
2830	dc011987	blueswir1	#else
2831	dc011987	blueswir1	gen_op_ldst(lduw);
2832	dc011987	blueswir1	#endif
2833	cf495bcf	bellard	break;
2834	cf495bcf	bellard	case 0x1: /* load unsigned byte */
2835	e8af50a3	bellard	gen_op_ldst(ldub);
2836	cf495bcf	bellard	break;
2837	cf495bcf	bellard	case 0x2: /* load unsigned halfword */
2838	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
2839	6ea4a6c8	blueswir1	gen_op_check_align_T0_1();
2840	6ea4a6c8	blueswir1	#endif
2841	e8af50a3	bellard	gen_op_ldst(lduh);
2842	cf495bcf	bellard	break;
2843	cf495bcf	bellard	case 0x3: /* load double word */
2844	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
2845	d4218d99	blueswir1	if (rd & 1)
2846	d4218d99	blueswir1	goto illegal_insn;
2847	e8af50a3	bellard	gen_op_ldst(ldd);
2848	cf495bcf	bellard	gen_movl_T0_reg(rd + 1);
2849	cf495bcf	bellard	break;
2850	cf495bcf	bellard	case 0x9: /* load signed byte */
2851	e8af50a3	bellard	gen_op_ldst(ldsb);
2852	cf495bcf	bellard	break;
2853	cf495bcf	bellard	case 0xa: /* load signed halfword */
2854	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
2855	6ea4a6c8	blueswir1	gen_op_check_align_T0_1();
2856	6ea4a6c8	blueswir1	#endif
2857	e8af50a3	bellard	gen_op_ldst(ldsh);
2858	cf495bcf	bellard	break;
2859	cf495bcf	bellard	case 0xd: /* ldstub -- XXX: should be atomically */
2860	e8af50a3	bellard	gen_op_ldst(ldstub);
2861	cf495bcf	bellard	break;
2862	cf495bcf	bellard	case 0x0f: /* swap register with memory. Also atomically */
2863	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
2864	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
2865	6ea4a6c8	blueswir1	#endif
2866	e80cfcfc	bellard	gen_movl_reg_T1(rd);
2867	e8af50a3	bellard	gen_op_ldst(swap);
2868	e8af50a3	bellard	break;
2869	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
2870	e8af50a3	bellard	case 0x10: /* load word alternate */
2871	3475187d	bellard	#ifndef TARGET_SPARC64
2872	d4218d99	blueswir1	if (IS_IMM)
2873	d4218d99	blueswir1	goto illegal_insn;
2874	e8af50a3	bellard	if (!supervisor(dc))
2875	e8af50a3	bellard	goto priv_insn;
2876	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
2877	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
2878	6ea4a6c8	blueswir1	#endif
2879	e8af50a3	bellard	gen_op_lda(insn, 1, 4, 0);
2880	dc011987	blueswir1	#else
2881	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
2882	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
2883	6ea4a6c8	blueswir1	#endif
2884	dc011987	blueswir1	gen_op_lduwa(insn, 1, 4, 0);
2885	dc011987	blueswir1	#endif
2886	e8af50a3	bellard	break;
2887	e8af50a3	bellard	case 0x11: /* load unsigned byte alternate */
2888	3475187d	bellard	#ifndef TARGET_SPARC64
2889	d4218d99	blueswir1	if (IS_IMM)
2890	d4218d99	blueswir1	goto illegal_insn;
2891	e8af50a3	bellard	if (!supervisor(dc))
2892	e8af50a3	bellard	goto priv_insn;
2893	3475187d	bellard	#endif
2894	e8af50a3	bellard	gen_op_lduba(insn, 1, 1, 0);
2895	e8af50a3	bellard	break;
2896	e8af50a3	bellard	case 0x12: /* load unsigned halfword alternate */
2897	3475187d	bellard	#ifndef TARGET_SPARC64
2898	d4218d99	blueswir1	if (IS_IMM)
2899	d4218d99	blueswir1	goto illegal_insn;
2900	e8af50a3	bellard	if (!supervisor(dc))
2901	e8af50a3	bellard	goto priv_insn;
2902	3475187d	bellard	#endif
2903	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
2904	6ea4a6c8	blueswir1	gen_op_check_align_T0_1();
2905	6ea4a6c8	blueswir1	#endif
2906	e8af50a3	bellard	gen_op_lduha(insn, 1, 2, 0);
2907	e8af50a3	bellard	break;
2908	e8af50a3	bellard	case 0x13: /* load double word alternate */
2909	3475187d	bellard	#ifndef TARGET_SPARC64
2910	d4218d99	blueswir1	if (IS_IMM)
2911	d4218d99	blueswir1	goto illegal_insn;
2912	e8af50a3	bellard	if (!supervisor(dc))
2913	e8af50a3	bellard	goto priv_insn;
2914	3475187d	bellard	#endif
2915	d4218d99	blueswir1	if (rd & 1)
2916	d4218d99	blueswir1	goto illegal_insn;
2917	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
2918	e8af50a3	bellard	gen_op_ldda(insn, 1, 8, 0);
2919	e8af50a3	bellard	gen_movl_T0_reg(rd + 1);
2920	e8af50a3	bellard	break;
2921	e8af50a3	bellard	case 0x19: /* load signed byte alternate */
2922	3475187d	bellard	#ifndef TARGET_SPARC64
2923	d4218d99	blueswir1	if (IS_IMM)
2924	d4218d99	blueswir1	goto illegal_insn;
2925	e8af50a3	bellard	if (!supervisor(dc))
2926	e8af50a3	bellard	goto priv_insn;
2927	3475187d	bellard	#endif
2928	e8af50a3	bellard	gen_op_ldsba(insn, 1, 1, 1);
2929	e8af50a3	bellard	break;
2930	e8af50a3	bellard	case 0x1a: /* load signed halfword alternate */
2931	3475187d	bellard	#ifndef TARGET_SPARC64
2932	d4218d99	blueswir1	if (IS_IMM)
2933	d4218d99	blueswir1	goto illegal_insn;
2934	e8af50a3	bellard	if (!supervisor(dc))
2935	e8af50a3	bellard	goto priv_insn;
2936	3475187d	bellard	#endif
2937	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
2938	6ea4a6c8	blueswir1	gen_op_check_align_T0_1();
2939	6ea4a6c8	blueswir1	#endif
2940	e8af50a3	bellard	gen_op_ldsha(insn, 1, 2 ,1);
2941	e8af50a3	bellard	break;
2942	e8af50a3	bellard	case 0x1d: /* ldstuba -- XXX: should be atomically */
2943	3475187d	bellard	#ifndef TARGET_SPARC64
2944	d4218d99	blueswir1	if (IS_IMM)
2945	d4218d99	blueswir1	goto illegal_insn;
2946	e8af50a3	bellard	if (!supervisor(dc))
2947	e8af50a3	bellard	goto priv_insn;
2948	3475187d	bellard	#endif
2949	e8af50a3	bellard	gen_op_ldstuba(insn, 1, 1, 0);
2950	e8af50a3	bellard	break;
2951	e8af50a3	bellard	case 0x1f: /* swap reg with alt. memory. Also atomically */
2952	3475187d	bellard	#ifndef TARGET_SPARC64
2953	d4218d99	blueswir1	if (IS_IMM)
2954	d4218d99	blueswir1	goto illegal_insn;
2955	e8af50a3	bellard	if (!supervisor(dc))
2956	e8af50a3	bellard	goto priv_insn;
2957	3475187d	bellard	#endif
2958	e80cfcfc	bellard	gen_movl_reg_T1(rd);
2959	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
2960	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
2961	6ea4a6c8	blueswir1	#endif
2962	e8af50a3	bellard	gen_op_swapa(insn, 1, 4, 0);
2963	cf495bcf	bellard	break;
2964	3475187d	bellard
2965	3475187d	bellard	#ifndef TARGET_SPARC64
2966	fcc72045	blueswir1	case 0x30: /* ldc */
2967	fcc72045	blueswir1	case 0x31: /* ldcsr */
2968	fcc72045	blueswir1	case 0x33: /* lddc */
2969	fcc72045	blueswir1	goto ncp_insn;
2970	0fa85d43	bellard	/* avoid warnings */
2971	0fa85d43	bellard	(void) &gen_op_stfa;
2972	0fa85d43	bellard	(void) &gen_op_stdfa;
2973	0fa85d43	bellard	(void) &gen_op_ldfa;
2974	0fa85d43	bellard	(void) &gen_op_lddfa;
2975	3475187d	bellard	#else
2976	dc011987	blueswir1	(void) &gen_op_lda;
2977	3475187d	bellard	#if !defined(CONFIG_USER_ONLY)
2978	3475187d	bellard	(void) &gen_op_cas;
2979	3475187d	bellard	(void) &gen_op_casx;
2980	e80cfcfc	bellard	#endif
2981	3475187d	bellard	#endif
2982	3475187d	bellard	#endif
2983	3475187d	bellard	#ifdef TARGET_SPARC64
2984	af7bf89b	bellard	case 0x08: /* V9 ldsw */
2985	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
2986	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
2987	6ea4a6c8	blueswir1	#endif
2988	3475187d	bellard	gen_op_ldst(ldsw);
2989	3475187d	bellard	break;
2990	af7bf89b	bellard	case 0x0b: /* V9 ldx */
2991	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
2992	3475187d	bellard	gen_op_ldst(ldx);
2993	3475187d	bellard	break;
2994	af7bf89b	bellard	case 0x18: /* V9 ldswa */
2995	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
2996	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
2997	6ea4a6c8	blueswir1	#endif
2998	3475187d	bellard	gen_op_ldswa(insn, 1, 4, 1);
2999	3475187d	bellard	break;
3000	af7bf89b	bellard	case 0x1b: /* V9 ldxa */
3001	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
3002	3475187d	bellard	gen_op_ldxa(insn, 1, 8, 0);
3003	3475187d	bellard	break;
3004	3475187d	bellard	case 0x2d: /* V9 prefetch, no effect */
3005	3475187d	bellard	goto skip_move;
3006	af7bf89b	bellard	case 0x30: /* V9 ldfa */
3007	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
3008	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
3009	6ea4a6c8	blueswir1	#endif
3010	3475187d	bellard	gen_op_ldfa(insn, 1, 8, 0); // XXX
3011	3475187d	bellard	break;
3012	af7bf89b	bellard	case 0x33: /* V9 lddfa */
3013	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
3014	3475187d	bellard	gen_op_lddfa(insn, 1, 8, 0); // XXX
3015	af7bf89b	bellard
3016	3475187d	bellard	break;
3017	3475187d	bellard	case 0x3d: /* V9 prefetcha, no effect */
3018	3475187d	bellard	goto skip_move;
3019	af7bf89b	bellard	case 0x32: /* V9 ldqfa */
3020	3475187d	bellard	goto nfpu_insn;
3021	3475187d	bellard	#endif
3022	3475187d	bellard	default:
3023	e80cfcfc	bellard	goto illegal_insn;
3024	7a3f1944	bellard	}
3025	cf495bcf	bellard	gen_movl_T1_reg(rd);
3026	3475187d	bellard	#ifdef TARGET_SPARC64
3027	3475187d	bellard	skip_move: ;
3028	3475187d	bellard	#endif
3029	e8af50a3	bellard	} else if (xop >= 0x20 && xop < 0x24) {
3030	a80dde08	bellard	if (gen_trap_ifnofpu(dc))
3031	a80dde08	bellard	goto jmp_insn;
3032	e8af50a3	bellard	switch (xop) {
3033	e8af50a3	bellard	case 0x20: /* load fpreg */
3034	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
3035	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
3036	6ea4a6c8	blueswir1	#endif
3037	e8af50a3	bellard	gen_op_ldst(ldf);
3038	e8af50a3	bellard	gen_op_store_FT0_fpr(rd);
3039	e8af50a3	bellard	break;
3040	e8af50a3	bellard	case 0x21: /* load fsr */
3041	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
3042	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
3043	6ea4a6c8	blueswir1	#endif
3044	9e61bde5	bellard	gen_op_ldst(ldf);
3045	e8af50a3	bellard	gen_op_ldfsr();
3046	e8af50a3	bellard	break;
3047	af7bf89b	bellard	case 0x22: /* load quad fpreg */
3048	af7bf89b	bellard	goto nfpu_insn;
3049	e8af50a3	bellard	case 0x23: /* load double fpreg */
3050	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
3051	e8af50a3	bellard	gen_op_ldst(lddf);
3052	3475187d	bellard	gen_op_store_DT0_fpr(DFPREG(rd));
3053	e8af50a3	bellard	break;
3054	e80cfcfc	bellard	default:
3055	e80cfcfc	bellard	goto illegal_insn;
3056	e8af50a3	bellard	}
3057	3475187d	bellard	} else if (xop < 8 \|\| (xop >= 0x14 && xop < 0x18) \|\| \
3058	3475187d	bellard	xop == 0xe \|\| xop == 0x1e) {
3059	cf495bcf	bellard	gen_movl_reg_T1(rd);
3060	cf495bcf	bellard	switch (xop) {
3061	cf495bcf	bellard	case 0x4:
3062	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
3063	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
3064	6ea4a6c8	blueswir1	#endif
3065	e8af50a3	bellard	gen_op_ldst(st);
3066	cf495bcf	bellard	break;
3067	cf495bcf	bellard	case 0x5:
3068	e8af50a3	bellard	gen_op_ldst(stb);
3069	cf495bcf	bellard	break;
3070	cf495bcf	bellard	case 0x6:
3071	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
3072	6ea4a6c8	blueswir1	gen_op_check_align_T0_1();
3073	6ea4a6c8	blueswir1	#endif
3074	e8af50a3	bellard	gen_op_ldst(sth);
3075	cf495bcf	bellard	break;
3076	cf495bcf	bellard	case 0x7:
3077	d4218d99	blueswir1	if (rd & 1)
3078	d4218d99	blueswir1	goto illegal_insn;
3079	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
3080	72cbca10	bellard	flush_T2(dc);
3081	cf495bcf	bellard	gen_movl_reg_T2(rd + 1);
3082	e8af50a3	bellard	gen_op_ldst(std);
3083	e8af50a3	bellard	break;
3084	3475187d	bellard	#if !defined(CONFIG_USER_ONLY) \|\| defined(TARGET_SPARC64)
3085	e8af50a3	bellard	case 0x14:
3086	3475187d	bellard	#ifndef TARGET_SPARC64
3087	d4218d99	blueswir1	if (IS_IMM)
3088	d4218d99	blueswir1	goto illegal_insn;
3089	e8af50a3	bellard	if (!supervisor(dc))
3090	e8af50a3	bellard	goto priv_insn;
3091	3475187d	bellard	#endif
3092	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
3093	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
3094	6ea4a6c8	blueswir1	#endif
3095	e8af50a3	bellard	gen_op_sta(insn, 0, 4, 0);
3096	d39c0b99	bellard	break;
3097	e8af50a3	bellard	case 0x15:
3098	3475187d	bellard	#ifndef TARGET_SPARC64
3099	d4218d99	blueswir1	if (IS_IMM)
3100	d4218d99	blueswir1	goto illegal_insn;
3101	e8af50a3	bellard	if (!supervisor(dc))
3102	e8af50a3	bellard	goto priv_insn;
3103	3475187d	bellard	#endif
3104	e8af50a3	bellard	gen_op_stba(insn, 0, 1, 0);
3105	d39c0b99	bellard	break;
3106	e8af50a3	bellard	case 0x16:
3107	3475187d	bellard	#ifndef TARGET_SPARC64
3108	d4218d99	blueswir1	if (IS_IMM)
3109	d4218d99	blueswir1	goto illegal_insn;
3110	e8af50a3	bellard	if (!supervisor(dc))
3111	e8af50a3	bellard	goto priv_insn;
3112	3475187d	bellard	#endif
3113	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
3114	6ea4a6c8	blueswir1	gen_op_check_align_T0_1();
3115	6ea4a6c8	blueswir1	#endif
3116	e8af50a3	bellard	gen_op_stha(insn, 0, 2, 0);
3117	d39c0b99	bellard	break;
3118	e8af50a3	bellard	case 0x17:
3119	3475187d	bellard	#ifndef TARGET_SPARC64
3120	d4218d99	blueswir1	if (IS_IMM)
3121	d4218d99	blueswir1	goto illegal_insn;
3122	e8af50a3	bellard	if (!supervisor(dc))
3123	e8af50a3	bellard	goto priv_insn;
3124	3475187d	bellard	#endif
3125	d4218d99	blueswir1	if (rd & 1)
3126	d4218d99	blueswir1	goto illegal_insn;
3127	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
3128	e8af50a3	bellard	flush_T2(dc);
3129	e8af50a3	bellard	gen_movl_reg_T2(rd + 1);
3130	e8af50a3	bellard	gen_op_stda(insn, 0, 8, 0);
3131	d39c0b99	bellard	break;
3132	e80cfcfc	bellard	#endif
3133	3475187d	bellard	#ifdef TARGET_SPARC64
3134	af7bf89b	bellard	case 0x0e: /* V9 stx */
3135	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
3136	3475187d	bellard	gen_op_ldst(stx);
3137	3475187d	bellard	break;
3138	af7bf89b	bellard	case 0x1e: /* V9 stxa */
3139	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
3140	3475187d	bellard	gen_op_stxa(insn, 0, 8, 0); // XXX
3141	3475187d	bellard	break;
3142	3475187d	bellard	#endif
3143	3475187d	bellard	default:
3144	e80cfcfc	bellard	goto illegal_insn;
3145	7a3f1944	bellard	}
3146	e8af50a3	bellard	} else if (xop > 0x23 && xop < 0x28) {
3147	a80dde08	bellard	if (gen_trap_ifnofpu(dc))
3148	a80dde08	bellard	goto jmp_insn;
3149	e8af50a3	bellard	switch (xop) {
3150	e8af50a3	bellard	case 0x24:
3151	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
3152	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
3153	6ea4a6c8	blueswir1	#endif
3154	e8af50a3	bellard	gen_op_load_fpr_FT0(rd);
3155	e8af50a3	bellard	gen_op_ldst(stf);
3156	e8af50a3	bellard	break;
3157	af7bf89b	bellard	case 0x25: /* stfsr, V9 stxfsr */
3158	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
3159	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
3160	6ea4a6c8	blueswir1	#endif
3161	e8af50a3	bellard	gen_op_stfsr();
3162	9e61bde5	bellard	gen_op_ldst(stf);
3163	e8af50a3	bellard	break;
3164	9143e598	blueswir1	#if !defined(CONFIG_USER_ONLY)
3165	af7bf89b	bellard	case 0x26: /* stdfq */
3166	9143e598	blueswir1	if (!supervisor(dc))
3167	9143e598	blueswir1	goto priv_insn;
3168	9143e598	blueswir1	if (gen_trap_ifnofpu(dc))
3169	9143e598	blueswir1	goto jmp_insn;
3170	9143e598	blueswir1	goto nfq_insn;
3171	9143e598	blueswir1	#endif
3172	e8af50a3	bellard	case 0x27:
3173	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
3174	3475187d	bellard	gen_op_load_fpr_DT0(DFPREG(rd));
3175	e8af50a3	bellard	gen_op_ldst(stdf);
3176	e8af50a3	bellard	break;
3177	e80cfcfc	bellard	default:
3178	3475187d	bellard	goto illegal_insn;
3179	3475187d	bellard	}
3180	3475187d	bellard	} else if (xop > 0x33 && xop < 0x3f) {
3181	3475187d	bellard	switch (xop) {
3182	a4d17f19	blueswir1	#ifdef TARGET_SPARC64
3183	af7bf89b	bellard	case 0x34: /* V9 stfa */
3184	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
3185	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
3186	6ea4a6c8	blueswir1	#endif
3187	3475187d	bellard	gen_op_stfa(insn, 0, 0, 0); // XXX
3188	3475187d	bellard	break;
3189	af7bf89b	bellard	case 0x37: /* V9 stdfa */
3190	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
3191	3475187d	bellard	gen_op_stdfa(insn, 0, 0, 0); // XXX
3192	3475187d	bellard	break;
3193	af7bf89b	bellard	case 0x3c: /* V9 casa */
3194	6ea4a6c8	blueswir1	#ifdef CONFIG_USER_ONLY
3195	6ea4a6c8	blueswir1	gen_op_check_align_T0_3();
3196	6ea4a6c8	blueswir1	#endif
3197	3475187d	bellard	gen_op_casa(insn, 0, 4, 0); // XXX
3198	3475187d	bellard	break;
3199	af7bf89b	bellard	case 0x3e: /* V9 casxa */
3200	6ea4a6c8	blueswir1	gen_op_check_align_T0_7();
3201	3475187d	bellard	gen_op_casxa(insn, 0, 8, 0); // XXX
3202	3475187d	bellard	break;
3203	af7bf89b	bellard	case 0x36: /* V9 stqfa */
3204	3475187d	bellard	goto nfpu_insn;
3205	a4d17f19	blueswir1	#else
3206	a4d17f19	blueswir1	case 0x34: /* stc */
3207	a4d17f19	blueswir1	case 0x35: /* stcsr */
3208	a4d17f19	blueswir1	case 0x36: /* stdcq */
3209	a4d17f19	blueswir1	case 0x37: /* stdc */
3210	a4d17f19	blueswir1	goto ncp_insn;
3211	a4d17f19	blueswir1	#endif
3212	3475187d	bellard	default:
3213	e80cfcfc	bellard	goto illegal_insn;
3214	e8af50a3	bellard	}
3215	e8af50a3	bellard	}
3216	e80cfcfc	bellard	else
3217	e80cfcfc	bellard	goto illegal_insn;
3218	7a3f1944	bellard	}
3219	af7bf89b	bellard	break;
3220	cf495bcf	bellard	}
3221	cf495bcf	bellard	/* default case for non jump instructions */
3222	72cbca10	bellard	if (dc->npc == DYNAMIC_PC) {
3223	72cbca10	bellard	dc->pc = DYNAMIC_PC;
3224	72cbca10	bellard	gen_op_next_insn();
3225	72cbca10	bellard	} else if (dc->npc == JUMP_PC) {
3226	72cbca10	bellard	/* we can do a static jump */
3227	46525e1f	blueswir1	gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
3228	72cbca10	bellard	dc->is_br = 1;
3229	72cbca10	bellard	} else {
3230	cf495bcf	bellard	dc->pc = dc->npc;
3231	cf495bcf	bellard	dc->npc = dc->npc + 4;
3232	cf495bcf	bellard	}
3233	e80cfcfc	bellard	jmp_insn:
3234	cf495bcf	bellard	return;
3235	cf495bcf	bellard	illegal_insn:
3236	72cbca10	bellard	save_state(dc);
3237	cf495bcf	bellard	gen_op_exception(TT_ILL_INSN);
3238	cf495bcf	bellard	dc->is_br = 1;
3239	e8af50a3	bellard	return;
3240	e80cfcfc	bellard	#if !defined(CONFIG_USER_ONLY)
3241	e8af50a3	bellard	priv_insn:
3242	e8af50a3	bellard	save_state(dc);
3243	e8af50a3	bellard	gen_op_exception(TT_PRIV_INSN);
3244	e8af50a3	bellard	dc->is_br = 1;
3245	e80cfcfc	bellard	return;
3246	e80cfcfc	bellard	#endif
3247	e80cfcfc	bellard	nfpu_insn:
3248	e80cfcfc	bellard	save_state(dc);
3249	e80cfcfc	bellard	gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
3250	e80cfcfc	bellard	dc->is_br = 1;
3251	fcc72045	blueswir1	return;
3252	9143e598	blueswir1	#if !defined(CONFIG_USER_ONLY)
3253	9143e598	blueswir1	nfq_insn:
3254	9143e598	blueswir1	save_state(dc);
3255	9143e598	blueswir1	gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
3256	9143e598	blueswir1	dc->is_br = 1;
3257	9143e598	blueswir1	return;
3258	9143e598	blueswir1	#endif
3259	fcc72045	blueswir1	#ifndef TARGET_SPARC64
3260	fcc72045	blueswir1	ncp_insn:
3261	fcc72045	blueswir1	save_state(dc);
3262	fcc72045	blueswir1	gen_op_exception(TT_NCP_INSN);
3263	fcc72045	blueswir1	dc->is_br = 1;
3264	fcc72045	blueswir1	return;
3265	fcc72045	blueswir1	#endif
3266	7a3f1944	bellard	}
3267	7a3f1944	bellard
3268	cf495bcf	bellard	static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3269	e8af50a3	bellard	int spc, CPUSPARCState *env)
3270	7a3f1944	bellard	{
3271	72cbca10	bellard	target_ulong pc_start, last_pc;
3272	cf495bcf	bellard	uint16_t *gen_opc_end;
3273	cf495bcf	bellard	DisasContext dc1, *dc = &dc1;
3274	e8af50a3	bellard	int j, lj = -1;
3275	cf495bcf	bellard
3276	cf495bcf	bellard	memset(dc, 0, sizeof(DisasContext));
3277	cf495bcf	bellard	dc->tb = tb;
3278	72cbca10	bellard	pc_start = tb->pc;
3279	cf495bcf	bellard	dc->pc = pc_start;
3280	e80cfcfc	bellard	last_pc = dc->pc;
3281	72cbca10	bellard	dc->npc = (target_ulong) tb->cs_base;
3282	e8af50a3	bellard	#if defined(CONFIG_USER_ONLY)
3283	e8af50a3	bellard	dc->mem_idx = 0;
3284	a80dde08	bellard	dc->fpu_enabled = 1;
3285	e8af50a3	bellard	#else
3286	e8af50a3	bellard	dc->mem_idx = ((env->psrs) != 0);
3287	a80dde08	bellard	#ifdef TARGET_SPARC64
3288	a80dde08	bellard	dc->fpu_enabled = (((env->pstate & PS_PEF) != 0) && ((env->fprs & FPRS_FEF) != 0));
3289	a80dde08	bellard	#else
3290	a80dde08	bellard	dc->fpu_enabled = ((env->psref) != 0);
3291	a80dde08	bellard	#endif
3292	e8af50a3	bellard	#endif
3293	cf495bcf	bellard	gen_opc_ptr = gen_opc_buf;
3294	cf495bcf	bellard	gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3295	cf495bcf	bellard	gen_opparam_ptr = gen_opparam_buf;
3296	83469015	bellard	nb_gen_labels = 0;
3297	cf495bcf	bellard
3298	cf495bcf	bellard	do {
3299	e8af50a3	bellard	if (env->nb_breakpoints > 0) {
3300	e8af50a3	bellard	for(j = 0; j < env->nb_breakpoints; j++) {
3301	e8af50a3	bellard	if (env->breakpoints[j] == dc->pc) {
3302	e80cfcfc	bellard	if (dc->pc != pc_start)
3303	e80cfcfc	bellard	save_state(dc);
3304	e80cfcfc	bellard	gen_op_debug();
3305	e80cfcfc	bellard	gen_op_movl_T0_0();
3306	e80cfcfc	bellard	gen_op_exit_tb();
3307	e80cfcfc	bellard	dc->is_br = 1;
3308	e80cfcfc	bellard	goto exit_gen_loop;
3309	e8af50a3	bellard	}
3310	e8af50a3	bellard	}
3311	e8af50a3	bellard	}
3312	e8af50a3	bellard	if (spc) {
3313	e8af50a3	bellard	if (loglevel > 0)
3314	e8af50a3	bellard	fprintf(logfile, "Search PC...\n");
3315	e8af50a3	bellard	j = gen_opc_ptr - gen_opc_buf;
3316	e8af50a3	bellard	if (lj < j) {
3317	e8af50a3	bellard	lj++;
3318	e8af50a3	bellard	while (lj < j)
3319	e8af50a3	bellard	gen_opc_instr_start[lj++] = 0;
3320	e8af50a3	bellard	gen_opc_pc[lj] = dc->pc;
3321	e8af50a3	bellard	gen_opc_npc[lj] = dc->npc;
3322	e8af50a3	bellard	gen_opc_instr_start[lj] = 1;
3323	e8af50a3	bellard	}
3324	e8af50a3	bellard	}
3325	cf495bcf	bellard	last_pc = dc->pc;
3326	cf495bcf	bellard	disas_sparc_insn(dc);
3327	3475187d	bellard
3328	cf495bcf	bellard	if (dc->is_br)
3329	cf495bcf	bellard	break;
3330	cf495bcf	bellard	/* if the next PC is different, we abort now */
3331	cf495bcf	bellard	if (dc->pc != (last_pc + 4))
3332	cf495bcf	bellard	break;
3333	d39c0b99	bellard	/* if we reach a page boundary, we stop generation so that the
3334	d39c0b99	bellard	PC of a TT_TFAULT exception is always in the right page */
3335	d39c0b99	bellard	if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
3336	d39c0b99	bellard	break;
3337	e80cfcfc	bellard	/* if single step mode, we generate only one instruction and
3338	e80cfcfc	bellard	generate an exception */
3339	e80cfcfc	bellard	if (env->singlestep_enabled) {
3340	3475187d	bellard	gen_jmp_im(dc->pc);
3341	e80cfcfc	bellard	gen_op_movl_T0_0();
3342	e80cfcfc	bellard	gen_op_exit_tb();
3343	e80cfcfc	bellard	break;
3344	e80cfcfc	bellard	}
3345	cf495bcf	bellard	} while ((gen_opc_ptr < gen_opc_end) &&
3346	cf495bcf	bellard	(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
3347	e80cfcfc	bellard
3348	e80cfcfc	bellard	exit_gen_loop:
3349	72cbca10	bellard	if (!dc->is_br) {
3350	72cbca10	bellard	if (dc->pc != DYNAMIC_PC &&
3351	72cbca10	bellard	(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
3352	72cbca10	bellard	/* static PC and NPC: we can use direct chaining */
3353	46525e1f	blueswir1	gen_branch(dc, dc->pc, dc->npc);
3354	72cbca10	bellard	} else {
3355	72cbca10	bellard	if (dc->pc != DYNAMIC_PC)
3356	3475187d	bellard	gen_jmp_im(dc->pc);
3357	72cbca10	bellard	save_npc(dc);
3358	72cbca10	bellard	gen_op_movl_T0_0();
3359	72cbca10	bellard	gen_op_exit_tb();
3360	72cbca10	bellard	}
3361	72cbca10	bellard	}
3362	cf495bcf	bellard	*gen_opc_ptr = INDEX_op_end;
3363	e8af50a3	bellard	if (spc) {
3364	e8af50a3	bellard	j = gen_opc_ptr - gen_opc_buf;
3365	e8af50a3	bellard	lj++;
3366	e8af50a3	bellard	while (lj <= j)
3367	e8af50a3	bellard	gen_opc_instr_start[lj++] = 0;
3368	e8af50a3	bellard	#if 0
3369	e8af50a3	bellard	if (loglevel > 0) {
3370	e8af50a3	bellard	page_dump(logfile);
3371	e8af50a3	bellard	}
3372	e8af50a3	bellard	#endif
3373	c3278b7b	bellard	gen_opc_jump_pc[0] = dc->jump_pc[0];
3374	c3278b7b	bellard	gen_opc_jump_pc[1] = dc->jump_pc[1];
3375	e8af50a3	bellard	} else {
3376	e80cfcfc	bellard	tb->size = last_pc + 4 - pc_start;
3377	e8af50a3	bellard	}
3378	7a3f1944	bellard	#ifdef DEBUG_DISAS
3379	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_IN_ASM) {
3380	cf495bcf	bellard	fprintf(logfile, "--------------\n");
3381	0fa85d43	bellard	fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3382	0fa85d43	bellard	target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
3383	cf495bcf	bellard	fprintf(logfile, "\n");
3384	e19e89a5	bellard	if (loglevel & CPU_LOG_TB_OP) {
3385	e19e89a5	bellard	fprintf(logfile, "OP:\n");
3386	e19e89a5	bellard	dump_ops(gen_opc_buf, gen_opparam_buf);
3387	e19e89a5	bellard	fprintf(logfile, "\n");
3388	e19e89a5	bellard	}
3389	cf495bcf	bellard	}
3390	7a3f1944	bellard	#endif
3391	cf495bcf	bellard	return 0;
3392	7a3f1944	bellard	}
3393	7a3f1944	bellard
3394	cf495bcf	bellard	int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
3395	7a3f1944	bellard	{
3396	e8af50a3	bellard	return gen_intermediate_code_internal(tb, 0, env);
3397	7a3f1944	bellard	}
3398	7a3f1944	bellard
3399	cf495bcf	bellard	int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
3400	7a3f1944	bellard	{
3401	e8af50a3	bellard	return gen_intermediate_code_internal(tb, 1, env);
3402	7a3f1944	bellard	}
3403	7a3f1944	bellard
3404	e80cfcfc	bellard	extern int ram_size;
3405	cf495bcf	bellard
3406	e80cfcfc	bellard	void cpu_reset(CPUSPARCState *env)
3407	e80cfcfc	bellard	{
3408	bb05683b	bellard	tlb_flush(env, 1);
3409	cf495bcf	bellard	env->cwp = 0;
3410	cf495bcf	bellard	env->wim = 1;
3411	cf495bcf	bellard	env->regwptr = env->regbase + (env->cwp * 16);
3412	e8af50a3	bellard	#if defined(CONFIG_USER_ONLY)
3413	cf495bcf	bellard	env->user_mode_only = 1;
3414	5ef54116	bellard	#ifdef TARGET_SPARC64
3415	6ef905f6	blueswir1	env->cleanwin = NWINDOWS - 2;
3416	6ef905f6	blueswir1	env->cansave = NWINDOWS - 2;
3417	6ef905f6	blueswir1	env->pstate = PS_RMO \| PS_PEF \| PS_IE;
3418	6ef905f6	blueswir1	env->asi = 0x82; // Primary no-fault
3419	5ef54116	bellard	#endif
3420	e8af50a3	bellard	#else
3421	32af58f9	blueswir1	env->psret = 0;
3422	e8af50a3	bellard	env->psrs = 1;
3423	0bee699e	bellard	env->psrps = 1;
3424	3475187d	bellard	#ifdef TARGET_SPARC64
3425	83469015	bellard	env->pstate = PS_PRIV;
3426	83469015	bellard	env->pc = 0x1fff0000000ULL;
3427	3475187d	bellard	#else
3428	83469015	bellard	env->pc = 0xffd00000;
3429	32af58f9	blueswir1	env->mmuregs[0] &= ~(MMU_E \| MMU_NF);
3430	3475187d	bellard	#endif
3431	83469015	bellard	env->npc = env->pc + 4;
3432	e8af50a3	bellard	#endif
3433	e80cfcfc	bellard	}
3434	e80cfcfc	bellard
3435	e80cfcfc	bellard	CPUSPARCState *cpu_sparc_init(void)
3436	e80cfcfc	bellard	{
3437	e80cfcfc	bellard	CPUSPARCState *env;
3438	e80cfcfc	bellard
3439	c68ea704	bellard	env = qemu_mallocz(sizeof(CPUSPARCState));
3440	c68ea704	bellard	if (!env)
3441	c68ea704	bellard	return NULL;
3442	c68ea704	bellard	cpu_exec_init(env);
3443	e80cfcfc	bellard	cpu_reset(env);
3444	cf495bcf	bellard	return (env);
3445	7a3f1944	bellard	}
3446	7a3f1944	bellard
3447	62724a37	blueswir1	static const sparc_def_t sparc_defs[] = {
3448	62724a37	blueswir1	#ifdef TARGET_SPARC64
3449	62724a37	blueswir1	{
3450	62724a37	blueswir1	.name = "TI UltraSparc II",
3451	62724a37	blueswir1	.iu_version = ((0x17ULL << 48) \| (0x11ULL << 32) \| (0 << 24)
3452	62724a37	blueswir1	\| (MAXTL << 8) \| (NWINDOWS - 1)),
3453	62724a37	blueswir1	.fpu_version = 0x00000000,
3454	62724a37	blueswir1	.mmu_version = 0,
3455	62724a37	blueswir1	},
3456	62724a37	blueswir1	#else
3457	62724a37	blueswir1	{
3458	62724a37	blueswir1	.name = "Fujitsu MB86904",
3459	62724a37	blueswir1	.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
3460	62724a37	blueswir1	.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3461	62724a37	blueswir1	.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
3462	62724a37	blueswir1	},
3463	e0353fe2	blueswir1	{
3464	5ef62c5c	blueswir1	.name = "Fujitsu MB86907",
3465	5ef62c5c	blueswir1	.iu_version = 0x05 << 24, /* Impl 0, ver 5 */
3466	5ef62c5c	blueswir1	.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3467	5ef62c5c	blueswir1	.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
3468	5ef62c5c	blueswir1	},
3469	5ef62c5c	blueswir1	{
3470	5ef62c5c	blueswir1	.name = "TI MicroSparc I",
3471	5ef62c5c	blueswir1	.iu_version = 0x41000000,
3472	5ef62c5c	blueswir1	.fpu_version = 4 << 17,
3473	5ef62c5c	blueswir1	.mmu_version = 0x41000000,
3474	5ef62c5c	blueswir1	},
3475	5ef62c5c	blueswir1	{
3476	e0353fe2	blueswir1	.name = "TI SuperSparc II",
3477	e0353fe2	blueswir1	.iu_version = 0x40000000,
3478	5ef62c5c	blueswir1	.fpu_version = 0 << 17,
3479	5ef62c5c	blueswir1	.mmu_version = 0x04000000,
3480	5ef62c5c	blueswir1	},
3481	5ef62c5c	blueswir1	{
3482	5ef62c5c	blueswir1	.name = "Ross RT620",
3483	5ef62c5c	blueswir1	.iu_version = 0x1e000000,
3484	5ef62c5c	blueswir1	.fpu_version = 1 << 17,
3485	5ef62c5c	blueswir1	.mmu_version = 0x17000000,
3486	e0353fe2	blueswir1	},
3487	62724a37	blueswir1	#endif
3488	62724a37	blueswir1	};
3489	62724a37	blueswir1
3490	62724a37	blueswir1	int sparc_find_by_name(const unsigned char name, const sparc_def_t *def)
3491	62724a37	blueswir1	{
3492	62724a37	blueswir1	int ret;
3493	62724a37	blueswir1	unsigned int i;
3494	62724a37	blueswir1
3495	62724a37	blueswir1	ret = -1;
3496	62724a37	blueswir1	*def = NULL;
3497	62724a37	blueswir1	for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3498	62724a37	blueswir1	if (strcasecmp(name, sparc_defs[i].name) == 0) {
3499	62724a37	blueswir1	*def = &sparc_defs[i];
3500	62724a37	blueswir1	ret = 0;
3501	62724a37	blueswir1	break;
3502	62724a37	blueswir1	}
3503	62724a37	blueswir1	}
3504	62724a37	blueswir1
3505	62724a37	blueswir1	return ret;
3506	62724a37	blueswir1	}
3507	62724a37	blueswir1
3508	62724a37	blueswir1	void sparc_cpu_list (FILE f, int (cpu_fprintf)(FILE f, const char fmt, ...))
3509	62724a37	blueswir1	{
3510	62724a37	blueswir1	unsigned int i;
3511	62724a37	blueswir1
3512	62724a37	blueswir1	for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
3513	62724a37	blueswir1	(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
3514	62724a37	blueswir1	sparc_defs[i].name,
3515	62724a37	blueswir1	sparc_defs[i].iu_version,
3516	62724a37	blueswir1	sparc_defs[i].fpu_version,
3517	62724a37	blueswir1	sparc_defs[i].mmu_version);
3518	62724a37	blueswir1	}
3519	62724a37	blueswir1	}
3520	62724a37	blueswir1
3521	62724a37	blueswir1	int cpu_sparc_register (CPUSPARCState env, const sparc_def_t def)
3522	62724a37	blueswir1	{
3523	62724a37	blueswir1	env->version = def->iu_version;
3524	62724a37	blueswir1	env->fsr = def->fpu_version;
3525	62724a37	blueswir1	#if !defined(TARGET_SPARC64)
3526	62724a37	blueswir1	env->mmuregs[0] = def->mmu_version;
3527	62724a37	blueswir1	#endif
3528	62724a37	blueswir1	return 0;
3529	62724a37	blueswir1	}
3530	62724a37	blueswir1
3531	7a3f1944	bellard	#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
3532	7a3f1944	bellard
3533	7fe48483	bellard	void cpu_dump_state(CPUState env, FILE f,
3534	7fe48483	bellard	int (cpu_fprintf)(FILE f, const char *fmt, ...),
3535	7fe48483	bellard	int flags)
3536	7a3f1944	bellard	{
3537	cf495bcf	bellard	int i, x;
3538	cf495bcf	bellard
3539	af7bf89b	bellard	cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
3540	7fe48483	bellard	cpu_fprintf(f, "General Registers:\n");
3541	cf495bcf	bellard	for (i = 0; i < 4; i++)
3542	af7bf89b	bellard	cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3543	7fe48483	bellard	cpu_fprintf(f, "\n");
3544	cf495bcf	bellard	for (; i < 8; i++)
3545	af7bf89b	bellard	cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
3546	7fe48483	bellard	cpu_fprintf(f, "\nCurrent Register Window:\n");
3547	cf495bcf	bellard	for (x = 0; x < 3; x++) {
3548	cf495bcf	bellard	for (i = 0; i < 4; i++)
3549	af7bf89b	bellard	cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3550	cf495bcf	bellard	(x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
3551	cf495bcf	bellard	env->regwptr[i + x * 8]);
3552	7fe48483	bellard	cpu_fprintf(f, "\n");
3553	cf495bcf	bellard	for (; i < 8; i++)
3554	af7bf89b	bellard	cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
3555	cf495bcf	bellard	(x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
3556	cf495bcf	bellard	env->regwptr[i + x * 8]);
3557	7fe48483	bellard	cpu_fprintf(f, "\n");
3558	cf495bcf	bellard	}
3559	7fe48483	bellard	cpu_fprintf(f, "\nFloating Point Registers:\n");
3560	e8af50a3	bellard	for (i = 0; i < 32; i++) {
3561	e8af50a3	bellard	if ((i & 3) == 0)
3562	7fe48483	bellard	cpu_fprintf(f, "%%f%02d:", i);
3563	7fe48483	bellard	cpu_fprintf(f, " %016lf", env->fpr[i]);
3564	e8af50a3	bellard	if ((i & 3) == 3)
3565	7fe48483	bellard	cpu_fprintf(f, "\n");
3566	e8af50a3	bellard	}
3567	ded3ab80	pbrook	#ifdef TARGET_SPARC64
3568	3299908c	blueswir1	cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
3569	3299908c	blueswir1	env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
3570	ded3ab80	pbrook	cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
3571	ded3ab80	pbrook	env->cansave, env->canrestore, env->otherwin, env->wstate,
3572	ded3ab80	pbrook	env->cleanwin, NWINDOWS - 1 - env->cwp);
3573	ded3ab80	pbrook	#else
3574	7fe48483	bellard	cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
3575	cf495bcf	bellard	GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
3576	cf495bcf	bellard	GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
3577	e8af50a3	bellard	env->psrs?'S':'-', env->psrps?'P':'-',
3578	e8af50a3	bellard	env->psret?'E':'-', env->wim);
3579	ded3ab80	pbrook	#endif
3580	3475187d	bellard	cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
3581	7a3f1944	bellard	}
3582	edfcbd99	bellard
3583	e80cfcfc	bellard	#if defined(CONFIG_USER_ONLY)
3584	9b3c35e0	j_mayer	target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
3585	edfcbd99	bellard	{
3586	edfcbd99	bellard	return addr;
3587	edfcbd99	bellard	}
3588	658138bc	bellard
3589	e80cfcfc	bellard	#else
3590	af7bf89b	bellard	extern int get_physical_address (CPUState env, target_phys_addr_t physical, int *prot,
3591	af7bf89b	bellard	int *access_index, target_ulong address, int rw,
3592	0fa85d43	bellard	int is_user);
3593	0fa85d43	bellard
3594	9b3c35e0	j_mayer	target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
3595	e80cfcfc	bellard	{
3596	af7bf89b	bellard	target_phys_addr_t phys_addr;
3597	e80cfcfc	bellard	int prot, access_index;
3598	e80cfcfc	bellard
3599	e80cfcfc	bellard	if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
3600	6b1575b7	bellard	if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
3601	6b1575b7	bellard	return -1;
3602	6c36d3fa	blueswir1	if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
3603	6c36d3fa	blueswir1	return -1;
3604	e80cfcfc	bellard	return phys_addr;
3605	e80cfcfc	bellard	}
3606	e80cfcfc	bellard	#endif
3607	e80cfcfc	bellard
3608	658138bc	bellard	void helper_flush(target_ulong addr)
3609	658138bc	bellard	{
3610	658138bc	bellard	addr &= ~7;
3611	658138bc	bellard	tb_invalidate_page_range(addr, addr + 8);
3612	658138bc	bellard	}

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