Revision ceecf1d1 hw/mips_malta.c
b/hw/mips_malta.c | ||
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418 | 418 |
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419 | 419 |
s->display_text[8] = '\0'; |
420 | 420 |
snprintf(s->display_text, 9, " "); |
421 |
malta_fpga_update_display(s); |
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} |
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static void malta_fpga_uart_init(CharDriverState *chr) |
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{ |
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qemu_chr_printf(chr, "CBUS UART\r\n"); |
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} |
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static void malta_fpga_led_init(CharDriverState *chr) |
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{ |
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qemu_chr_printf(chr, "\e[HMalta LEDBAR\r\n"); |
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qemu_chr_printf(chr, "+--------+\r\n"); |
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qemu_chr_printf(chr, "+ +\r\n"); |
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qemu_chr_printf(chr, "+--------+\r\n"); |
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qemu_chr_printf(chr, "\n"); |
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qemu_chr_printf(chr, "Malta ASCII\r\n"); |
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qemu_chr_printf(chr, "+--------+\r\n"); |
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qemu_chr_printf(chr, "+ +\r\n"); |
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qemu_chr_printf(chr, "+--------+\r\n"); |
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422 | 439 |
} |
423 | 440 |
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424 | 441 |
static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env) |
... | ... | |
436 | 453 |
/* 0xa00 is less than a page, so will still get the right offsets. */ |
437 | 454 |
cpu_register_physical_memory(base + 0xa00, 0x100000 - 0xa00, malta); |
438 | 455 |
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s->display = qemu_chr_open("fpga", "vc:320x200"); |
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qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n"); |
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qemu_chr_printf(s->display, "+--------+\r\n"); |
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qemu_chr_printf(s->display, "+ +\r\n"); |
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qemu_chr_printf(s->display, "+--------+\r\n"); |
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qemu_chr_printf(s->display, "\n"); |
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qemu_chr_printf(s->display, "Malta ASCII\r\n"); |
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qemu_chr_printf(s->display, "+--------+\r\n"); |
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qemu_chr_printf(s->display, "+ +\r\n"); |
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qemu_chr_printf(s->display, "+--------+\r\n"); |
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uart_chr = qemu_chr_open("cbus", "vc:80Cx24C"); |
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qemu_chr_printf(uart_chr, "CBUS UART\r\n"); |
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s->display = qemu_chr_open("fpga", "vc:320x200", malta_fpga_led_init); |
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uart_chr = qemu_chr_open("cbus", "vc:80Cx24C", malta_fpga_uart_init); |
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452 | 459 |
s->uart = |
453 | 460 |
serial_mm_init(base + 0x900, 3, env->irq[2], 230400, uart_chr, 1); |
454 | 461 |
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