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/*
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* gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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*/
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#include "config.h" |
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#include "qemu-common.h" |
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#ifdef CONFIG_USER_ONLY
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <stdarg.h> |
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#include <string.h> |
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#include <errno.h> |
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#include <unistd.h> |
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#include <fcntl.h> |
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#include "qemu.h" |
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#else
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#include "qemu-char.h" |
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#include "sysemu.h" |
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#include "gdbstub.h" |
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#endif
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#define MAX_PACKET_LENGTH 4096 |
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#include "qemu_socket.h" |
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enum {
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GDB_SIGNAL_0 = 0,
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GDB_SIGNAL_INT = 2,
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GDB_SIGNAL_TRAP = 5,
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GDB_SIGNAL_UNKNOWN = 143
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}; |
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#ifdef CONFIG_USER_ONLY
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/* Map target signal numbers to GDB protocol signal numbers and vice
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* versa. For user emulation's currently supported systems, we can
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* assume most signals are defined.
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*/
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static int gdb_signal_table[] = { |
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0,
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TARGET_SIGHUP, |
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TARGET_SIGINT, |
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TARGET_SIGQUIT, |
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TARGET_SIGILL, |
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TARGET_SIGTRAP, |
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TARGET_SIGABRT, |
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-1, /* SIGEMT */ |
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TARGET_SIGFPE, |
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TARGET_SIGKILL, |
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TARGET_SIGBUS, |
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TARGET_SIGSEGV, |
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TARGET_SIGSYS, |
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TARGET_SIGPIPE, |
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TARGET_SIGALRM, |
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TARGET_SIGTERM, |
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TARGET_SIGURG, |
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TARGET_SIGSTOP, |
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TARGET_SIGTSTP, |
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TARGET_SIGCONT, |
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TARGET_SIGCHLD, |
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TARGET_SIGTTIN, |
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TARGET_SIGTTOU, |
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TARGET_SIGIO, |
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TARGET_SIGXCPU, |
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TARGET_SIGXFSZ, |
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TARGET_SIGVTALRM, |
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TARGET_SIGPROF, |
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TARGET_SIGWINCH, |
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-1, /* SIGLOST */ |
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TARGET_SIGUSR1, |
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TARGET_SIGUSR2, |
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#ifdef TARGET_SIGPWR
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TARGET_SIGPWR, |
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#else
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-1,
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#endif
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-1, /* SIGPOLL */ |
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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#ifdef __SIGRTMIN
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__SIGRTMIN + 1,
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__SIGRTMIN + 2,
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__SIGRTMIN + 3,
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__SIGRTMIN + 4,
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__SIGRTMIN + 5,
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__SIGRTMIN + 6,
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__SIGRTMIN + 7,
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__SIGRTMIN + 8,
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__SIGRTMIN + 9,
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__SIGRTMIN + 10,
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__SIGRTMIN + 11,
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__SIGRTMIN + 12,
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__SIGRTMIN + 13,
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__SIGRTMIN + 14,
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__SIGRTMIN + 15,
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__SIGRTMIN + 16,
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__SIGRTMIN + 17,
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__SIGRTMIN + 18,
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__SIGRTMIN + 19,
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__SIGRTMIN + 20,
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__SIGRTMIN + 21,
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__SIGRTMIN + 22,
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__SIGRTMIN + 23,
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__SIGRTMIN + 24,
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__SIGRTMIN + 25,
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__SIGRTMIN + 26,
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__SIGRTMIN + 27,
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__SIGRTMIN + 28,
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__SIGRTMIN + 29,
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__SIGRTMIN + 30,
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__SIGRTMIN + 31,
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-1, /* SIGCANCEL */ |
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__SIGRTMIN, |
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__SIGRTMIN + 32,
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__SIGRTMIN + 33,
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__SIGRTMIN + 34,
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__SIGRTMIN + 35,
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__SIGRTMIN + 36,
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__SIGRTMIN + 37,
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__SIGRTMIN + 38,
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__SIGRTMIN + 39,
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__SIGRTMIN + 40,
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__SIGRTMIN + 41,
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__SIGRTMIN + 42,
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__SIGRTMIN + 43,
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__SIGRTMIN + 44,
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__SIGRTMIN + 45,
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__SIGRTMIN + 46,
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__SIGRTMIN + 47,
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__SIGRTMIN + 48,
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__SIGRTMIN + 49,
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__SIGRTMIN + 50,
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__SIGRTMIN + 51,
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__SIGRTMIN + 52,
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__SIGRTMIN + 53,
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__SIGRTMIN + 54,
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__SIGRTMIN + 55,
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__SIGRTMIN + 56,
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__SIGRTMIN + 57,
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__SIGRTMIN + 58,
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__SIGRTMIN + 59,
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__SIGRTMIN + 60,
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__SIGRTMIN + 61,
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__SIGRTMIN + 62,
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__SIGRTMIN + 63,
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__SIGRTMIN + 64,
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__SIGRTMIN + 65,
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__SIGRTMIN + 66,
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__SIGRTMIN + 67,
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__SIGRTMIN + 68,
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__SIGRTMIN + 69,
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__SIGRTMIN + 70,
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__SIGRTMIN + 71,
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__SIGRTMIN + 72,
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__SIGRTMIN + 73,
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__SIGRTMIN + 74,
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__SIGRTMIN + 75,
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__SIGRTMIN + 76,
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__SIGRTMIN + 77,
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__SIGRTMIN + 78,
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__SIGRTMIN + 79,
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__SIGRTMIN + 80,
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__SIGRTMIN + 81,
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__SIGRTMIN + 82,
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__SIGRTMIN + 83,
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__SIGRTMIN + 84,
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__SIGRTMIN + 85,
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__SIGRTMIN + 86,
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__SIGRTMIN + 87,
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__SIGRTMIN + 88,
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__SIGRTMIN + 89,
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__SIGRTMIN + 90,
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__SIGRTMIN + 91,
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__SIGRTMIN + 92,
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__SIGRTMIN + 93,
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__SIGRTMIN + 94,
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__SIGRTMIN + 95,
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-1, /* SIGINFO */ |
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-1, /* UNKNOWN */ |
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-1, /* DEFAULT */ |
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-1,
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-1,
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-1,
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-1,
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-1,
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-1
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#endif
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}; |
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#else
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/* In system mode we only need SIGINT and SIGTRAP; other signals
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are not yet supported. */
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enum {
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TARGET_SIGINT = 2,
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TARGET_SIGTRAP = 5
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}; |
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static int gdb_signal_table[] = { |
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-1,
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-1,
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TARGET_SIGINT, |
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-1,
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-1,
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TARGET_SIGTRAP |
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}; |
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#endif
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#ifdef CONFIG_USER_ONLY
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static int target_signal_to_gdb (int sig) |
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{ |
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int i;
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for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++) |
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if (gdb_signal_table[i] == sig)
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return i;
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return GDB_SIGNAL_UNKNOWN;
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} |
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#endif
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static int gdb_signal_to_target (int sig) |
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{ |
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if (sig < ARRAY_SIZE (gdb_signal_table))
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return gdb_signal_table[sig];
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else
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return -1; |
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} |
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//#define DEBUG_GDB
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typedef struct GDBRegisterState { |
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int base_reg;
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int num_regs;
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gdb_reg_cb get_reg; |
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gdb_reg_cb set_reg; |
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const char *xml; |
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struct GDBRegisterState *next;
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} GDBRegisterState; |
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enum RSState {
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RS_IDLE, |
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RS_GETLINE, |
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RS_CHKSUM1, |
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RS_CHKSUM2, |
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RS_SYSCALL, |
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}; |
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typedef struct GDBState { |
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CPUState *c_cpu; /* current CPU for step/continue ops */
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CPUState *g_cpu; /* current CPU for other ops */
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CPUState *query_cpu; /* for q{f|s}ThreadInfo */
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enum RSState state; /* parsing state */ |
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char line_buf[MAX_PACKET_LENGTH];
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int line_buf_index;
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int line_csum;
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uint8_t last_packet[MAX_PACKET_LENGTH + 4];
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int last_packet_len;
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int signal;
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#ifdef CONFIG_USER_ONLY
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int fd;
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int running_state;
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#else
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CharDriverState *chr; |
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#endif
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} GDBState; |
290 |
|
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/* By default use no IRQs and no timers while single stepping so as to
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* make single stepping like an ICE HW step.
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*/
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static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER; |
295 |
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static GDBState *gdbserver_state;
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/* This is an ugly hack to cope with both new and old gdb.
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If gdb sends qXfer:features:read then assume we're talking to a newish
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gdb that understands target descriptions. */
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static int gdb_has_xml; |
302 |
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#ifdef CONFIG_USER_ONLY
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/* XXX: This is not thread safe. Do we care? */
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static int gdbserver_fd = -1; |
306 |
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static int get_char(GDBState *s) |
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{ |
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uint8_t ch; |
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int ret;
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|
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for(;;) {
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ret = recv(s->fd, &ch, 1, 0); |
314 |
if (ret < 0) { |
315 |
if (errno == ECONNRESET)
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s->fd = -1;
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if (errno != EINTR && errno != EAGAIN)
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return -1; |
319 |
} else if (ret == 0) { |
320 |
close(s->fd); |
321 |
s->fd = -1;
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return -1; |
323 |
} else {
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break;
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} |
326 |
} |
327 |
return ch;
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} |
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#endif
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static gdb_syscall_complete_cb gdb_current_syscall_cb;
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enum {
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GDB_SYS_UNKNOWN, |
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GDB_SYS_ENABLED, |
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GDB_SYS_DISABLED, |
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} gdb_syscall_mode; |
338 |
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/* If gdb is connected when the first semihosting syscall occurs then use
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remote gdb syscalls. Otherwise use native file IO. */
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int use_gdb_syscalls(void) |
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{ |
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if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
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gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED |
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: GDB_SYS_DISABLED); |
346 |
} |
347 |
return gdb_syscall_mode == GDB_SYS_ENABLED;
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} |
349 |
|
350 |
/* Resume execution. */
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static inline void gdb_continue(GDBState *s) |
352 |
{ |
353 |
#ifdef CONFIG_USER_ONLY
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s->running_state = 1;
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#else
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vm_start(); |
357 |
#endif
|
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} |
359 |
|
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static void put_buffer(GDBState *s, const uint8_t *buf, int len) |
361 |
{ |
362 |
#ifdef CONFIG_USER_ONLY
|
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int ret;
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|
365 |
while (len > 0) { |
366 |
ret = send(s->fd, buf, len, 0);
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if (ret < 0) { |
368 |
if (errno != EINTR && errno != EAGAIN)
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return;
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370 |
} else {
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buf += ret; |
372 |
len -= ret; |
373 |
} |
374 |
} |
375 |
#else
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qemu_chr_write(s->chr, buf, len); |
377 |
#endif
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378 |
} |
379 |
|
380 |
static inline int fromhex(int v) |
381 |
{ |
382 |
if (v >= '0' && v <= '9') |
383 |
return v - '0'; |
384 |
else if (v >= 'A' && v <= 'F') |
385 |
return v - 'A' + 10; |
386 |
else if (v >= 'a' && v <= 'f') |
387 |
return v - 'a' + 10; |
388 |
else
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return 0; |
390 |
} |
391 |
|
392 |
static inline int tohex(int v) |
393 |
{ |
394 |
if (v < 10) |
395 |
return v + '0'; |
396 |
else
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397 |
return v - 10 + 'a'; |
398 |
} |
399 |
|
400 |
static void memtohex(char *buf, const uint8_t *mem, int len) |
401 |
{ |
402 |
int i, c;
|
403 |
char *q;
|
404 |
q = buf; |
405 |
for(i = 0; i < len; i++) { |
406 |
c = mem[i]; |
407 |
*q++ = tohex(c >> 4);
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408 |
*q++ = tohex(c & 0xf);
|
409 |
} |
410 |
*q = '\0';
|
411 |
} |
412 |
|
413 |
static void hextomem(uint8_t *mem, const char *buf, int len) |
414 |
{ |
415 |
int i;
|
416 |
|
417 |
for(i = 0; i < len; i++) { |
418 |
mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]); |
419 |
buf += 2;
|
420 |
} |
421 |
} |
422 |
|
423 |
/* return -1 if error, 0 if OK */
|
424 |
static int put_packet_binary(GDBState *s, const char *buf, int len) |
425 |
{ |
426 |
int csum, i;
|
427 |
uint8_t *p; |
428 |
|
429 |
for(;;) {
|
430 |
p = s->last_packet; |
431 |
*(p++) = '$';
|
432 |
memcpy(p, buf, len); |
433 |
p += len; |
434 |
csum = 0;
|
435 |
for(i = 0; i < len; i++) { |
436 |
csum += buf[i]; |
437 |
} |
438 |
*(p++) = '#';
|
439 |
*(p++) = tohex((csum >> 4) & 0xf); |
440 |
*(p++) = tohex((csum) & 0xf);
|
441 |
|
442 |
s->last_packet_len = p - s->last_packet; |
443 |
put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len); |
444 |
|
445 |
#ifdef CONFIG_USER_ONLY
|
446 |
i = get_char(s); |
447 |
if (i < 0) |
448 |
return -1; |
449 |
if (i == '+') |
450 |
break;
|
451 |
#else
|
452 |
break;
|
453 |
#endif
|
454 |
} |
455 |
return 0; |
456 |
} |
457 |
|
458 |
/* return -1 if error, 0 if OK */
|
459 |
static int put_packet(GDBState *s, const char *buf) |
460 |
{ |
461 |
#ifdef DEBUG_GDB
|
462 |
printf("reply='%s'\n", buf);
|
463 |
#endif
|
464 |
|
465 |
return put_packet_binary(s, buf, strlen(buf));
|
466 |
} |
467 |
|
468 |
/* The GDB remote protocol transfers values in target byte order. This means
|
469 |
we can use the raw memory access routines to access the value buffer.
|
470 |
Conveniently, these also handle the case where the buffer is mis-aligned.
|
471 |
*/
|
472 |
#define GET_REG8(val) do { \ |
473 |
stb_p(mem_buf, val); \ |
474 |
return 1; \ |
475 |
} while(0) |
476 |
#define GET_REG16(val) do { \ |
477 |
stw_p(mem_buf, val); \ |
478 |
return 2; \ |
479 |
} while(0) |
480 |
#define GET_REG32(val) do { \ |
481 |
stl_p(mem_buf, val); \ |
482 |
return 4; \ |
483 |
} while(0) |
484 |
#define GET_REG64(val) do { \ |
485 |
stq_p(mem_buf, val); \ |
486 |
return 8; \ |
487 |
} while(0) |
488 |
|
489 |
#if TARGET_LONG_BITS == 64 |
490 |
#define GET_REGL(val) GET_REG64(val)
|
491 |
#define ldtul_p(addr) ldq_p(addr)
|
492 |
#else
|
493 |
#define GET_REGL(val) GET_REG32(val)
|
494 |
#define ldtul_p(addr) ldl_p(addr)
|
495 |
#endif
|
496 |
|
497 |
#if defined(TARGET_I386)
|
498 |
|
499 |
#ifdef TARGET_X86_64
|
500 |
static const int gpr_map[16] = { |
501 |
R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP, |
502 |
8, 9, 10, 11, 12, 13, 14, 15 |
503 |
}; |
504 |
#else
|
505 |
static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7}; |
506 |
#endif
|
507 |
|
508 |
#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25) |
509 |
|
510 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
511 |
{ |
512 |
if (n < CPU_NB_REGS) {
|
513 |
GET_REGL(env->regs[gpr_map[n]]); |
514 |
} else if (n >= CPU_NB_REGS + 8 && n < CPU_NB_REGS + 16) { |
515 |
/* FIXME: byteswap float values. */
|
516 |
#ifdef USE_X86LDOUBLE
|
517 |
memcpy(mem_buf, &env->fpregs[n - (CPU_NB_REGS + 8)], 10); |
518 |
#else
|
519 |
memset(mem_buf, 0, 10); |
520 |
#endif
|
521 |
return 10; |
522 |
} else if (n >= CPU_NB_REGS + 24) { |
523 |
n -= CPU_NB_REGS + 24;
|
524 |
if (n < CPU_NB_REGS) {
|
525 |
stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
|
526 |
stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1)); |
527 |
return 16; |
528 |
} else if (n == CPU_NB_REGS) { |
529 |
GET_REG32(env->mxcsr); |
530 |
} |
531 |
} else {
|
532 |
n -= CPU_NB_REGS; |
533 |
switch (n) {
|
534 |
case 0: GET_REGL(env->eip); |
535 |
case 1: GET_REG32(env->eflags); |
536 |
case 2: GET_REG32(env->segs[R_CS].selector); |
537 |
case 3: GET_REG32(env->segs[R_SS].selector); |
538 |
case 4: GET_REG32(env->segs[R_DS].selector); |
539 |
case 5: GET_REG32(env->segs[R_ES].selector); |
540 |
case 6: GET_REG32(env->segs[R_FS].selector); |
541 |
case 7: GET_REG32(env->segs[R_GS].selector); |
542 |
/* 8...15 x87 regs. */
|
543 |
case 16: GET_REG32(env->fpuc); |
544 |
case 17: GET_REG32((env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11); |
545 |
case 18: GET_REG32(0); /* ftag */ |
546 |
case 19: GET_REG32(0); /* fiseg */ |
547 |
case 20: GET_REG32(0); /* fioff */ |
548 |
case 21: GET_REG32(0); /* foseg */ |
549 |
case 22: GET_REG32(0); /* fooff */ |
550 |
case 23: GET_REG32(0); /* fop */ |
551 |
/* 24+ xmm regs. */
|
552 |
} |
553 |
} |
554 |
return 0; |
555 |
} |
556 |
|
557 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int i) |
558 |
{ |
559 |
uint32_t tmp; |
560 |
|
561 |
if (i < CPU_NB_REGS) {
|
562 |
env->regs[gpr_map[i]] = ldtul_p(mem_buf); |
563 |
return sizeof(target_ulong); |
564 |
} else if (i >= CPU_NB_REGS + 8 && i < CPU_NB_REGS + 16) { |
565 |
i -= CPU_NB_REGS + 8;
|
566 |
#ifdef USE_X86LDOUBLE
|
567 |
memcpy(&env->fpregs[i], mem_buf, 10);
|
568 |
#endif
|
569 |
return 10; |
570 |
} else if (i >= CPU_NB_REGS + 24) { |
571 |
i -= CPU_NB_REGS + 24;
|
572 |
if (i < CPU_NB_REGS) {
|
573 |
env->xmm_regs[i].XMM_Q(0) = ldq_p(mem_buf);
|
574 |
env->xmm_regs[i].XMM_Q(1) = ldq_p(mem_buf + 8); |
575 |
return 16; |
576 |
} else if (i == CPU_NB_REGS) { |
577 |
env->mxcsr = ldl_p(mem_buf); |
578 |
return 4; |
579 |
} |
580 |
} else {
|
581 |
i -= CPU_NB_REGS; |
582 |
switch (i) {
|
583 |
case 0: env->eip = ldtul_p(mem_buf); return sizeof(target_ulong); |
584 |
case 1: env->eflags = ldl_p(mem_buf); return 4; |
585 |
#if defined(CONFIG_USER_ONLY)
|
586 |
#define LOAD_SEG(index, sreg)\
|
587 |
tmp = ldl_p(mem_buf);\ |
588 |
if (tmp != env->segs[sreg].selector)\
|
589 |
cpu_x86_load_seg(env, sreg, tmp); |
590 |
#else
|
591 |
/* FIXME: Honor segment registers. Needs to avoid raising an exception
|
592 |
when the selector is invalid. */
|
593 |
#define LOAD_SEG(index, sreg) do {} while(0) |
594 |
#endif
|
595 |
case 2: LOAD_SEG(10, R_CS); return 4; |
596 |
case 3: LOAD_SEG(11, R_SS); return 4; |
597 |
case 4: LOAD_SEG(12, R_DS); return 4; |
598 |
case 5: LOAD_SEG(13, R_ES); return 4; |
599 |
case 6: LOAD_SEG(14, R_FS); return 4; |
600 |
case 7: LOAD_SEG(15, R_GS); return 4; |
601 |
/* 8...15 x87 regs. */
|
602 |
case 16: env->fpuc = ldl_p(mem_buf); return 4; |
603 |
case 17: |
604 |
tmp = ldl_p(mem_buf); |
605 |
env->fpstt = (tmp >> 11) & 7; |
606 |
env->fpus = tmp & ~0x3800;
|
607 |
return 4; |
608 |
case 18: /* ftag */ return 4; |
609 |
case 19: /* fiseg */ return 4; |
610 |
case 20: /* fioff */ return 4; |
611 |
case 21: /* foseg */ return 4; |
612 |
case 22: /* fooff */ return 4; |
613 |
case 23: /* fop */ return 4; |
614 |
/* 24+ xmm regs. */
|
615 |
} |
616 |
} |
617 |
/* Unrecognised register. */
|
618 |
return 0; |
619 |
} |
620 |
|
621 |
#elif defined (TARGET_PPC)
|
622 |
|
623 |
#define NUM_CORE_REGS 71 |
624 |
|
625 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
626 |
{ |
627 |
if (n < 32) { |
628 |
/* gprs */
|
629 |
GET_REGL(env->gpr[n]); |
630 |
} else if (n < 64) { |
631 |
/* fprs */
|
632 |
stfq_p(mem_buf, env->fpr[n-32]);
|
633 |
return 8; |
634 |
} else {
|
635 |
switch (n) {
|
636 |
case 64: GET_REGL(env->nip); |
637 |
case 65: GET_REGL(env->msr); |
638 |
case 66: |
639 |
{ |
640 |
uint32_t cr = 0;
|
641 |
int i;
|
642 |
for (i = 0; i < 8; i++) |
643 |
cr |= env->crf[i] << (32 - ((i + 1) * 4)); |
644 |
GET_REG32(cr); |
645 |
} |
646 |
case 67: GET_REGL(env->lr); |
647 |
case 68: GET_REGL(env->ctr); |
648 |
case 69: GET_REGL(env->xer); |
649 |
case 70: GET_REG32(0); /* fpscr */ |
650 |
} |
651 |
} |
652 |
return 0; |
653 |
} |
654 |
|
655 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
656 |
{ |
657 |
if (n < 32) { |
658 |
/* gprs */
|
659 |
env->gpr[n] = ldtul_p(mem_buf); |
660 |
return sizeof(target_ulong); |
661 |
} else if (n < 64) { |
662 |
/* fprs */
|
663 |
env->fpr[n-32] = ldfq_p(mem_buf);
|
664 |
return 8; |
665 |
} else {
|
666 |
switch (n) {
|
667 |
case 64: |
668 |
env->nip = ldtul_p(mem_buf); |
669 |
return sizeof(target_ulong); |
670 |
case 65: |
671 |
ppc_store_msr(env, ldtul_p(mem_buf)); |
672 |
return sizeof(target_ulong); |
673 |
case 66: |
674 |
{ |
675 |
uint32_t cr = ldl_p(mem_buf); |
676 |
int i;
|
677 |
for (i = 0; i < 8; i++) |
678 |
env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF; |
679 |
return 4; |
680 |
} |
681 |
case 67: |
682 |
env->lr = ldtul_p(mem_buf); |
683 |
return sizeof(target_ulong); |
684 |
case 68: |
685 |
env->ctr = ldtul_p(mem_buf); |
686 |
return sizeof(target_ulong); |
687 |
case 69: |
688 |
env->xer = ldtul_p(mem_buf); |
689 |
return sizeof(target_ulong); |
690 |
case 70: |
691 |
/* fpscr */
|
692 |
return 4; |
693 |
} |
694 |
} |
695 |
return 0; |
696 |
} |
697 |
|
698 |
#elif defined (TARGET_SPARC)
|
699 |
|
700 |
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
|
701 |
#define NUM_CORE_REGS 86 |
702 |
#else
|
703 |
#define NUM_CORE_REGS 72 |
704 |
#endif
|
705 |
|
706 |
#ifdef TARGET_ABI32
|
707 |
#define GET_REGA(val) GET_REG32(val)
|
708 |
#else
|
709 |
#define GET_REGA(val) GET_REGL(val)
|
710 |
#endif
|
711 |
|
712 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
713 |
{ |
714 |
if (n < 8) { |
715 |
/* g0..g7 */
|
716 |
GET_REGA(env->gregs[n]); |
717 |
} |
718 |
if (n < 32) { |
719 |
/* register window */
|
720 |
GET_REGA(env->regwptr[n - 8]);
|
721 |
} |
722 |
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
|
723 |
if (n < 64) { |
724 |
/* fprs */
|
725 |
GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
|
726 |
} |
727 |
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
|
728 |
switch (n) {
|
729 |
case 64: GET_REGA(env->y); |
730 |
case 65: GET_REGA(GET_PSR(env)); |
731 |
case 66: GET_REGA(env->wim); |
732 |
case 67: GET_REGA(env->tbr); |
733 |
case 68: GET_REGA(env->pc); |
734 |
case 69: GET_REGA(env->npc); |
735 |
case 70: GET_REGA(env->fsr); |
736 |
case 71: GET_REGA(0); /* csr */ |
737 |
default: GET_REGA(0); |
738 |
} |
739 |
#else
|
740 |
if (n < 64) { |
741 |
/* f0-f31 */
|
742 |
GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
|
743 |
} |
744 |
if (n < 80) { |
745 |
/* f32-f62 (double width, even numbers only) */
|
746 |
uint64_t val; |
747 |
|
748 |
val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32; |
749 |
val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]); |
750 |
GET_REG64(val); |
751 |
} |
752 |
switch (n) {
|
753 |
case 80: GET_REGL(env->pc); |
754 |
case 81: GET_REGL(env->npc); |
755 |
case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) | |
756 |
((env->asi & 0xff) << 24) | |
757 |
((env->pstate & 0xfff) << 8) | |
758 |
GET_CWP64(env)); |
759 |
case 83: GET_REGL(env->fsr); |
760 |
case 84: GET_REGL(env->fprs); |
761 |
case 85: GET_REGL(env->y); |
762 |
} |
763 |
#endif
|
764 |
return 0; |
765 |
} |
766 |
|
767 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
768 |
{ |
769 |
#if defined(TARGET_ABI32)
|
770 |
abi_ulong tmp; |
771 |
|
772 |
tmp = ldl_p(mem_buf); |
773 |
#else
|
774 |
target_ulong tmp; |
775 |
|
776 |
tmp = ldtul_p(mem_buf); |
777 |
#endif
|
778 |
|
779 |
if (n < 8) { |
780 |
/* g0..g7 */
|
781 |
env->gregs[n] = tmp; |
782 |
} else if (n < 32) { |
783 |
/* register window */
|
784 |
env->regwptr[n - 8] = tmp;
|
785 |
} |
786 |
#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
|
787 |
else if (n < 64) { |
788 |
/* fprs */
|
789 |
*((uint32_t *)&env->fpr[n - 32]) = tmp;
|
790 |
} else {
|
791 |
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
|
792 |
switch (n) {
|
793 |
case 64: env->y = tmp; break; |
794 |
case 65: PUT_PSR(env, tmp); break; |
795 |
case 66: env->wim = tmp; break; |
796 |
case 67: env->tbr = tmp; break; |
797 |
case 68: env->pc = tmp; break; |
798 |
case 69: env->npc = tmp; break; |
799 |
case 70: env->fsr = tmp; break; |
800 |
default: return 0; |
801 |
} |
802 |
} |
803 |
return 4; |
804 |
#else
|
805 |
else if (n < 64) { |
806 |
/* f0-f31 */
|
807 |
env->fpr[n] = ldfl_p(mem_buf); |
808 |
return 4; |
809 |
} else if (n < 80) { |
810 |
/* f32-f62 (double width, even numbers only) */
|
811 |
*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32; |
812 |
*((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp; |
813 |
} else {
|
814 |
switch (n) {
|
815 |
case 80: env->pc = tmp; break; |
816 |
case 81: env->npc = tmp; break; |
817 |
case 82: |
818 |
PUT_CCR(env, tmp >> 32);
|
819 |
env->asi = (tmp >> 24) & 0xff; |
820 |
env->pstate = (tmp >> 8) & 0xfff; |
821 |
PUT_CWP64(env, tmp & 0xff);
|
822 |
break;
|
823 |
case 83: env->fsr = tmp; break; |
824 |
case 84: env->fprs = tmp; break; |
825 |
case 85: env->y = tmp; break; |
826 |
default: return 0; |
827 |
} |
828 |
} |
829 |
return 8; |
830 |
#endif
|
831 |
} |
832 |
#elif defined (TARGET_ARM)
|
833 |
|
834 |
/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
|
835 |
whatever the target description contains. Due to a historical mishap
|
836 |
the FPA registers appear in between core integer regs and the CPSR.
|
837 |
We hack round this by giving the FPA regs zero size when talking to a
|
838 |
newer gdb. */
|
839 |
#define NUM_CORE_REGS 26 |
840 |
#define GDB_CORE_XML "arm-core.xml" |
841 |
|
842 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
843 |
{ |
844 |
if (n < 16) { |
845 |
/* Core integer register. */
|
846 |
GET_REG32(env->regs[n]); |
847 |
} |
848 |
if (n < 24) { |
849 |
/* FPA registers. */
|
850 |
if (gdb_has_xml)
|
851 |
return 0; |
852 |
memset(mem_buf, 0, 12); |
853 |
return 12; |
854 |
} |
855 |
switch (n) {
|
856 |
case 24: |
857 |
/* FPA status register. */
|
858 |
if (gdb_has_xml)
|
859 |
return 0; |
860 |
GET_REG32(0);
|
861 |
case 25: |
862 |
/* CPSR */
|
863 |
GET_REG32(cpsr_read(env)); |
864 |
} |
865 |
/* Unknown register. */
|
866 |
return 0; |
867 |
} |
868 |
|
869 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
870 |
{ |
871 |
uint32_t tmp; |
872 |
|
873 |
tmp = ldl_p(mem_buf); |
874 |
|
875 |
/* Mask out low bit of PC to workaround gdb bugs. This will probably
|
876 |
cause problems if we ever implement the Jazelle DBX extensions. */
|
877 |
if (n == 15) |
878 |
tmp &= ~1;
|
879 |
|
880 |
if (n < 16) { |
881 |
/* Core integer register. */
|
882 |
env->regs[n] = tmp; |
883 |
return 4; |
884 |
} |
885 |
if (n < 24) { /* 16-23 */ |
886 |
/* FPA registers (ignored). */
|
887 |
if (gdb_has_xml)
|
888 |
return 0; |
889 |
return 12; |
890 |
} |
891 |
switch (n) {
|
892 |
case 24: |
893 |
/* FPA status register (ignored). */
|
894 |
if (gdb_has_xml)
|
895 |
return 0; |
896 |
return 4; |
897 |
case 25: |
898 |
/* CPSR */
|
899 |
cpsr_write (env, tmp, 0xffffffff);
|
900 |
return 4; |
901 |
} |
902 |
/* Unknown register. */
|
903 |
return 0; |
904 |
} |
905 |
|
906 |
#elif defined (TARGET_M68K)
|
907 |
|
908 |
#define NUM_CORE_REGS 18 |
909 |
|
910 |
#define GDB_CORE_XML "cf-core.xml" |
911 |
|
912 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
913 |
{ |
914 |
if (n < 8) { |
915 |
/* D0-D7 */
|
916 |
GET_REG32(env->dregs[n]); |
917 |
} else if (n < 16) { |
918 |
/* A0-A7 */
|
919 |
GET_REG32(env->aregs[n - 8]);
|
920 |
} else {
|
921 |
switch (n) {
|
922 |
case 16: GET_REG32(env->sr); |
923 |
case 17: GET_REG32(env->pc); |
924 |
} |
925 |
} |
926 |
/* FP registers not included here because they vary between
|
927 |
ColdFire and m68k. Use XML bits for these. */
|
928 |
return 0; |
929 |
} |
930 |
|
931 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
932 |
{ |
933 |
uint32_t tmp; |
934 |
|
935 |
tmp = ldl_p(mem_buf); |
936 |
|
937 |
if (n < 8) { |
938 |
/* D0-D7 */
|
939 |
env->dregs[n] = tmp; |
940 |
} else if (n < 8) { |
941 |
/* A0-A7 */
|
942 |
env->aregs[n - 8] = tmp;
|
943 |
} else {
|
944 |
switch (n) {
|
945 |
case 16: env->sr = tmp; break; |
946 |
case 17: env->pc = tmp; break; |
947 |
default: return 0; |
948 |
} |
949 |
} |
950 |
return 4; |
951 |
} |
952 |
#elif defined (TARGET_MIPS)
|
953 |
|
954 |
#define NUM_CORE_REGS 73 |
955 |
|
956 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
957 |
{ |
958 |
if (n < 32) { |
959 |
GET_REGL(env->active_tc.gpr[n]); |
960 |
} |
961 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) { |
962 |
if (n >= 38 && n < 70) { |
963 |
if (env->CP0_Status & (1 << CP0St_FR)) |
964 |
GET_REGL(env->active_fpu.fpr[n - 38].d);
|
965 |
else
|
966 |
GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
|
967 |
} |
968 |
switch (n) {
|
969 |
case 70: GET_REGL((int32_t)env->active_fpu.fcr31); |
970 |
case 71: GET_REGL((int32_t)env->active_fpu.fcr0); |
971 |
} |
972 |
} |
973 |
switch (n) {
|
974 |
case 32: GET_REGL((int32_t)env->CP0_Status); |
975 |
case 33: GET_REGL(env->active_tc.LO[0]); |
976 |
case 34: GET_REGL(env->active_tc.HI[0]); |
977 |
case 35: GET_REGL(env->CP0_BadVAddr); |
978 |
case 36: GET_REGL((int32_t)env->CP0_Cause); |
979 |
case 37: GET_REGL(env->active_tc.PC); |
980 |
case 72: GET_REGL(0); /* fp */ |
981 |
case 89: GET_REGL((int32_t)env->CP0_PRid); |
982 |
} |
983 |
if (n >= 73 && n <= 88) { |
984 |
/* 16 embedded regs. */
|
985 |
GET_REGL(0);
|
986 |
} |
987 |
|
988 |
return 0; |
989 |
} |
990 |
|
991 |
/* convert MIPS rounding mode in FCR31 to IEEE library */
|
992 |
static unsigned int ieee_rm[] = |
993 |
{ |
994 |
float_round_nearest_even, |
995 |
float_round_to_zero, |
996 |
float_round_up, |
997 |
float_round_down |
998 |
}; |
999 |
#define RESTORE_ROUNDING_MODE \
|
1000 |
set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
|
1001 |
|
1002 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
1003 |
{ |
1004 |
target_ulong tmp; |
1005 |
|
1006 |
tmp = ldtul_p(mem_buf); |
1007 |
|
1008 |
if (n < 32) { |
1009 |
env->active_tc.gpr[n] = tmp; |
1010 |
return sizeof(target_ulong); |
1011 |
} |
1012 |
if (env->CP0_Config1 & (1 << CP0C1_FP) |
1013 |
&& n >= 38 && n < 73) { |
1014 |
if (n < 70) { |
1015 |
if (env->CP0_Status & (1 << CP0St_FR)) |
1016 |
env->active_fpu.fpr[n - 38].d = tmp;
|
1017 |
else
|
1018 |
env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
|
1019 |
} |
1020 |
switch (n) {
|
1021 |
case 70: |
1022 |
env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
|
1023 |
/* set rounding mode */
|
1024 |
RESTORE_ROUNDING_MODE; |
1025 |
#ifndef CONFIG_SOFTFLOAT
|
1026 |
/* no floating point exception for native float */
|
1027 |
SET_FP_ENABLE(env->active_fpu.fcr31, 0);
|
1028 |
#endif
|
1029 |
break;
|
1030 |
case 71: env->active_fpu.fcr0 = tmp; break; |
1031 |
} |
1032 |
return sizeof(target_ulong); |
1033 |
} |
1034 |
switch (n) {
|
1035 |
case 32: env->CP0_Status = tmp; break; |
1036 |
case 33: env->active_tc.LO[0] = tmp; break; |
1037 |
case 34: env->active_tc.HI[0] = tmp; break; |
1038 |
case 35: env->CP0_BadVAddr = tmp; break; |
1039 |
case 36: env->CP0_Cause = tmp; break; |
1040 |
case 37: env->active_tc.PC = tmp; break; |
1041 |
case 72: /* fp, ignored */ break; |
1042 |
default:
|
1043 |
if (n > 89) |
1044 |
return 0; |
1045 |
/* Other registers are readonly. Ignore writes. */
|
1046 |
break;
|
1047 |
} |
1048 |
|
1049 |
return sizeof(target_ulong); |
1050 |
} |
1051 |
#elif defined (TARGET_SH4)
|
1052 |
|
1053 |
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
|
1054 |
/* FIXME: We should use XML for this. */
|
1055 |
|
1056 |
#define NUM_CORE_REGS 59 |
1057 |
|
1058 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
1059 |
{ |
1060 |
if (n < 8) { |
1061 |
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
|
1062 |
GET_REGL(env->gregs[n + 16]);
|
1063 |
} else {
|
1064 |
GET_REGL(env->gregs[n]); |
1065 |
} |
1066 |
} else if (n < 16) { |
1067 |
GET_REGL(env->gregs[n - 8]);
|
1068 |
} else if (n >= 25 && n < 41) { |
1069 |
GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]); |
1070 |
} else if (n >= 43 && n < 51) { |
1071 |
GET_REGL(env->gregs[n - 43]);
|
1072 |
} else if (n >= 51 && n < 59) { |
1073 |
GET_REGL(env->gregs[n - (51 - 16)]); |
1074 |
} |
1075 |
switch (n) {
|
1076 |
case 16: GET_REGL(env->pc); |
1077 |
case 17: GET_REGL(env->pr); |
1078 |
case 18: GET_REGL(env->gbr); |
1079 |
case 19: GET_REGL(env->vbr); |
1080 |
case 20: GET_REGL(env->mach); |
1081 |
case 21: GET_REGL(env->macl); |
1082 |
case 22: GET_REGL(env->sr); |
1083 |
case 23: GET_REGL(env->fpul); |
1084 |
case 24: GET_REGL(env->fpscr); |
1085 |
case 41: GET_REGL(env->ssr); |
1086 |
case 42: GET_REGL(env->spc); |
1087 |
} |
1088 |
|
1089 |
return 0; |
1090 |
} |
1091 |
|
1092 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
1093 |
{ |
1094 |
uint32_t tmp; |
1095 |
|
1096 |
tmp = ldl_p(mem_buf); |
1097 |
|
1098 |
if (n < 8) { |
1099 |
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
|
1100 |
env->gregs[n + 16] = tmp;
|
1101 |
} else {
|
1102 |
env->gregs[n] = tmp; |
1103 |
} |
1104 |
return 4; |
1105 |
} else if (n < 16) { |
1106 |
env->gregs[n - 8] = tmp;
|
1107 |
return 4; |
1108 |
} else if (n >= 25 && n < 41) { |
1109 |
env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp; |
1110 |
} else if (n >= 43 && n < 51) { |
1111 |
env->gregs[n - 43] = tmp;
|
1112 |
return 4; |
1113 |
} else if (n >= 51 && n < 59) { |
1114 |
env->gregs[n - (51 - 16)] = tmp; |
1115 |
return 4; |
1116 |
} |
1117 |
switch (n) {
|
1118 |
case 16: env->pc = tmp; |
1119 |
case 17: env->pr = tmp; |
1120 |
case 18: env->gbr = tmp; |
1121 |
case 19: env->vbr = tmp; |
1122 |
case 20: env->mach = tmp; |
1123 |
case 21: env->macl = tmp; |
1124 |
case 22: env->sr = tmp; |
1125 |
case 23: env->fpul = tmp; |
1126 |
case 24: env->fpscr = tmp; |
1127 |
case 41: env->ssr = tmp; |
1128 |
case 42: env->spc = tmp; |
1129 |
default: return 0; |
1130 |
} |
1131 |
|
1132 |
return 4; |
1133 |
} |
1134 |
#elif defined (TARGET_CRIS)
|
1135 |
|
1136 |
#define NUM_CORE_REGS 49 |
1137 |
|
1138 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
1139 |
{ |
1140 |
uint8_t srs; |
1141 |
|
1142 |
srs = env->pregs[PR_SRS]; |
1143 |
if (n < 16) { |
1144 |
GET_REG32(env->regs[n]); |
1145 |
} |
1146 |
|
1147 |
if (n >= 21 && n < 32) { |
1148 |
GET_REG32(env->pregs[n - 16]);
|
1149 |
} |
1150 |
if (n >= 33 && n < 49) { |
1151 |
GET_REG32(env->sregs[srs][n - 33]);
|
1152 |
} |
1153 |
switch (n) {
|
1154 |
case 16: GET_REG8(env->pregs[0]); |
1155 |
case 17: GET_REG8(env->pregs[1]); |
1156 |
case 18: GET_REG32(env->pregs[2]); |
1157 |
case 19: GET_REG8(srs); |
1158 |
case 20: GET_REG16(env->pregs[4]); |
1159 |
case 32: GET_REG32(env->pc); |
1160 |
} |
1161 |
|
1162 |
return 0; |
1163 |
} |
1164 |
|
1165 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
1166 |
{ |
1167 |
uint32_t tmp; |
1168 |
|
1169 |
if (n > 49) |
1170 |
return 0; |
1171 |
|
1172 |
tmp = ldl_p(mem_buf); |
1173 |
|
1174 |
if (n < 16) { |
1175 |
env->regs[n] = tmp; |
1176 |
} |
1177 |
|
1178 |
if (n >= 21 && n < 32) { |
1179 |
env->pregs[n - 16] = tmp;
|
1180 |
} |
1181 |
|
1182 |
/* FIXME: Should support function regs be writable? */
|
1183 |
switch (n) {
|
1184 |
case 16: return 1; |
1185 |
case 17: return 1; |
1186 |
case 18: env->pregs[PR_PID] = tmp; break; |
1187 |
case 19: return 1; |
1188 |
case 20: return 2; |
1189 |
case 32: env->pc = tmp; break; |
1190 |
} |
1191 |
|
1192 |
return 4; |
1193 |
} |
1194 |
#elif defined (TARGET_ALPHA)
|
1195 |
|
1196 |
#define NUM_CORE_REGS 65 |
1197 |
|
1198 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
1199 |
{ |
1200 |
if (n < 31) { |
1201 |
GET_REGL(env->ir[n]); |
1202 |
} |
1203 |
else if (n == 31) { |
1204 |
GET_REGL(0);
|
1205 |
} |
1206 |
else if (n<63) { |
1207 |
uint64_t val; |
1208 |
|
1209 |
val=*((uint64_t *)&env->fir[n-32]);
|
1210 |
GET_REGL(val); |
1211 |
} |
1212 |
else if (n==63) { |
1213 |
GET_REGL(env->fpcr); |
1214 |
} |
1215 |
else if (n==64) { |
1216 |
GET_REGL(env->pc); |
1217 |
} |
1218 |
else {
|
1219 |
GET_REGL(0);
|
1220 |
} |
1221 |
|
1222 |
return 0; |
1223 |
} |
1224 |
|
1225 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
1226 |
{ |
1227 |
target_ulong tmp; |
1228 |
tmp = ldtul_p(mem_buf); |
1229 |
|
1230 |
if (n < 31) { |
1231 |
env->ir[n] = tmp; |
1232 |
} |
1233 |
|
1234 |
if (n > 31 && n < 63) { |
1235 |
env->fir[n - 32] = ldfl_p(mem_buf);
|
1236 |
} |
1237 |
|
1238 |
if (n == 64 ) { |
1239 |
env->pc=tmp; |
1240 |
} |
1241 |
|
1242 |
return 8; |
1243 |
} |
1244 |
#else
|
1245 |
|
1246 |
#define NUM_CORE_REGS 0 |
1247 |
|
1248 |
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) |
1249 |
{ |
1250 |
return 0; |
1251 |
} |
1252 |
|
1253 |
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) |
1254 |
{ |
1255 |
return 0; |
1256 |
} |
1257 |
|
1258 |
#endif
|
1259 |
|
1260 |
static int num_g_regs = NUM_CORE_REGS; |
1261 |
|
1262 |
#ifdef GDB_CORE_XML
|
1263 |
/* Encode data using the encoding for 'x' packets. */
|
1264 |
static int memtox(char *buf, const char *mem, int len) |
1265 |
{ |
1266 |
char *p = buf;
|
1267 |
char c;
|
1268 |
|
1269 |
while (len--) {
|
1270 |
c = *(mem++); |
1271 |
switch (c) {
|
1272 |
case '#': case '$': case '*': case '}': |
1273 |
*(p++) = '}';
|
1274 |
*(p++) = c ^ 0x20;
|
1275 |
break;
|
1276 |
default:
|
1277 |
*(p++) = c; |
1278 |
break;
|
1279 |
} |
1280 |
} |
1281 |
return p - buf;
|
1282 |
} |
1283 |
|
1284 |
static const char *get_feature_xml(const char *p, const char **newp) |
1285 |
{ |
1286 |
extern const char *const xml_builtin[][2]; |
1287 |
size_t len; |
1288 |
int i;
|
1289 |
const char *name; |
1290 |
static char target_xml[1024]; |
1291 |
|
1292 |
len = 0;
|
1293 |
while (p[len] && p[len] != ':') |
1294 |
len++; |
1295 |
*newp = p + len; |
1296 |
|
1297 |
name = NULL;
|
1298 |
if (strncmp(p, "target.xml", len) == 0) { |
1299 |
/* Generate the XML description for this CPU. */
|
1300 |
if (!target_xml[0]) { |
1301 |
GDBRegisterState *r; |
1302 |
|
1303 |
snprintf(target_xml, sizeof(target_xml),
|
1304 |
"<?xml version=\"1.0\"?>"
|
1305 |
"<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
|
1306 |
"<target>"
|
1307 |
"<xi:include href=\"%s\"/>",
|
1308 |
GDB_CORE_XML); |
1309 |
|
1310 |
for (r = first_cpu->gdb_regs; r; r = r->next) {
|
1311 |
strcat(target_xml, "<xi:include href=\"");
|
1312 |
strcat(target_xml, r->xml); |
1313 |
strcat(target_xml, "\"/>");
|
1314 |
} |
1315 |
strcat(target_xml, "</target>");
|
1316 |
} |
1317 |
return target_xml;
|
1318 |
} |
1319 |
for (i = 0; ; i++) { |
1320 |
name = xml_builtin[i][0];
|
1321 |
if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len)) |
1322 |
break;
|
1323 |
} |
1324 |
return name ? xml_builtin[i][1] : NULL; |
1325 |
} |
1326 |
#endif
|
1327 |
|
1328 |
static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg) |
1329 |
{ |
1330 |
GDBRegisterState *r; |
1331 |
|
1332 |
if (reg < NUM_CORE_REGS)
|
1333 |
return cpu_gdb_read_register(env, mem_buf, reg);
|
1334 |
|
1335 |
for (r = env->gdb_regs; r; r = r->next) {
|
1336 |
if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
|
1337 |
return r->get_reg(env, mem_buf, reg - r->base_reg);
|
1338 |
} |
1339 |
} |
1340 |
return 0; |
1341 |
} |
1342 |
|
1343 |
static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg) |
1344 |
{ |
1345 |
GDBRegisterState *r; |
1346 |
|
1347 |
if (reg < NUM_CORE_REGS)
|
1348 |
return cpu_gdb_write_register(env, mem_buf, reg);
|
1349 |
|
1350 |
for (r = env->gdb_regs; r; r = r->next) {
|
1351 |
if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
|
1352 |
return r->set_reg(env, mem_buf, reg - r->base_reg);
|
1353 |
} |
1354 |
} |
1355 |
return 0; |
1356 |
} |
1357 |
|
1358 |
/* Register a supplemental set of CPU registers. If g_pos is nonzero it
|
1359 |
specifies the first register number and these registers are included in
|
1360 |
a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
|
1361 |
gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
|
1362 |
*/
|
1363 |
|
1364 |
void gdb_register_coprocessor(CPUState * env,
|
1365 |
gdb_reg_cb get_reg, gdb_reg_cb set_reg, |
1366 |
int num_regs, const char *xml, int g_pos) |
1367 |
{ |
1368 |
GDBRegisterState *s; |
1369 |
GDBRegisterState **p; |
1370 |
static int last_reg = NUM_CORE_REGS; |
1371 |
|
1372 |
s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
|
1373 |
s->base_reg = last_reg; |
1374 |
s->num_regs = num_regs; |
1375 |
s->get_reg = get_reg; |
1376 |
s->set_reg = set_reg; |
1377 |
s->xml = xml; |
1378 |
p = &env->gdb_regs; |
1379 |
while (*p) {
|
1380 |
/* Check for duplicates. */
|
1381 |
if (strcmp((*p)->xml, xml) == 0) |
1382 |
return;
|
1383 |
p = &(*p)->next; |
1384 |
} |
1385 |
/* Add to end of list. */
|
1386 |
last_reg += num_regs; |
1387 |
*p = s; |
1388 |
if (g_pos) {
|
1389 |
if (g_pos != s->base_reg) {
|
1390 |
fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
|
1391 |
"Expected %d got %d\n", xml, g_pos, s->base_reg);
|
1392 |
} else {
|
1393 |
num_g_regs = last_reg; |
1394 |
} |
1395 |
} |
1396 |
} |
1397 |
|
1398 |
/* GDB breakpoint/watchpoint types */
|
1399 |
#define GDB_BREAKPOINT_SW 0 |
1400 |
#define GDB_BREAKPOINT_HW 1 |
1401 |
#define GDB_WATCHPOINT_WRITE 2 |
1402 |
#define GDB_WATCHPOINT_READ 3 |
1403 |
#define GDB_WATCHPOINT_ACCESS 4 |
1404 |
|
1405 |
#ifndef CONFIG_USER_ONLY
|
1406 |
static const int xlat_gdb_type[] = { |
1407 |
[GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE, |
1408 |
[GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ, |
1409 |
[GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS, |
1410 |
}; |
1411 |
#endif
|
1412 |
|
1413 |
static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type) |
1414 |
{ |
1415 |
CPUState *env; |
1416 |
int err = 0; |
1417 |
|
1418 |
switch (type) {
|
1419 |
case GDB_BREAKPOINT_SW:
|
1420 |
case GDB_BREAKPOINT_HW:
|
1421 |
for (env = first_cpu; env != NULL; env = env->next_cpu) { |
1422 |
err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
|
1423 |
if (err)
|
1424 |
break;
|
1425 |
} |
1426 |
return err;
|
1427 |
#ifndef CONFIG_USER_ONLY
|
1428 |
case GDB_WATCHPOINT_WRITE:
|
1429 |
case GDB_WATCHPOINT_READ:
|
1430 |
case GDB_WATCHPOINT_ACCESS:
|
1431 |
for (env = first_cpu; env != NULL; env = env->next_cpu) { |
1432 |
err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type], |
1433 |
NULL);
|
1434 |
if (err)
|
1435 |
break;
|
1436 |
} |
1437 |
return err;
|
1438 |
#endif
|
1439 |
default:
|
1440 |
return -ENOSYS;
|
1441 |
} |
1442 |
} |
1443 |
|
1444 |
static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type) |
1445 |
{ |
1446 |
CPUState *env; |
1447 |
int err = 0; |
1448 |
|
1449 |
switch (type) {
|
1450 |
case GDB_BREAKPOINT_SW:
|
1451 |
case GDB_BREAKPOINT_HW:
|
1452 |
for (env = first_cpu; env != NULL; env = env->next_cpu) { |
1453 |
err = cpu_breakpoint_remove(env, addr, BP_GDB); |
1454 |
if (err)
|
1455 |
break;
|
1456 |
} |
1457 |
return err;
|
1458 |
#ifndef CONFIG_USER_ONLY
|
1459 |
case GDB_WATCHPOINT_WRITE:
|
1460 |
case GDB_WATCHPOINT_READ:
|
1461 |
case GDB_WATCHPOINT_ACCESS:
|
1462 |
for (env = first_cpu; env != NULL; env = env->next_cpu) { |
1463 |
err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]); |
1464 |
if (err)
|
1465 |
break;
|
1466 |
} |
1467 |
return err;
|
1468 |
#endif
|
1469 |
default:
|
1470 |
return -ENOSYS;
|
1471 |
} |
1472 |
} |
1473 |
|
1474 |
static void gdb_breakpoint_remove_all(void) |
1475 |
{ |
1476 |
CPUState *env; |
1477 |
|
1478 |
for (env = first_cpu; env != NULL; env = env->next_cpu) { |
1479 |
cpu_breakpoint_remove_all(env, BP_GDB); |
1480 |
#ifndef CONFIG_USER_ONLY
|
1481 |
cpu_watchpoint_remove_all(env, BP_GDB); |
1482 |
#endif
|
1483 |
} |
1484 |
} |
1485 |
|
1486 |
static int gdb_handle_packet(GDBState *s, const char *line_buf) |
1487 |
{ |
1488 |
CPUState *env; |
1489 |
const char *p; |
1490 |
int ch, reg_size, type, res, thread;
|
1491 |
char buf[MAX_PACKET_LENGTH];
|
1492 |
uint8_t mem_buf[MAX_PACKET_LENGTH]; |
1493 |
uint8_t *registers; |
1494 |
target_ulong addr, len; |
1495 |
|
1496 |
#ifdef DEBUG_GDB
|
1497 |
printf("command='%s'\n", line_buf);
|
1498 |
#endif
|
1499 |
p = line_buf; |
1500 |
ch = *p++; |
1501 |
switch(ch) {
|
1502 |
case '?': |
1503 |
/* TODO: Make this return the correct value for user-mode. */
|
1504 |
snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP, |
1505 |
s->c_cpu->cpu_index+1);
|
1506 |
put_packet(s, buf); |
1507 |
/* Remove all the breakpoints when this query is issued,
|
1508 |
* because gdb is doing and initial connect and the state
|
1509 |
* should be cleaned up.
|
1510 |
*/
|
1511 |
gdb_breakpoint_remove_all(); |
1512 |
break;
|
1513 |
case 'c': |
1514 |
if (*p != '\0') { |
1515 |
addr = strtoull(p, (char **)&p, 16); |
1516 |
#if defined(TARGET_I386)
|
1517 |
s->c_cpu->eip = addr; |
1518 |
#elif defined (TARGET_PPC)
|
1519 |
s->c_cpu->nip = addr; |
1520 |
#elif defined (TARGET_SPARC)
|
1521 |
s->c_cpu->pc = addr; |
1522 |
s->c_cpu->npc = addr + 4;
|
1523 |
#elif defined (TARGET_ARM)
|
1524 |
s->c_cpu->regs[15] = addr;
|
1525 |
#elif defined (TARGET_SH4)
|
1526 |
s->c_cpu->pc = addr; |
1527 |
#elif defined (TARGET_MIPS)
|
1528 |
s->c_cpu->active_tc.PC = addr; |
1529 |
#elif defined (TARGET_CRIS)
|
1530 |
s->c_cpu->pc = addr; |
1531 |
#elif defined (TARGET_ALPHA)
|
1532 |
s->c_cpu->pc = addr; |
1533 |
#endif
|
1534 |
} |
1535 |
s->signal = 0;
|
1536 |
gdb_continue(s); |
1537 |
return RS_IDLE;
|
1538 |
case 'C': |
1539 |
s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16)); |
1540 |
if (s->signal == -1) |
1541 |
s->signal = 0;
|
1542 |
gdb_continue(s); |
1543 |
return RS_IDLE;
|
1544 |
case 'k': |
1545 |
/* Kill the target */
|
1546 |
fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
|
1547 |
exit(0);
|
1548 |
case 'D': |
1549 |
/* Detach packet */
|
1550 |
gdb_breakpoint_remove_all(); |
1551 |
gdb_continue(s); |
1552 |
put_packet(s, "OK");
|
1553 |
break;
|
1554 |
case 's': |
1555 |
if (*p != '\0') { |
1556 |
addr = strtoull(p, (char **)&p, 16); |
1557 |
#if defined(TARGET_I386)
|
1558 |
s->c_cpu->eip = addr; |
1559 |
#elif defined (TARGET_PPC)
|
1560 |
s->c_cpu->nip = addr; |
1561 |
#elif defined (TARGET_SPARC)
|
1562 |
s->c_cpu->pc = addr; |
1563 |
s->c_cpu->npc = addr + 4;
|
1564 |
#elif defined (TARGET_ARM)
|
1565 |
s->c_cpu->regs[15] = addr;
|
1566 |
#elif defined (TARGET_SH4)
|
1567 |
s->c_cpu->pc = addr; |
1568 |
#elif defined (TARGET_MIPS)
|
1569 |
s->c_cpu->active_tc.PC = addr; |
1570 |
#elif defined (TARGET_CRIS)
|
1571 |
s->c_cpu->pc = addr; |
1572 |
#elif defined (TARGET_ALPHA)
|
1573 |
s->c_cpu->pc = addr; |
1574 |
#endif
|
1575 |
} |
1576 |
cpu_single_step(s->c_cpu, sstep_flags); |
1577 |
gdb_continue(s); |
1578 |
return RS_IDLE;
|
1579 |
case 'F': |
1580 |
{ |
1581 |
target_ulong ret; |
1582 |
target_ulong err; |
1583 |
|
1584 |
ret = strtoull(p, (char **)&p, 16); |
1585 |
if (*p == ',') { |
1586 |
p++; |
1587 |
err = strtoull(p, (char **)&p, 16); |
1588 |
} else {
|
1589 |
err = 0;
|
1590 |
} |
1591 |
if (*p == ',') |
1592 |
p++; |
1593 |
type = *p; |
1594 |
if (gdb_current_syscall_cb)
|
1595 |
gdb_current_syscall_cb(s->c_cpu, ret, err); |
1596 |
if (type == 'C') { |
1597 |
put_packet(s, "T02");
|
1598 |
} else {
|
1599 |
gdb_continue(s); |
1600 |
} |
1601 |
} |
1602 |
break;
|
1603 |
case 'g': |
1604 |
len = 0;
|
1605 |
for (addr = 0; addr < num_g_regs; addr++) { |
1606 |
reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr); |
1607 |
len += reg_size; |
1608 |
} |
1609 |
memtohex(buf, mem_buf, len); |
1610 |
put_packet(s, buf); |
1611 |
break;
|
1612 |
case 'G': |
1613 |
registers = mem_buf; |
1614 |
len = strlen(p) / 2;
|
1615 |
hextomem((uint8_t *)registers, p, len); |
1616 |
for (addr = 0; addr < num_g_regs && len > 0; addr++) { |
1617 |
reg_size = gdb_write_register(s->g_cpu, registers, addr); |
1618 |
len -= reg_size; |
1619 |
registers += reg_size; |
1620 |
} |
1621 |
put_packet(s, "OK");
|
1622 |
break;
|
1623 |
case 'm': |
1624 |
addr = strtoull(p, (char **)&p, 16); |
1625 |
if (*p == ',') |
1626 |
p++; |
1627 |
len = strtoull(p, NULL, 16); |
1628 |
if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) { |
1629 |
put_packet (s, "E14");
|
1630 |
} else {
|
1631 |
memtohex(buf, mem_buf, len); |
1632 |
put_packet(s, buf); |
1633 |
} |
1634 |
break;
|
1635 |
case 'M': |
1636 |
addr = strtoull(p, (char **)&p, 16); |
1637 |
if (*p == ',') |
1638 |
p++; |
1639 |
len = strtoull(p, (char **)&p, 16); |
1640 |
if (*p == ':') |
1641 |
p++; |
1642 |
hextomem(mem_buf, p, len); |
1643 |
if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0) |
1644 |
put_packet(s, "E14");
|
1645 |
else
|
1646 |
put_packet(s, "OK");
|
1647 |
break;
|
1648 |
case 'p': |
1649 |
/* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
|
1650 |
This works, but can be very slow. Anything new enough to
|
1651 |
understand XML also knows how to use this properly. */
|
1652 |
if (!gdb_has_xml)
|
1653 |
goto unknown_command;
|
1654 |
addr = strtoull(p, (char **)&p, 16); |
1655 |
reg_size = gdb_read_register(s->g_cpu, mem_buf, addr); |
1656 |
if (reg_size) {
|
1657 |
memtohex(buf, mem_buf, reg_size); |
1658 |
put_packet(s, buf); |
1659 |
} else {
|
1660 |
put_packet(s, "E14");
|
1661 |
} |
1662 |
break;
|
1663 |
case 'P': |
1664 |
if (!gdb_has_xml)
|
1665 |
goto unknown_command;
|
1666 |
addr = strtoull(p, (char **)&p, 16); |
1667 |
if (*p == '=') |
1668 |
p++; |
1669 |
reg_size = strlen(p) / 2;
|
1670 |
hextomem(mem_buf, p, reg_size); |
1671 |
gdb_write_register(s->g_cpu, mem_buf, addr); |
1672 |
put_packet(s, "OK");
|
1673 |
break;
|
1674 |
case 'Z': |
1675 |
case 'z': |
1676 |
type = strtoul(p, (char **)&p, 16); |
1677 |
if (*p == ',') |
1678 |
p++; |
1679 |
addr = strtoull(p, (char **)&p, 16); |
1680 |
if (*p == ',') |
1681 |
p++; |
1682 |
len = strtoull(p, (char **)&p, 16); |
1683 |
if (ch == 'Z') |
1684 |
res = gdb_breakpoint_insert(addr, len, type); |
1685 |
else
|
1686 |
res = gdb_breakpoint_remove(addr, len, type); |
1687 |
if (res >= 0) |
1688 |
put_packet(s, "OK");
|
1689 |
else if (res == -ENOSYS) |
1690 |
put_packet(s, "");
|
1691 |
else
|
1692 |
put_packet(s, "E22");
|
1693 |
break;
|
1694 |
case 'H': |
1695 |
type = *p++; |
1696 |
thread = strtoull(p, (char **)&p, 16); |
1697 |
if (thread == -1 || thread == 0) { |
1698 |
put_packet(s, "OK");
|
1699 |
break;
|
1700 |
} |
1701 |
for (env = first_cpu; env != NULL; env = env->next_cpu) |
1702 |
if (env->cpu_index + 1 == thread) |
1703 |
break;
|
1704 |
if (env == NULL) { |
1705 |
put_packet(s, "E22");
|
1706 |
break;
|
1707 |
} |
1708 |
switch (type) {
|
1709 |
case 'c': |
1710 |
s->c_cpu = env; |
1711 |
put_packet(s, "OK");
|
1712 |
break;
|
1713 |
case 'g': |
1714 |
s->g_cpu = env; |
1715 |
put_packet(s, "OK");
|
1716 |
break;
|
1717 |
default:
|
1718 |
put_packet(s, "E22");
|
1719 |
break;
|
1720 |
} |
1721 |
break;
|
1722 |
case 'T': |
1723 |
thread = strtoull(p, (char **)&p, 16); |
1724 |
#ifndef CONFIG_USER_ONLY
|
1725 |
if (thread > 0 && thread < smp_cpus + 1) |
1726 |
#else
|
1727 |
if (thread == 1) |
1728 |
#endif
|
1729 |
put_packet(s, "OK");
|
1730 |
else
|
1731 |
put_packet(s, "E22");
|
1732 |
break;
|
1733 |
case 'q': |
1734 |
case 'Q': |
1735 |
/* parse any 'q' packets here */
|
1736 |
if (!strcmp(p,"qemu.sstepbits")) { |
1737 |
/* Query Breakpoint bit definitions */
|
1738 |
snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x", |
1739 |
SSTEP_ENABLE, |
1740 |
SSTEP_NOIRQ, |
1741 |
SSTEP_NOTIMER); |
1742 |
put_packet(s, buf); |
1743 |
break;
|
1744 |
} else if (strncmp(p,"qemu.sstep",10) == 0) { |
1745 |
/* Display or change the sstep_flags */
|
1746 |
p += 10;
|
1747 |
if (*p != '=') { |
1748 |
/* Display current setting */
|
1749 |
snprintf(buf, sizeof(buf), "0x%x", sstep_flags); |
1750 |
put_packet(s, buf); |
1751 |
break;
|
1752 |
} |
1753 |
p++; |
1754 |
type = strtoul(p, (char **)&p, 16); |
1755 |
sstep_flags = type; |
1756 |
put_packet(s, "OK");
|
1757 |
break;
|
1758 |
} else if (strcmp(p,"C") == 0) { |
1759 |
/* "Current thread" remains vague in the spec, so always return
|
1760 |
* the first CPU (gdb returns the first thread). */
|
1761 |
put_packet(s, "QC1");
|
1762 |
break;
|
1763 |
} else if (strcmp(p,"fThreadInfo") == 0) { |
1764 |
s->query_cpu = first_cpu; |
1765 |
goto report_cpuinfo;
|
1766 |
} else if (strcmp(p,"sThreadInfo") == 0) { |
1767 |
report_cpuinfo:
|
1768 |
if (s->query_cpu) {
|
1769 |
snprintf(buf, sizeof(buf), "m%x", s->query_cpu->cpu_index+1); |
1770 |
put_packet(s, buf); |
1771 |
s->query_cpu = s->query_cpu->next_cpu; |
1772 |
} else
|
1773 |
put_packet(s, "l");
|
1774 |
break;
|
1775 |
} else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) { |
1776 |
thread = strtoull(p+16, (char **)&p, 16); |
1777 |
for (env = first_cpu; env != NULL; env = env->next_cpu) |
1778 |
if (env->cpu_index + 1 == thread) { |
1779 |
len = snprintf((char *)mem_buf, sizeof(mem_buf), |
1780 |
"CPU#%d [%s]", env->cpu_index,
|
1781 |
env->halted ? "halted " : "running"); |
1782 |
memtohex(buf, mem_buf, len); |
1783 |
put_packet(s, buf); |
1784 |
break;
|
1785 |
} |
1786 |
break;
|
1787 |
} |
1788 |
#ifdef CONFIG_LINUX_USER
|
1789 |
else if (strncmp(p, "Offsets", 7) == 0) { |
1790 |
TaskState *ts = s->c_cpu->opaque; |
1791 |
|
1792 |
snprintf(buf, sizeof(buf),
|
1793 |
"Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx |
1794 |
";Bss=" TARGET_ABI_FMT_lx,
|
1795 |
ts->info->code_offset, |
1796 |
ts->info->data_offset, |
1797 |
ts->info->data_offset); |
1798 |
put_packet(s, buf); |
1799 |
break;
|
1800 |
} |
1801 |
#endif
|
1802 |
if (strncmp(p, "Supported", 9) == 0) { |
1803 |
snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH); |
1804 |
#ifdef GDB_CORE_XML
|
1805 |
strcat(buf, ";qXfer:features:read+");
|
1806 |
#endif
|
1807 |
put_packet(s, buf); |
1808 |
break;
|
1809 |
} |
1810 |
#ifdef GDB_CORE_XML
|
1811 |
if (strncmp(p, "Xfer:features:read:", 19) == 0) { |
1812 |
const char *xml; |
1813 |
target_ulong total_len; |
1814 |
|
1815 |
gdb_has_xml = 1;
|
1816 |
p += 19;
|
1817 |
xml = get_feature_xml(p, &p); |
1818 |
if (!xml) {
|
1819 |
snprintf(buf, sizeof(buf), "E00"); |
1820 |
put_packet(s, buf); |
1821 |
break;
|
1822 |
} |
1823 |
|
1824 |
if (*p == ':') |
1825 |
p++; |
1826 |
addr = strtoul(p, (char **)&p, 16); |
1827 |
if (*p == ',') |
1828 |
p++; |
1829 |
len = strtoul(p, (char **)&p, 16); |
1830 |
|
1831 |
total_len = strlen(xml); |
1832 |
if (addr > total_len) {
|
1833 |
snprintf(buf, sizeof(buf), "E00"); |
1834 |
put_packet(s, buf); |
1835 |
break;
|
1836 |
} |
1837 |
if (len > (MAX_PACKET_LENGTH - 5) / 2) |
1838 |
len = (MAX_PACKET_LENGTH - 5) / 2; |
1839 |
if (len < total_len - addr) {
|
1840 |
buf[0] = 'm'; |
1841 |
len = memtox(buf + 1, xml + addr, len);
|
1842 |
} else {
|
1843 |
buf[0] = 'l'; |
1844 |
len = memtox(buf + 1, xml + addr, total_len - addr);
|
1845 |
} |
1846 |
put_packet_binary(s, buf, len + 1);
|
1847 |
break;
|
1848 |
} |
1849 |
#endif
|
1850 |
/* Unrecognised 'q' command. */
|
1851 |
goto unknown_command;
|
1852 |
|
1853 |
default:
|
1854 |
unknown_command:
|
1855 |
/* put empty packet */
|
1856 |
buf[0] = '\0'; |
1857 |
put_packet(s, buf); |
1858 |
break;
|
1859 |
} |
1860 |
return RS_IDLE;
|
1861 |
} |
1862 |
|
1863 |
void gdb_set_stop_cpu(CPUState *env)
|
1864 |
{ |
1865 |
gdbserver_state->c_cpu = env; |
1866 |
gdbserver_state->g_cpu = env; |
1867 |
} |
1868 |
|
1869 |
#ifndef CONFIG_USER_ONLY
|
1870 |
static void gdb_vm_stopped(void *opaque, int reason) |
1871 |
{ |
1872 |
GDBState *s = gdbserver_state; |
1873 |
CPUState *env = s->c_cpu; |
1874 |
char buf[256]; |
1875 |
const char *type; |
1876 |
int ret;
|
1877 |
|
1878 |
if (s->state == RS_SYSCALL)
|
1879 |
return;
|
1880 |
|
1881 |
/* disable single step if it was enable */
|
1882 |
cpu_single_step(env, 0);
|
1883 |
|
1884 |
if (reason == EXCP_DEBUG) {
|
1885 |
if (env->watchpoint_hit) {
|
1886 |
switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
|
1887 |
case BP_MEM_READ:
|
1888 |
type = "r";
|
1889 |
break;
|
1890 |
case BP_MEM_ACCESS:
|
1891 |
type = "a";
|
1892 |
break;
|
1893 |
default:
|
1894 |
type = "";
|
1895 |
break;
|
1896 |
} |
1897 |
snprintf(buf, sizeof(buf),
|
1898 |
"T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";", |
1899 |
GDB_SIGNAL_TRAP, env->cpu_index+1, type,
|
1900 |
env->watchpoint_hit->vaddr); |
1901 |
put_packet(s, buf); |
1902 |
env->watchpoint_hit = NULL;
|
1903 |
return;
|
1904 |
} |
1905 |
tb_flush(env); |
1906 |
ret = GDB_SIGNAL_TRAP; |
1907 |
} else if (reason == EXCP_INTERRUPT) { |
1908 |
ret = GDB_SIGNAL_INT; |
1909 |
} else {
|
1910 |
ret = 0;
|
1911 |
} |
1912 |
snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, env->cpu_index+1); |
1913 |
put_packet(s, buf); |
1914 |
} |
1915 |
#endif
|
1916 |
|
1917 |
/* Send a gdb syscall request.
|
1918 |
This accepts limited printf-style format specifiers, specifically:
|
1919 |
%x - target_ulong argument printed in hex.
|
1920 |
%lx - 64-bit argument printed in hex.
|
1921 |
%s - string pointer (target_ulong) and length (int) pair. */
|
1922 |
void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...) |
1923 |
{ |
1924 |
va_list va; |
1925 |
char buf[256]; |
1926 |
char *p;
|
1927 |
target_ulong addr; |
1928 |
uint64_t i64; |
1929 |
GDBState *s; |
1930 |
|
1931 |
s = gdbserver_state; |
1932 |
if (!s)
|
1933 |
return;
|
1934 |
gdb_current_syscall_cb = cb; |
1935 |
s->state = RS_SYSCALL; |
1936 |
#ifndef CONFIG_USER_ONLY
|
1937 |
vm_stop(EXCP_DEBUG); |
1938 |
#endif
|
1939 |
s->state = RS_IDLE; |
1940 |
va_start(va, fmt); |
1941 |
p = buf; |
1942 |
*(p++) = 'F';
|
1943 |
while (*fmt) {
|
1944 |
if (*fmt == '%') { |
1945 |
fmt++; |
1946 |
switch (*fmt++) {
|
1947 |
case 'x': |
1948 |
addr = va_arg(va, target_ulong); |
1949 |
p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
|
1950 |
break;
|
1951 |
case 'l': |
1952 |
if (*(fmt++) != 'x') |
1953 |
goto bad_format;
|
1954 |
i64 = va_arg(va, uint64_t); |
1955 |
p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64); |
1956 |
break;
|
1957 |
case 's': |
1958 |
addr = va_arg(va, target_ulong); |
1959 |
p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x", |
1960 |
addr, va_arg(va, int));
|
1961 |
break;
|
1962 |
default:
|
1963 |
bad_format:
|
1964 |
fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
|
1965 |
fmt - 1);
|
1966 |
break;
|
1967 |
} |
1968 |
} else {
|
1969 |
*(p++) = *(fmt++); |
1970 |
} |
1971 |
} |
1972 |
*p = 0;
|
1973 |
va_end(va); |
1974 |
put_packet(s, buf); |
1975 |
#ifdef CONFIG_USER_ONLY
|
1976 |
gdb_handlesig(s->c_cpu, 0);
|
1977 |
#else
|
1978 |
cpu_interrupt(s->c_cpu, CPU_INTERRUPT_EXIT); |
1979 |
#endif
|
1980 |
} |
1981 |
|
1982 |
static void gdb_read_byte(GDBState *s, int ch) |
1983 |
{ |
1984 |
int i, csum;
|
1985 |
uint8_t reply; |
1986 |
|
1987 |
#ifndef CONFIG_USER_ONLY
|
1988 |
if (s->last_packet_len) {
|
1989 |
/* Waiting for a response to the last packet. If we see the start
|
1990 |
of a new command then abandon the previous response. */
|
1991 |
if (ch == '-') { |
1992 |
#ifdef DEBUG_GDB
|
1993 |
printf("Got NACK, retransmitting\n");
|
1994 |
#endif
|
1995 |
put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len); |
1996 |
} |
1997 |
#ifdef DEBUG_GDB
|
1998 |
else if (ch == '+') |
1999 |
printf("Got ACK\n");
|
2000 |
else
|
2001 |
printf("Got '%c' when expecting ACK/NACK\n", ch);
|
2002 |
#endif
|
2003 |
if (ch == '+' || ch == '$') |
2004 |
s->last_packet_len = 0;
|
2005 |
if (ch != '$') |
2006 |
return;
|
2007 |
} |
2008 |
if (vm_running) {
|
2009 |
/* when the CPU is running, we cannot do anything except stop
|
2010 |
it when receiving a char */
|
2011 |
vm_stop(EXCP_INTERRUPT); |
2012 |
} else
|
2013 |
#endif
|
2014 |
{ |
2015 |
switch(s->state) {
|
2016 |
case RS_IDLE:
|
2017 |
if (ch == '$') { |
2018 |
s->line_buf_index = 0;
|
2019 |
s->state = RS_GETLINE; |
2020 |
} |
2021 |
break;
|
2022 |
case RS_GETLINE:
|
2023 |
if (ch == '#') { |
2024 |
s->state = RS_CHKSUM1; |
2025 |
} else if (s->line_buf_index >= sizeof(s->line_buf) - 1) { |
2026 |
s->state = RS_IDLE; |
2027 |
} else {
|
2028 |
s->line_buf[s->line_buf_index++] = ch; |
2029 |
} |
2030 |
break;
|
2031 |
case RS_CHKSUM1:
|
2032 |
s->line_buf[s->line_buf_index] = '\0';
|
2033 |
s->line_csum = fromhex(ch) << 4;
|
2034 |
s->state = RS_CHKSUM2; |
2035 |
break;
|
2036 |
case RS_CHKSUM2:
|
2037 |
s->line_csum |= fromhex(ch); |
2038 |
csum = 0;
|
2039 |
for(i = 0; i < s->line_buf_index; i++) { |
2040 |
csum += s->line_buf[i]; |
2041 |
} |
2042 |
if (s->line_csum != (csum & 0xff)) { |
2043 |
reply = '-';
|
2044 |
put_buffer(s, &reply, 1);
|
2045 |
s->state = RS_IDLE; |
2046 |
} else {
|
2047 |
reply = '+';
|
2048 |
put_buffer(s, &reply, 1);
|
2049 |
s->state = gdb_handle_packet(s, s->line_buf); |
2050 |
} |
2051 |
break;
|
2052 |
default:
|
2053 |
abort(); |
2054 |
} |
2055 |
} |
2056 |
} |
2057 |
|
2058 |
#ifdef CONFIG_USER_ONLY
|
2059 |
int
|
2060 |
gdb_queuesig (void)
|
2061 |
{ |
2062 |
GDBState *s; |
2063 |
|
2064 |
s = gdbserver_state; |
2065 |
|
2066 |
if (gdbserver_fd < 0 || s->fd < 0) |
2067 |
return 0; |
2068 |
else
|
2069 |
return 1; |
2070 |
} |
2071 |
|
2072 |
int
|
2073 |
gdb_handlesig (CPUState *env, int sig)
|
2074 |
{ |
2075 |
GDBState *s; |
2076 |
char buf[256]; |
2077 |
int n;
|
2078 |
|
2079 |
s = gdbserver_state; |
2080 |
if (gdbserver_fd < 0 || s->fd < 0) |
2081 |
return sig;
|
2082 |
|
2083 |
/* disable single step if it was enabled */
|
2084 |
cpu_single_step(env, 0);
|
2085 |
tb_flush(env); |
2086 |
|
2087 |
if (sig != 0) |
2088 |
{ |
2089 |
snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig)); |
2090 |
put_packet(s, buf); |
2091 |
} |
2092 |
/* put_packet() might have detected that the peer terminated the
|
2093 |
connection. */
|
2094 |
if (s->fd < 0) |
2095 |
return sig;
|
2096 |
|
2097 |
sig = 0;
|
2098 |
s->state = RS_IDLE; |
2099 |
s->running_state = 0;
|
2100 |
while (s->running_state == 0) { |
2101 |
n = read (s->fd, buf, 256);
|
2102 |
if (n > 0) |
2103 |
{ |
2104 |
int i;
|
2105 |
|
2106 |
for (i = 0; i < n; i++) |
2107 |
gdb_read_byte (s, buf[i]); |
2108 |
} |
2109 |
else if (n == 0 || errno != EAGAIN) |
2110 |
{ |
2111 |
/* XXX: Connection closed. Should probably wait for annother
|
2112 |
connection before continuing. */
|
2113 |
return sig;
|
2114 |
} |
2115 |
} |
2116 |
sig = s->signal; |
2117 |
s->signal = 0;
|
2118 |
return sig;
|
2119 |
} |
2120 |
|
2121 |
/* Tell the remote gdb that the process has exited. */
|
2122 |
void gdb_exit(CPUState *env, int code) |
2123 |
{ |
2124 |
GDBState *s; |
2125 |
char buf[4]; |
2126 |
|
2127 |
s = gdbserver_state; |
2128 |
if (gdbserver_fd < 0 || s->fd < 0) |
2129 |
return;
|
2130 |
|
2131 |
snprintf(buf, sizeof(buf), "W%02x", code); |
2132 |
put_packet(s, buf); |
2133 |
} |
2134 |
|
2135 |
/* Tell the remote gdb that the process has exited due to SIG. */
|
2136 |
void gdb_signalled(CPUState *env, int sig) |
2137 |
{ |
2138 |
GDBState *s; |
2139 |
char buf[4]; |
2140 |
|
2141 |
s = gdbserver_state; |
2142 |
if (gdbserver_fd < 0 || s->fd < 0) |
2143 |
return;
|
2144 |
|
2145 |
snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig)); |
2146 |
put_packet(s, buf); |
2147 |
} |
2148 |
|
2149 |
static void gdb_accept(void) |
2150 |
{ |
2151 |
GDBState *s; |
2152 |
struct sockaddr_in sockaddr;
|
2153 |
socklen_t len; |
2154 |
int val, fd;
|
2155 |
|
2156 |
for(;;) {
|
2157 |
len = sizeof(sockaddr);
|
2158 |
fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
|
2159 |
if (fd < 0 && errno != EINTR) { |
2160 |
perror("accept");
|
2161 |
return;
|
2162 |
} else if (fd >= 0) { |
2163 |
break;
|
2164 |
} |
2165 |
} |
2166 |
|
2167 |
/* set short latency */
|
2168 |
val = 1;
|
2169 |
setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val)); |
2170 |
|
2171 |
s = qemu_mallocz(sizeof(GDBState));
|
2172 |
if (!s) {
|
2173 |
errno = ENOMEM; |
2174 |
perror("accept");
|
2175 |
return;
|
2176 |
} |
2177 |
|
2178 |
memset (s, 0, sizeof (GDBState)); |
2179 |
s->c_cpu = first_cpu; |
2180 |
s->g_cpu = first_cpu; |
2181 |
s->fd = fd; |
2182 |
gdb_has_xml = 0;
|
2183 |
|
2184 |
gdbserver_state = s; |
2185 |
|
2186 |
fcntl(fd, F_SETFL, O_NONBLOCK); |
2187 |
} |
2188 |
|
2189 |
static int gdbserver_open(int port) |
2190 |
{ |
2191 |
struct sockaddr_in sockaddr;
|
2192 |
int fd, val, ret;
|
2193 |
|
2194 |
fd = socket(PF_INET, SOCK_STREAM, 0);
|
2195 |
if (fd < 0) { |
2196 |
perror("socket");
|
2197 |
return -1; |
2198 |
} |
2199 |
|
2200 |
/* allow fast reuse */
|
2201 |
val = 1;
|
2202 |
setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val)); |
2203 |
|
2204 |
sockaddr.sin_family = AF_INET; |
2205 |
sockaddr.sin_port = htons(port); |
2206 |
sockaddr.sin_addr.s_addr = 0;
|
2207 |
ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr)); |
2208 |
if (ret < 0) { |
2209 |
perror("bind");
|
2210 |
return -1; |
2211 |
} |
2212 |
ret = listen(fd, 0);
|
2213 |
if (ret < 0) { |
2214 |
perror("listen");
|
2215 |
return -1; |
2216 |
} |
2217 |
return fd;
|
2218 |
} |
2219 |
|
2220 |
int gdbserver_start(int port) |
2221 |
{ |
2222 |
gdbserver_fd = gdbserver_open(port); |
2223 |
if (gdbserver_fd < 0) |
2224 |
return -1; |
2225 |
/* accept connections */
|
2226 |
gdb_accept(); |
2227 |
return 0; |
2228 |
} |
2229 |
|
2230 |
/* Disable gdb stub for child processes. */
|
2231 |
void gdbserver_fork(CPUState *env)
|
2232 |
{ |
2233 |
GDBState *s = gdbserver_state; |
2234 |
if (gdbserver_fd < 0 || s->fd < 0) |
2235 |
return;
|
2236 |
close(s->fd); |
2237 |
s->fd = -1;
|
2238 |
cpu_breakpoint_remove_all(env, BP_GDB); |
2239 |
cpu_watchpoint_remove_all(env, BP_GDB); |
2240 |
} |
2241 |
#else
|
2242 |
static int gdb_chr_can_receive(void *opaque) |
2243 |
{ |
2244 |
/* We can handle an arbitrarily large amount of data.
|
2245 |
Pick the maximum packet size, which is as good as anything. */
|
2246 |
return MAX_PACKET_LENGTH;
|
2247 |
} |
2248 |
|
2249 |
static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size) |
2250 |
{ |
2251 |
int i;
|
2252 |
|
2253 |
for (i = 0; i < size; i++) { |
2254 |
gdb_read_byte(gdbserver_state, buf[i]); |
2255 |
} |
2256 |
} |
2257 |
|
2258 |
static void gdb_chr_event(void *opaque, int event) |
2259 |
{ |
2260 |
switch (event) {
|
2261 |
case CHR_EVENT_RESET:
|
2262 |
vm_stop(EXCP_INTERRUPT); |
2263 |
gdb_has_xml = 0;
|
2264 |
break;
|
2265 |
default:
|
2266 |
break;
|
2267 |
} |
2268 |
} |
2269 |
|
2270 |
int gdbserver_start(const char *port) |
2271 |
{ |
2272 |
GDBState *s; |
2273 |
char gdbstub_port_name[128]; |
2274 |
int port_num;
|
2275 |
char *p;
|
2276 |
CharDriverState *chr; |
2277 |
|
2278 |
if (!port || !*port)
|
2279 |
return -1; |
2280 |
|
2281 |
port_num = strtol(port, &p, 10);
|
2282 |
if (*p == 0) { |
2283 |
/* A numeric value is interpreted as a port number. */
|
2284 |
snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
|
2285 |
"tcp::%d,nowait,nodelay,server", port_num);
|
2286 |
port = gdbstub_port_name; |
2287 |
} |
2288 |
|
2289 |
chr = qemu_chr_open("gdb", port, NULL); |
2290 |
if (!chr)
|
2291 |
return -1; |
2292 |
|
2293 |
s = qemu_mallocz(sizeof(GDBState));
|
2294 |
if (!s) {
|
2295 |
return -1; |
2296 |
} |
2297 |
s->c_cpu = first_cpu; |
2298 |
s->g_cpu = first_cpu; |
2299 |
s->chr = chr; |
2300 |
gdbserver_state = s; |
2301 |
qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive, |
2302 |
gdb_chr_event, NULL);
|
2303 |
qemu_add_vm_stop_handler(gdb_vm_stopped, NULL);
|
2304 |
return 0; |
2305 |
} |
2306 |
#endif
|