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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "tcg.h"
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#ifndef CONFIG_NO_DYNGEN_OP
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/* legacy dyngen operations */
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#include "gen-op.h"
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#endif
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int gen_new_label(void);
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static inline void tcg_gen_op1(int opc, TCGv arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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}
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static inline void tcg_gen_op1i(int opc, TCGArg arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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}
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static inline void tcg_gen_op2(int opc, TCGv arg1, TCGv arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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}
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static inline void tcg_gen_op2i(int opc, TCGv arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op3(int opc, TCGv arg1, TCGv arg2, TCGv arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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}
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static inline void tcg_gen_op3i(int opc, TCGv arg1, TCGv arg2, TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_op4(int opc, TCGv arg1, TCGv arg2, TCGv arg3, 
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                               TCGv arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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}
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static inline void tcg_gen_op4i(int opc, TCGv arg1, TCGv arg2, TCGv arg3, 
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                                TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii(int opc, TCGv arg1, TCGv arg2, TCGArg arg3, 
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                                 TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op5(int opc, TCGv arg1, TCGv arg2, 
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                               TCGv arg3, TCGv arg4,
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                               TCGv arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = GET_TCGV(arg5);
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}
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static inline void tcg_gen_op5i(int opc, TCGv arg1, TCGv arg2, 
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                                TCGv arg3, TCGv arg4,
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                                TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op6(int opc, TCGv arg1, TCGv arg2, 
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                               TCGv arg3, TCGv arg4,
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                               TCGv arg5, TCGv arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = GET_TCGV(arg5);
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    *gen_opparam_ptr++ = GET_TCGV(arg6);
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}
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static inline void tcg_gen_op6ii(int opc, TCGv arg1, TCGv arg2, 
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                                 TCGv arg3, TCGv arg4,
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                                 TCGArg arg5, TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = arg5;
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void gen_set_label(int n)
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{
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    tcg_gen_op1i(INDEX_op_set_label, n);
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}
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static inline void tcg_gen_br(int label)
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{
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    tcg_gen_op1i(INDEX_op_br, label);
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}
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static inline void tcg_gen_mov_i32(TCGv ret, TCGv arg)
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{
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    tcg_gen_op2(INDEX_op_mov_i32, ret, arg);
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}
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static inline void tcg_gen_movi_i32(TCGv ret, int32_t arg)
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{
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    tcg_gen_op2i(INDEX_op_movi_i32, ret, arg);
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}
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/* helper calls */
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#define TCG_HELPER_CALL_FLAGS 0
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static inline void tcg_gen_helper_0_0(void *func)
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{
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    tcg_gen_call(&tcg_ctx, 
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 0, NULL);
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}
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static inline void tcg_gen_helper_0_1(void *func, TCGv arg)
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{
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 1, &arg);
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}
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static inline void tcg_gen_helper_0_2(void *func, TCGv arg1, TCGv arg2)
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{
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    TCGv args[2];
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    args[0] = arg1;
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    args[1] = arg2;
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    tcg_gen_call(&tcg_ctx, 
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 2, args);
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}
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static inline void tcg_gen_helper_0_4(void *func, TCGv arg1, TCGv arg2,
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                                      TCGv arg3, TCGv arg4)
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{
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    TCGv args[4];
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    args[3] = arg4;
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 4, args);
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}
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static inline void tcg_gen_helper_1_0(void *func, TCGv ret)
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{
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 0, NULL);
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}
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static inline void tcg_gen_helper_1_1(void *func, TCGv ret, TCGv arg1)
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{
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 1, &arg1);
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}
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static inline void tcg_gen_helper_1_2(void *func, TCGv ret, 
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                                      TCGv arg1, TCGv arg2)
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{
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    TCGv args[2];
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    args[0] = arg1;
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    args[1] = arg2;
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    tcg_gen_call(&tcg_ctx, 
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 2, args);
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}
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static inline void tcg_gen_helper_1_4(void *func, TCGv ret,
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                                      TCGv arg1, TCGv arg2, TCGv arg3,
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                                      TCGv arg4)
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{
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    TCGv args[4];
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    args[3] = arg4;
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 4, args);
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}
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/* 32 bit ops */
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static inline void tcg_gen_ld8u_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld8u_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld8s_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld8s_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld16u_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld16u_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld16s_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld16s_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_st8_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st8_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_st16_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st16_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_st_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_add_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_add_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_addi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_add_i32(ret, arg1, tcg_const_i32(arg2));
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    }
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}
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static inline void tcg_gen_sub_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_sub_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_subi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_sub_i32(ret, arg1, tcg_const_i32(arg2));
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    }
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}
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static inline void tcg_gen_and_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_and_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_andi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0) {
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        tcg_gen_movi_i32(ret, 0);
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    } else if (arg2 == 0xffffffff) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_and_i32(ret, arg1, tcg_const_i32(arg2));
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    }
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}
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static inline void tcg_gen_or_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_or_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_ori_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0xffffffff) {
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        tcg_gen_movi_i32(ret, 0xffffffff);
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    } else if (arg2 == 0) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_or_i32(ret, arg1, tcg_const_i32(arg2));
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    }
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}
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static inline void tcg_gen_xor_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_xor_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_xori_i32(TCGv ret, TCGv arg1, int32_t arg2)
366 c896fe29 bellard
{
367 c896fe29 bellard
    /* some cases can be optimized here */
368 c896fe29 bellard
    if (arg2 == 0) {
369 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
370 c896fe29 bellard
    } else {
371 c896fe29 bellard
        tcg_gen_xor_i32(ret, arg1, tcg_const_i32(arg2));
372 c896fe29 bellard
    }
373 c896fe29 bellard
}
374 c896fe29 bellard
375 ac56dd48 pbrook
static inline void tcg_gen_shl_i32(TCGv ret, TCGv arg1, TCGv arg2)
376 c896fe29 bellard
{
377 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shl_i32, ret, arg1, arg2);
378 c896fe29 bellard
}
379 c896fe29 bellard
380 ac56dd48 pbrook
static inline void tcg_gen_shli_i32(TCGv ret, TCGv arg1, int32_t arg2)
381 c896fe29 bellard
{
382 c896fe29 bellard
    tcg_gen_shl_i32(ret, arg1, tcg_const_i32(arg2));
383 c896fe29 bellard
}
384 c896fe29 bellard
385 ac56dd48 pbrook
static inline void tcg_gen_shr_i32(TCGv ret, TCGv arg1, TCGv arg2)
386 c896fe29 bellard
{
387 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shr_i32, ret, arg1, arg2);
388 c896fe29 bellard
}
389 c896fe29 bellard
390 ac56dd48 pbrook
static inline void tcg_gen_shri_i32(TCGv ret, TCGv arg1, int32_t arg2)
391 c896fe29 bellard
{
392 c896fe29 bellard
    tcg_gen_shr_i32(ret, arg1, tcg_const_i32(arg2));
393 c896fe29 bellard
}
394 c896fe29 bellard
395 ac56dd48 pbrook
static inline void tcg_gen_sar_i32(TCGv ret, TCGv arg1, TCGv arg2)
396 c896fe29 bellard
{
397 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sar_i32, ret, arg1, arg2);
398 c896fe29 bellard
}
399 c896fe29 bellard
400 ac56dd48 pbrook
static inline void tcg_gen_sari_i32(TCGv ret, TCGv arg1, int32_t arg2)
401 c896fe29 bellard
{
402 c896fe29 bellard
    tcg_gen_sar_i32(ret, arg1, tcg_const_i32(arg2));
403 c896fe29 bellard
}
404 c896fe29 bellard
405 ac56dd48 pbrook
static inline void tcg_gen_brcond_i32(int cond, TCGv arg1, TCGv arg2, 
406 c896fe29 bellard
                                      int label_index)
407 c896fe29 bellard
{
408 ac56dd48 pbrook
    tcg_gen_op4ii(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
409 c896fe29 bellard
}
410 c896fe29 bellard
411 ac56dd48 pbrook
static inline void tcg_gen_mul_i32(TCGv ret, TCGv arg1, TCGv arg2)
412 c896fe29 bellard
{
413 c896fe29 bellard
    tcg_gen_op3(INDEX_op_mul_i32, ret, arg1, arg2);
414 c896fe29 bellard
}
415 c896fe29 bellard
416 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i32
417 ac56dd48 pbrook
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2)
418 c896fe29 bellard
{
419 c896fe29 bellard
    tcg_gen_op3(INDEX_op_div_i32, ret, arg1, arg2);
420 c896fe29 bellard
}
421 c896fe29 bellard
422 ac56dd48 pbrook
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2)
423 c896fe29 bellard
{
424 c896fe29 bellard
    tcg_gen_op3(INDEX_op_rem_i32, ret, arg1, arg2);
425 c896fe29 bellard
}
426 c896fe29 bellard
427 ac56dd48 pbrook
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2)
428 c896fe29 bellard
{
429 c896fe29 bellard
    tcg_gen_op3(INDEX_op_divu_i32, ret, arg1, arg2);
430 c896fe29 bellard
}
431 c896fe29 bellard
432 ac56dd48 pbrook
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2)
433 c896fe29 bellard
{
434 c896fe29 bellard
    tcg_gen_op3(INDEX_op_remu_i32, ret, arg1, arg2);
435 c896fe29 bellard
}
436 c896fe29 bellard
#else
437 ac56dd48 pbrook
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2)
438 c896fe29 bellard
{
439 ac56dd48 pbrook
    TCGv t0;
440 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
441 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
442 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
443 c896fe29 bellard
}
444 c896fe29 bellard
445 ac56dd48 pbrook
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2)
446 c896fe29 bellard
{
447 ac56dd48 pbrook
    TCGv t0;
448 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
449 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
450 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
451 c896fe29 bellard
}
452 c896fe29 bellard
453 ac56dd48 pbrook
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2)
454 c896fe29 bellard
{
455 ac56dd48 pbrook
    TCGv t0;
456 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
457 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
458 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
459 c896fe29 bellard
}
460 c896fe29 bellard
461 ac56dd48 pbrook
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2)
462 c896fe29 bellard
{
463 ac56dd48 pbrook
    TCGv t0;
464 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
465 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
466 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
467 c896fe29 bellard
}
468 c896fe29 bellard
#endif
469 c896fe29 bellard
470 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
471 c896fe29 bellard
472 ac56dd48 pbrook
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg)
473 c896fe29 bellard
{
474 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
475 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
476 c896fe29 bellard
}
477 c896fe29 bellard
478 ac56dd48 pbrook
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg)
479 c896fe29 bellard
{
480 c896fe29 bellard
    tcg_gen_movi_i32(ret, arg);
481 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
482 c896fe29 bellard
}
483 c896fe29 bellard
484 ac56dd48 pbrook
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
485 c896fe29 bellard
{
486 c896fe29 bellard
    tcg_gen_ld8u_i32(ret, arg2, offset);
487 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
488 c896fe29 bellard
}
489 c896fe29 bellard
490 ac56dd48 pbrook
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
491 c896fe29 bellard
{
492 c896fe29 bellard
    tcg_gen_ld8s_i32(ret, arg2, offset);
493 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
494 c896fe29 bellard
}
495 c896fe29 bellard
496 ac56dd48 pbrook
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
497 c896fe29 bellard
{
498 c896fe29 bellard
    tcg_gen_ld16u_i32(ret, arg2, offset);
499 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
500 c896fe29 bellard
}
501 c896fe29 bellard
502 ac56dd48 pbrook
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
503 c896fe29 bellard
{
504 c896fe29 bellard
    tcg_gen_ld16s_i32(ret, arg2, offset);
505 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
506 c896fe29 bellard
}
507 c896fe29 bellard
508 ac56dd48 pbrook
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
509 c896fe29 bellard
{
510 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
511 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
512 c896fe29 bellard
}
513 c896fe29 bellard
514 ac56dd48 pbrook
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
515 c896fe29 bellard
{
516 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
517 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
518 c896fe29 bellard
}
519 c896fe29 bellard
520 ac56dd48 pbrook
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
521 c896fe29 bellard
{
522 c896fe29 bellard
    /* since arg2 and ret have different types, they cannot be the
523 c896fe29 bellard
       same temporary */
524 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
525 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
526 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset + 4);
527 c896fe29 bellard
#else
528 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
529 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
530 c896fe29 bellard
#endif
531 c896fe29 bellard
}
532 c896fe29 bellard
533 ac56dd48 pbrook
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
534 c896fe29 bellard
{
535 c896fe29 bellard
    tcg_gen_st8_i32(arg1, arg2, offset);
536 c896fe29 bellard
}
537 c896fe29 bellard
538 ac56dd48 pbrook
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
539 c896fe29 bellard
{
540 c896fe29 bellard
    tcg_gen_st16_i32(arg1, arg2, offset);
541 c896fe29 bellard
}
542 c896fe29 bellard
543 ac56dd48 pbrook
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
544 c896fe29 bellard
{
545 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset);
546 c896fe29 bellard
}
547 c896fe29 bellard
548 ac56dd48 pbrook
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
549 c896fe29 bellard
{
550 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
551 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
552 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset + 4);
553 c896fe29 bellard
#else
554 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset);
555 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
556 c896fe29 bellard
#endif
557 c896fe29 bellard
}
558 c896fe29 bellard
559 ac56dd48 pbrook
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2)
560 c896fe29 bellard
{
561 ac56dd48 pbrook
    tcg_gen_op6(INDEX_op_add2_i32, ret, TCGV_HIGH(ret), 
562 ac56dd48 pbrook
                arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2));
563 c896fe29 bellard
}
564 c896fe29 bellard
565 ac56dd48 pbrook
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2)
566 c896fe29 bellard
{
567 c896fe29 bellard
    tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2));
568 c896fe29 bellard
}
569 c896fe29 bellard
570 ac56dd48 pbrook
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2)
571 c896fe29 bellard
{
572 ac56dd48 pbrook
    tcg_gen_op6(INDEX_op_sub2_i32, ret, TCGV_HIGH(ret), 
573 ac56dd48 pbrook
                arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2));
574 c896fe29 bellard
}
575 c896fe29 bellard
576 ac56dd48 pbrook
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2)
577 c896fe29 bellard
{
578 c896fe29 bellard
    tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2));
579 c896fe29 bellard
}
580 c896fe29 bellard
581 ac56dd48 pbrook
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2)
582 c896fe29 bellard
{
583 c896fe29 bellard
    tcg_gen_and_i32(ret, arg1, arg2);
584 ac56dd48 pbrook
    tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
585 c896fe29 bellard
}
586 c896fe29 bellard
587 ac56dd48 pbrook
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2)
588 c896fe29 bellard
{
589 c896fe29 bellard
    tcg_gen_andi_i32(ret, arg1, arg2);
590 ac56dd48 pbrook
    tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
591 c896fe29 bellard
}
592 c896fe29 bellard
593 ac56dd48 pbrook
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2)
594 c896fe29 bellard
{
595 c896fe29 bellard
    tcg_gen_or_i32(ret, arg1, arg2);
596 ac56dd48 pbrook
    tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
597 c896fe29 bellard
}
598 c896fe29 bellard
599 ac56dd48 pbrook
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2)
600 c896fe29 bellard
{
601 c896fe29 bellard
    tcg_gen_ori_i32(ret, arg1, arg2);
602 ac56dd48 pbrook
    tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
603 c896fe29 bellard
}
604 c896fe29 bellard
605 ac56dd48 pbrook
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2)
606 c896fe29 bellard
{
607 c896fe29 bellard
    tcg_gen_xor_i32(ret, arg1, arg2);
608 ac56dd48 pbrook
    tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
609 c896fe29 bellard
}
610 c896fe29 bellard
611 ac56dd48 pbrook
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2)
612 c896fe29 bellard
{
613 c896fe29 bellard
    tcg_gen_xori_i32(ret, arg1, arg2);
614 ac56dd48 pbrook
    tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
615 c896fe29 bellard
}
616 c896fe29 bellard
617 c896fe29 bellard
/* XXX: use generic code when basic block handling is OK or CPU
618 c896fe29 bellard
   specific code (x86) */
619 ac56dd48 pbrook
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2)
620 c896fe29 bellard
{
621 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_shl_i64, ret, arg1, arg2);
622 c896fe29 bellard
}
623 c896fe29 bellard
624 ac56dd48 pbrook
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2)
625 c896fe29 bellard
{
626 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
627 c896fe29 bellard
}
628 c896fe29 bellard
629 ac56dd48 pbrook
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2)
630 c896fe29 bellard
{
631 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_shr_i64, ret, arg1, arg2);
632 c896fe29 bellard
}
633 c896fe29 bellard
634 ac56dd48 pbrook
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2)
635 c896fe29 bellard
{
636 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
637 c896fe29 bellard
}
638 c896fe29 bellard
639 ac56dd48 pbrook
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2)
640 c896fe29 bellard
{
641 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_sar_i64, ret, arg1, arg2);
642 c896fe29 bellard
}
643 c896fe29 bellard
644 ac56dd48 pbrook
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2)
645 c896fe29 bellard
{
646 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
647 c896fe29 bellard
}
648 c896fe29 bellard
649 ac56dd48 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, 
650 c896fe29 bellard
                                      int label_index)
651 c896fe29 bellard
{
652 ac56dd48 pbrook
    tcg_gen_op6ii(INDEX_op_brcond2_i32, 
653 ac56dd48 pbrook
                  arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2),
654 ac56dd48 pbrook
                  cond, label_index);
655 c896fe29 bellard
}
656 c896fe29 bellard
657 ac56dd48 pbrook
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2)
658 c896fe29 bellard
{
659 ac56dd48 pbrook
    TCGv t0, t1;
660 c896fe29 bellard
    
661 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
662 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
663 c896fe29 bellard
664 ac56dd48 pbrook
    tcg_gen_op4(INDEX_op_mulu2_i32, t0, TCGV_HIGH(t0), arg1, arg2);
665 c896fe29 bellard
    
666 ac56dd48 pbrook
    tcg_gen_mul_i32(t1, arg1, TCGV_HIGH(arg2));
667 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
668 ac56dd48 pbrook
    tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), arg2);
669 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
670 c896fe29 bellard
    
671 c896fe29 bellard
    tcg_gen_mov_i64(ret, t0);
672 c896fe29 bellard
}
673 c896fe29 bellard
674 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
675 c896fe29 bellard
{
676 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_div_i64, ret, arg1, arg2);
677 c896fe29 bellard
}
678 c896fe29 bellard
679 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
680 c896fe29 bellard
{
681 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_rem_i64, ret, arg1, arg2);
682 c896fe29 bellard
}
683 c896fe29 bellard
684 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
685 c896fe29 bellard
{
686 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_divu_i64, ret, arg1, arg2);
687 c896fe29 bellard
}
688 c896fe29 bellard
689 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
690 c896fe29 bellard
{
691 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_remu_i64, ret, arg1, arg2);
692 c896fe29 bellard
}
693 c896fe29 bellard
694 c896fe29 bellard
#else
695 c896fe29 bellard
696 ac56dd48 pbrook
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg)
697 c896fe29 bellard
{
698 c896fe29 bellard
    tcg_gen_op2(INDEX_op_mov_i64, ret, arg);
699 c896fe29 bellard
}
700 c896fe29 bellard
701 ac56dd48 pbrook
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg)
702 c896fe29 bellard
{
703 ac56dd48 pbrook
    tcg_gen_op2i(INDEX_op_movi_i64, ret, arg);
704 c896fe29 bellard
}
705 c896fe29 bellard
706 ac56dd48 pbrook
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2,
707 ac56dd48 pbrook
                                    tcg_target_long offset)
708 c896fe29 bellard
{
709 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld8u_i64, ret, arg2, offset);
710 c896fe29 bellard
}
711 c896fe29 bellard
712 ac56dd48 pbrook
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2,
713 ac56dd48 pbrook
                                    tcg_target_long offset)
714 c896fe29 bellard
{
715 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld8s_i64, ret, arg2, offset);
716 c896fe29 bellard
}
717 c896fe29 bellard
718 ac56dd48 pbrook
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2,
719 ac56dd48 pbrook
                                     tcg_target_long offset)
720 c896fe29 bellard
{
721 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld16u_i64, ret, arg2, offset);
722 c896fe29 bellard
}
723 c896fe29 bellard
724 ac56dd48 pbrook
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2,
725 ac56dd48 pbrook
                                     tcg_target_long offset)
726 c896fe29 bellard
{
727 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld16s_i64, ret, arg2, offset);
728 c896fe29 bellard
}
729 c896fe29 bellard
730 ac56dd48 pbrook
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2,
731 ac56dd48 pbrook
                                     tcg_target_long offset)
732 c896fe29 bellard
{
733 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld32u_i64, ret, arg2, offset);
734 c896fe29 bellard
}
735 c896fe29 bellard
736 ac56dd48 pbrook
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2,
737 ac56dd48 pbrook
                                     tcg_target_long offset)
738 c896fe29 bellard
{
739 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld32s_i64, ret, arg2, offset);
740 c896fe29 bellard
}
741 c896fe29 bellard
742 ac56dd48 pbrook
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
743 c896fe29 bellard
{
744 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld_i64, ret, arg2, offset);
745 c896fe29 bellard
}
746 c896fe29 bellard
747 ac56dd48 pbrook
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2,
748 ac56dd48 pbrook
                                   tcg_target_long offset)
749 c896fe29 bellard
{
750 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st8_i64, arg1, arg2, offset);
751 c896fe29 bellard
}
752 c896fe29 bellard
753 ac56dd48 pbrook
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2,
754 ac56dd48 pbrook
                                    tcg_target_long offset)
755 c896fe29 bellard
{
756 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st16_i64, arg1, arg2, offset);
757 c896fe29 bellard
}
758 c896fe29 bellard
759 ac56dd48 pbrook
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2,
760 ac56dd48 pbrook
                                    tcg_target_long offset)
761 c896fe29 bellard
{
762 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st32_i64, arg1, arg2, offset);
763 c896fe29 bellard
}
764 c896fe29 bellard
765 ac56dd48 pbrook
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
766 c896fe29 bellard
{
767 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st_i64, arg1, arg2, offset);
768 c896fe29 bellard
}
769 c896fe29 bellard
770 ac56dd48 pbrook
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2)
771 c896fe29 bellard
{
772 c896fe29 bellard
    tcg_gen_op3(INDEX_op_add_i64, ret, arg1, arg2);
773 c896fe29 bellard
}
774 c896fe29 bellard
775 ac56dd48 pbrook
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2)
776 c896fe29 bellard
{
777 c896fe29 bellard
    tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2));
778 c896fe29 bellard
}
779 c896fe29 bellard
780 ac56dd48 pbrook
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2)
781 c896fe29 bellard
{
782 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sub_i64, ret, arg1, arg2);
783 c896fe29 bellard
}
784 c896fe29 bellard
785 ac56dd48 pbrook
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2)
786 c896fe29 bellard
{
787 c896fe29 bellard
    tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2));
788 c896fe29 bellard
}
789 c896fe29 bellard
790 ac56dd48 pbrook
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2)
791 c896fe29 bellard
{
792 c896fe29 bellard
    tcg_gen_op3(INDEX_op_and_i64, ret, arg1, arg2);
793 c896fe29 bellard
}
794 c896fe29 bellard
795 ac56dd48 pbrook
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2)
796 c896fe29 bellard
{
797 c896fe29 bellard
    tcg_gen_and_i64(ret, arg1, tcg_const_i64(arg2));
798 c896fe29 bellard
}
799 c896fe29 bellard
800 ac56dd48 pbrook
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2)
801 c896fe29 bellard
{
802 c896fe29 bellard
    tcg_gen_op3(INDEX_op_or_i64, ret, arg1, arg2);
803 c896fe29 bellard
}
804 c896fe29 bellard
805 ac56dd48 pbrook
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2)
806 c896fe29 bellard
{
807 c896fe29 bellard
    tcg_gen_or_i64(ret, arg1, tcg_const_i64(arg2));
808 c896fe29 bellard
}
809 c896fe29 bellard
810 ac56dd48 pbrook
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2)
811 c896fe29 bellard
{
812 c896fe29 bellard
    tcg_gen_op3(INDEX_op_xor_i64, ret, arg1, arg2);
813 c896fe29 bellard
}
814 c896fe29 bellard
815 ac56dd48 pbrook
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2)
816 c896fe29 bellard
{
817 c896fe29 bellard
    tcg_gen_xor_i64(ret, arg1, tcg_const_i64(arg2));
818 c896fe29 bellard
}
819 c896fe29 bellard
820 ac56dd48 pbrook
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2)
821 c896fe29 bellard
{
822 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shl_i64, ret, arg1, arg2);
823 c896fe29 bellard
}
824 c896fe29 bellard
825 ac56dd48 pbrook
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2)
826 c896fe29 bellard
{
827 c896fe29 bellard
    tcg_gen_shl_i64(ret, arg1, tcg_const_i64(arg2));
828 c896fe29 bellard
}
829 c896fe29 bellard
830 ac56dd48 pbrook
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2)
831 c896fe29 bellard
{
832 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shr_i64, ret, arg1, arg2);
833 c896fe29 bellard
}
834 c896fe29 bellard
835 ac56dd48 pbrook
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2)
836 c896fe29 bellard
{
837 c896fe29 bellard
    tcg_gen_shr_i64(ret, arg1, tcg_const_i64(arg2));
838 c896fe29 bellard
}
839 c896fe29 bellard
840 ac56dd48 pbrook
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2)
841 c896fe29 bellard
{
842 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sar_i64, ret, arg1, arg2);
843 c896fe29 bellard
}
844 c896fe29 bellard
845 ac56dd48 pbrook
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2)
846 c896fe29 bellard
{
847 c896fe29 bellard
    tcg_gen_sar_i64(ret, arg1, tcg_const_i64(arg2));
848 c896fe29 bellard
}
849 c896fe29 bellard
850 ac56dd48 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, 
851 c896fe29 bellard
                                      int label_index)
852 c896fe29 bellard
{
853 ac56dd48 pbrook
    tcg_gen_op4ii(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
854 c896fe29 bellard
}
855 c896fe29 bellard
856 ac56dd48 pbrook
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2)
857 c896fe29 bellard
{
858 c896fe29 bellard
    tcg_gen_op3(INDEX_op_mul_i64, ret, arg1, arg2);
859 c896fe29 bellard
}
860 c896fe29 bellard
861 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i64
862 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
863 c896fe29 bellard
{
864 c896fe29 bellard
    tcg_gen_op3(INDEX_op_div_i64, ret, arg1, arg2);
865 c896fe29 bellard
}
866 c896fe29 bellard
867 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
868 c896fe29 bellard
{
869 c896fe29 bellard
    tcg_gen_op3(INDEX_op_rem_i64, ret, arg1, arg2);
870 c896fe29 bellard
}
871 c896fe29 bellard
872 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
873 c896fe29 bellard
{
874 c896fe29 bellard
    tcg_gen_op3(INDEX_op_divu_i64, ret, arg1, arg2);
875 c896fe29 bellard
}
876 c896fe29 bellard
877 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
878 c896fe29 bellard
{
879 c896fe29 bellard
    tcg_gen_op3(INDEX_op_remu_i64, ret, arg1, arg2);
880 c896fe29 bellard
}
881 c896fe29 bellard
#else
882 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
883 c896fe29 bellard
{
884 ac56dd48 pbrook
    TCGv t0;
885 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
886 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
887 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
888 c896fe29 bellard
}
889 c896fe29 bellard
890 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
891 c896fe29 bellard
{
892 ac56dd48 pbrook
    TCGv t0;
893 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
894 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
895 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
896 c896fe29 bellard
}
897 c896fe29 bellard
898 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
899 c896fe29 bellard
{
900 ac56dd48 pbrook
    TCGv t0;
901 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
902 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
903 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
904 c896fe29 bellard
}
905 c896fe29 bellard
906 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
907 c896fe29 bellard
{
908 ac56dd48 pbrook
    TCGv t0;
909 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
910 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
911 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
912 c896fe29 bellard
}
913 c896fe29 bellard
#endif
914 c896fe29 bellard
915 c896fe29 bellard
#endif
916 c896fe29 bellard
917 c896fe29 bellard
/***************************************/
918 c896fe29 bellard
/* optional operations */
919 c896fe29 bellard
920 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i32(TCGv ret, TCGv arg)
921 c896fe29 bellard
{
922 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i32
923 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext8s_i32, ret, arg);
924 c896fe29 bellard
#else
925 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 24);
926 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 24);
927 c896fe29 bellard
#endif
928 c896fe29 bellard
}
929 c896fe29 bellard
930 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i32(TCGv ret, TCGv arg)
931 c896fe29 bellard
{
932 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i32
933 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext16s_i32, ret, arg);
934 c896fe29 bellard
#else
935 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 16);
936 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 16);
937 c896fe29 bellard
#endif
938 c896fe29 bellard
}
939 c896fe29 bellard
940 c896fe29 bellard
/* Note: we assume the two high bytes are set to zero */
941 ac56dd48 pbrook
static inline void tcg_gen_bswap16_i32(TCGv ret, TCGv arg)
942 c896fe29 bellard
{
943 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap16_i32
944 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap16_i32, ret, arg);
945 c896fe29 bellard
#else
946 ac56dd48 pbrook
    TCGv t0, t1;
947 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
948 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
949 c896fe29 bellard
    
950 c896fe29 bellard
    tcg_gen_shri_i32(t0, arg, 8);
951 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x000000ff);
952 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
953 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
954 c896fe29 bellard
#endif
955 c896fe29 bellard
}
956 c896fe29 bellard
957 ac56dd48 pbrook
static inline void tcg_gen_bswap_i32(TCGv ret, TCGv arg)
958 c896fe29 bellard
{
959 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap_i32
960 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap_i32, ret, arg);
961 c896fe29 bellard
#else
962 ac56dd48 pbrook
    TCGv t0, t1;
963 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
964 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
965 c896fe29 bellard
    
966 c896fe29 bellard
    tcg_gen_shli_i32(t0, arg, 24);
967 c896fe29 bellard
    
968 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x0000ff00);
969 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
970 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
971 c896fe29 bellard
    
972 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 8);
973 c896fe29 bellard
    tcg_gen_andi_i32(t1, t1, 0x0000ff00);
974 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
975 c896fe29 bellard
    
976 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 24);
977 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
978 c896fe29 bellard
#endif
979 c896fe29 bellard
}
980 c896fe29 bellard
981 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
982 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg)
983 c896fe29 bellard
{
984 c896fe29 bellard
    tcg_gen_ext8s_i32(ret, arg);
985 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
986 c896fe29 bellard
}
987 c896fe29 bellard
988 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg)
989 c896fe29 bellard
{
990 c896fe29 bellard
    tcg_gen_ext16s_i32(ret, arg);
991 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
992 c896fe29 bellard
}
993 c896fe29 bellard
994 ac56dd48 pbrook
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg)
995 c896fe29 bellard
{
996 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
997 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
998 c896fe29 bellard
}
999 c896fe29 bellard
1000 ac56dd48 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg)
1001 c896fe29 bellard
{
1002 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1003 c896fe29 bellard
}
1004 c896fe29 bellard
1005 ac56dd48 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg)
1006 c896fe29 bellard
{
1007 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1008 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1009 c896fe29 bellard
}
1010 c896fe29 bellard
1011 ac56dd48 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg)
1012 c896fe29 bellard
{
1013 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1014 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1015 c896fe29 bellard
}
1016 c896fe29 bellard
1017 ac56dd48 pbrook
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
1018 c896fe29 bellard
{
1019 ac56dd48 pbrook
    TCGv t0, t1;
1020 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1021 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1022 c896fe29 bellard
1023 c896fe29 bellard
    tcg_gen_bswap_i32(t0, arg);
1024 ac56dd48 pbrook
    tcg_gen_bswap_i32(t1, TCGV_HIGH(arg));
1025 c896fe29 bellard
    tcg_gen_mov_i32(ret, t1);
1026 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1027 c896fe29 bellard
}
1028 c896fe29 bellard
#else
1029 c896fe29 bellard
1030 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg)
1031 c896fe29 bellard
{
1032 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i64
1033 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext8s_i64, ret, arg);
1034 c896fe29 bellard
#else
1035 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 56);
1036 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 56);
1037 c896fe29 bellard
#endif
1038 c896fe29 bellard
}
1039 c896fe29 bellard
1040 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg)
1041 c896fe29 bellard
{
1042 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i64
1043 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext16s_i64, ret, arg);
1044 c896fe29 bellard
#else
1045 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 48);
1046 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 48);
1047 c896fe29 bellard
#endif
1048 c896fe29 bellard
}
1049 c896fe29 bellard
1050 ac56dd48 pbrook
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg)
1051 c896fe29 bellard
{
1052 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext32s_i64
1053 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext32s_i64, ret, arg);
1054 c896fe29 bellard
#else
1055 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 32);
1056 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 32);
1057 c896fe29 bellard
#endif
1058 c896fe29 bellard
}
1059 c896fe29 bellard
1060 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1061 ac56dd48 pbrook
   registers.  This will probably break MIPS64 targets.  */
1062 ac56dd48 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg)
1063 c896fe29 bellard
{
1064 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1065 c896fe29 bellard
}
1066 c896fe29 bellard
1067 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1068 c896fe29 bellard
   registers */
1069 ac56dd48 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg)
1070 c896fe29 bellard
{
1071 c896fe29 bellard
    tcg_gen_andi_i64(ret, arg, 0xffffffff);
1072 c896fe29 bellard
}
1073 c896fe29 bellard
1074 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1075 c896fe29 bellard
   registers */
1076 ac56dd48 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg)
1077 c896fe29 bellard
{
1078 c896fe29 bellard
    tcg_gen_ext32s_i64(ret, arg);
1079 c896fe29 bellard
}
1080 c896fe29 bellard
1081 ac56dd48 pbrook
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
1082 c896fe29 bellard
{
1083 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap_i64
1084 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap_i64, ret, arg);
1085 c896fe29 bellard
#else
1086 ac56dd48 pbrook
    TCGv t0, t1;
1087 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1088 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1089 c896fe29 bellard
    
1090 c896fe29 bellard
    tcg_gen_shli_i64(t0, arg, 56);
1091 c896fe29 bellard
    
1092 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1093 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 40);
1094 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1095 c896fe29 bellard
    
1096 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1097 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 24);
1098 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1099 c896fe29 bellard
1100 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0xff000000);
1101 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 8);
1102 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1103 c896fe29 bellard
1104 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 8);
1105 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0xff000000);
1106 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1107 c896fe29 bellard
    
1108 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 24);
1109 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1110 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1111 c896fe29 bellard
1112 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 40);
1113 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1114 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1115 c896fe29 bellard
1116 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 56);
1117 c896fe29 bellard
    tcg_gen_or_i64(ret, t0, t1);
1118 c896fe29 bellard
#endif
1119 c896fe29 bellard
}
1120 c896fe29 bellard
1121 c896fe29 bellard
#endif
1122 c896fe29 bellard
1123 5ff9d6a4 bellard
1124 5ff9d6a4 bellard
static inline void tcg_gen_discard_i32(TCGv arg)
1125 5ff9d6a4 bellard
{
1126 5ff9d6a4 bellard
    tcg_gen_op1(INDEX_op_discard, arg);
1127 5ff9d6a4 bellard
}
1128 5ff9d6a4 bellard
1129 5ff9d6a4 bellard
#if TCG_TARGET_REG_BITS == 32
1130 5ff9d6a4 bellard
static inline void tcg_gen_discard_i64(TCGv arg)
1131 5ff9d6a4 bellard
{
1132 5ff9d6a4 bellard
    tcg_gen_discard_i32(arg);
1133 5ff9d6a4 bellard
    tcg_gen_discard_i32(TCGV_HIGH(arg));
1134 5ff9d6a4 bellard
}
1135 5ff9d6a4 bellard
#else
1136 5ff9d6a4 bellard
static inline void tcg_gen_discard_i64(TCGv arg)
1137 5ff9d6a4 bellard
{
1138 5ff9d6a4 bellard
    tcg_gen_op1(INDEX_op_discard, arg);
1139 5ff9d6a4 bellard
}
1140 5ff9d6a4 bellard
#endif
1141 5ff9d6a4 bellard
1142 c896fe29 bellard
/***************************************/
1143 ac56dd48 pbrook
static inline void tcg_gen_macro_2(TCGv ret0, TCGv ret1, int macro_id)
1144 c896fe29 bellard
{
1145 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_macro_2, ret0, ret1, macro_id);
1146 c896fe29 bellard
}
1147 c896fe29 bellard
1148 c896fe29 bellard
/***************************************/
1149 c896fe29 bellard
/* QEMU specific operations. Their type depend on the QEMU CPU
1150 c896fe29 bellard
   type. */
1151 c896fe29 bellard
#ifndef TARGET_LONG_BITS
1152 c896fe29 bellard
#error must include QEMU headers
1153 c896fe29 bellard
#endif
1154 c896fe29 bellard
1155 c896fe29 bellard
static inline void tcg_gen_exit_tb(tcg_target_long val)
1156 c896fe29 bellard
{
1157 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_exit_tb, val);
1158 c896fe29 bellard
}
1159 c896fe29 bellard
1160 c896fe29 bellard
static inline void tcg_gen_goto_tb(int idx)
1161 c896fe29 bellard
{
1162 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
1163 c896fe29 bellard
}
1164 c896fe29 bellard
1165 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1166 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1167 c896fe29 bellard
{
1168 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1169 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1170 c896fe29 bellard
#else
1171 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld8u, ret, addr, TCGV_HIGH(addr), mem_index);
1172 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1173 c896fe29 bellard
#endif
1174 c896fe29 bellard
}
1175 c896fe29 bellard
1176 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1177 c896fe29 bellard
{
1178 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1179 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1180 c896fe29 bellard
#else
1181 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld8s, ret, addr, TCGV_HIGH(addr), mem_index);
1182 21fc3cfc pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1183 c896fe29 bellard
#endif
1184 c896fe29 bellard
}
1185 c896fe29 bellard
1186 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1187 c896fe29 bellard
{
1188 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1189 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1190 c896fe29 bellard
#else
1191 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld16u, ret, addr, TCGV_HIGH(addr), mem_index);
1192 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1193 c896fe29 bellard
#endif
1194 c896fe29 bellard
}
1195 c896fe29 bellard
1196 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1197 c896fe29 bellard
{
1198 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1199 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1200 c896fe29 bellard
#else
1201 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld16s, ret, addr, TCGV_HIGH(addr), mem_index);
1202 21fc3cfc pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1203 c896fe29 bellard
#endif
1204 c896fe29 bellard
}
1205 c896fe29 bellard
1206 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1207 c896fe29 bellard
{
1208 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1209 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1210 c896fe29 bellard
#else
1211 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index);
1212 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1213 c896fe29 bellard
#endif
1214 c896fe29 bellard
}
1215 c896fe29 bellard
1216 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1217 c896fe29 bellard
{
1218 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1219 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1220 c896fe29 bellard
#else
1221 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index);
1222 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1223 c896fe29 bellard
#endif
1224 c896fe29 bellard
}
1225 c896fe29 bellard
1226 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index)
1227 c896fe29 bellard
{
1228 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1229 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), addr, mem_index);
1230 c896fe29 bellard
#else
1231 ac56dd48 pbrook
    tcg_gen_op5i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret),
1232 ac56dd48 pbrook
                 addr, TCGV_HIGH(addr), mem_index);
1233 c896fe29 bellard
#endif
1234 c896fe29 bellard
}
1235 c896fe29 bellard
1236 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1237 c896fe29 bellard
{
1238 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1239 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index);
1240 c896fe29 bellard
#else
1241 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st8, arg, addr, TCGV_HIGH(addr), mem_index);
1242 c896fe29 bellard
#endif
1243 c896fe29 bellard
}
1244 c896fe29 bellard
1245 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1246 c896fe29 bellard
{
1247 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1248 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index);
1249 c896fe29 bellard
#else
1250 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st16, arg, addr, TCGV_HIGH(addr), mem_index);
1251 c896fe29 bellard
#endif
1252 c896fe29 bellard
}
1253 c896fe29 bellard
1254 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1255 c896fe29 bellard
{
1256 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1257 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index);
1258 c896fe29 bellard
#else
1259 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st32, arg, addr, TCGV_HIGH(addr), mem_index);
1260 c896fe29 bellard
#endif
1261 c896fe29 bellard
}
1262 c896fe29 bellard
1263 ac56dd48 pbrook
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
1264 c896fe29 bellard
{
1265 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1266 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), addr, mem_index);
1267 c896fe29 bellard
#else
1268 ac56dd48 pbrook
    tcg_gen_op5i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg),
1269 ac56dd48 pbrook
                 addr, TCGV_HIGH(addr), mem_index);
1270 c896fe29 bellard
#endif
1271 c896fe29 bellard
}
1272 c896fe29 bellard
1273 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i32
1274 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i32
1275 f8422f52 blueswir1
1276 c896fe29 bellard
#else /* TCG_TARGET_REG_BITS == 32 */
1277 c896fe29 bellard
1278 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1279 c896fe29 bellard
{
1280 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1281 c896fe29 bellard
}
1282 c896fe29 bellard
1283 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1284 c896fe29 bellard
{
1285 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1286 c896fe29 bellard
}
1287 c896fe29 bellard
1288 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1289 c896fe29 bellard
{
1290 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1291 c896fe29 bellard
}
1292 c896fe29 bellard
1293 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1294 c896fe29 bellard
{
1295 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1296 c896fe29 bellard
}
1297 c896fe29 bellard
1298 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1299 c896fe29 bellard
{
1300 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1301 c896fe29 bellard
}
1302 c896fe29 bellard
1303 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1304 c896fe29 bellard
{
1305 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32s, ret, addr, mem_index);
1306 c896fe29 bellard
}
1307 c896fe29 bellard
1308 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index)
1309 c896fe29 bellard
{
1310 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld64, ret, addr, mem_index);
1311 c896fe29 bellard
}
1312 c896fe29 bellard
1313 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1314 c896fe29 bellard
{
1315 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index);
1316 c896fe29 bellard
}
1317 c896fe29 bellard
1318 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1319 c896fe29 bellard
{
1320 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index);
1321 c896fe29 bellard
}
1322 c896fe29 bellard
1323 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1324 c896fe29 bellard
{
1325 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index);
1326 c896fe29 bellard
}
1327 c896fe29 bellard
1328 ac56dd48 pbrook
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
1329 c896fe29 bellard
{
1330 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st64, arg, addr, mem_index);
1331 c896fe29 bellard
}
1332 c896fe29 bellard
1333 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i64
1334 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i64
1335 f8422f52 blueswir1
1336 c896fe29 bellard
#endif /* TCG_TARGET_REG_BITS != 32 */
1337 f8422f52 blueswir1
1338 f8422f52 blueswir1
#if TARGET_LONG_BITS == 64
1339 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I64
1340 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i64
1341 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i64
1342 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
1343 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
1344 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
1345 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
1346 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
1347 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
1348 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i64
1349 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i64
1350 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i64
1351 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st32_i64
1352 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i64
1353 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i64
1354 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i64
1355 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i64
1356 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i64
1357 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i64
1358 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i64
1359 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i64
1360 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i64
1361 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i64
1362 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i64
1363 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i64
1364 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i64
1365 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i64
1366 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i64
1367 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i64
1368 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i64
1369 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
1370 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i64
1371 a98824ac blueswir1
#define tcg_const_tl tcg_const_i64
1372 f8422f52 blueswir1
#else
1373 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I32
1374 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i32
1375 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i32
1376 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1377 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1378 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1379 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1380 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
1381 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
1382 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i32
1383 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i32
1384 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i32
1385 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st_i32
1386 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i32
1387 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i32
1388 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i32
1389 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i32
1390 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i32
1391 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i32
1392 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i32
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#define tcg_gen_or_tl tcg_gen_or_i32
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#define tcg_gen_ori_tl tcg_gen_ori_i32
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#define tcg_gen_xor_tl tcg_gen_xor_i32
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#define tcg_gen_xori_tl tcg_gen_xori_i32
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#define tcg_gen_shl_tl tcg_gen_shl_i32
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#define tcg_gen_shli_tl tcg_gen_shli_i32
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#define tcg_gen_shr_tl tcg_gen_shr_i32
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#define tcg_gen_shri_tl tcg_gen_shri_i32
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#define tcg_gen_sar_tl tcg_gen_sar_i32
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#define tcg_gen_sari_tl tcg_gen_sari_i32
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#define tcg_gen_brcond_tl tcg_gen_brcond_i32
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#define tcg_gen_discard_tl tcg_gen_discard_i32
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#define tcg_const_tl tcg_const_i32
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#endif