Revision cf6d64bf
| b/hw/apic.c | ||
|---|---|---|
| 94 | 94 |
#define MSI_ADDR_BASE 0xfee00000 |
| 95 | 95 |
#define MSI_ADDR_SIZE 0x100000 |
| 96 | 96 |
|
| 97 |
typedef struct APICState {
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| 97 |
struct APICState {
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| 98 | 98 |
CPUState *cpu_env; |
| 99 | 99 |
uint32_t apicbase; |
| 100 | 100 |
uint8_t id; |
| ... | ... | |
| 118 | 118 |
QEMUTimer *timer; |
| 119 | 119 |
int sipi_vector; |
| 120 | 120 |
int wait_for_sipi; |
| 121 |
} APICState;
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| 121 |
}; |
|
| 122 | 122 |
|
| 123 | 123 |
static int apic_io_memory; |
| 124 | 124 |
static APICState *local_apics[MAX_APICS + 1]; |
| ... | ... | |
| 167 | 167 |
return !!(tab[i] & mask); |
| 168 | 168 |
} |
| 169 | 169 |
|
| 170 |
static void apic_local_deliver(CPUState *env, int vector)
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static void apic_local_deliver(APICState *s, int vector)
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| 171 | 171 |
{
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APICState *s = env->apic_state; |
|
| 173 | 172 |
uint32_t lvt = s->lvt[vector]; |
| 174 | 173 |
int trigger_mode; |
| 175 | 174 |
|
| ... | ... | |
| 180 | 179 |
|
| 181 | 180 |
switch ((lvt >> 8) & 7) {
|
| 182 | 181 |
case APIC_DM_SMI: |
| 183 |
cpu_interrupt(env, CPU_INTERRUPT_SMI); |
|
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
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| 184 | 183 |
break; |
| 185 | 184 |
|
| 186 | 185 |
case APIC_DM_NMI: |
| 187 |
cpu_interrupt(env, CPU_INTERRUPT_NMI); |
|
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
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|
| 188 | 187 |
break; |
| 189 | 188 |
|
| 190 | 189 |
case APIC_DM_EXTINT: |
| 191 |
cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
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|
| 192 | 191 |
break; |
| 193 | 192 |
|
| 194 | 193 |
case APIC_DM_FIXED: |
| ... | ... | |
| 200 | 199 |
} |
| 201 | 200 |
} |
| 202 | 201 |
|
| 203 |
void apic_deliver_pic_intr(CPUState *env, int level)
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void apic_deliver_pic_intr(APICState *s, int level)
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|
| 204 | 203 |
{
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if (level) |
|
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apic_local_deliver(env, APIC_LVT_LINT0); |
|
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else {
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APICState *s = env->apic_state; |
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if (level) {
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apic_local_deliver(s, APIC_LVT_LINT0); |
|
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} else {
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| 209 | 207 |
uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
| 210 | 208 |
|
| 211 | 209 |
switch ((lvt >> 8) & 7) {
|
| ... | ... | |
| 215 | 213 |
reset_bit(s->irr, lvt & 0xff); |
| 216 | 214 |
/* fall through */ |
| 217 | 215 |
case APIC_DM_EXTINT: |
| 218 |
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
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| 219 | 217 |
break; |
| 220 | 218 |
} |
| 221 | 219 |
} |
| ... | ... | |
| 591 | 589 |
trigger_mode); |
| 592 | 590 |
} |
| 593 | 591 |
|
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int apic_get_interrupt(CPUState *env)
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int apic_get_interrupt(APICState *s)
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| 595 | 593 |
{
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APICState *s = env->apic_state; |
|
| 597 | 594 |
int intno; |
| 598 | 595 |
|
| 599 | 596 |
/* if the APIC is installed or enabled, we let the 8259 handle the |
| ... | ... | |
| 615 | 612 |
return intno; |
| 616 | 613 |
} |
| 617 | 614 |
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int apic_accept_pic_intr(CPUState *env)
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int apic_accept_pic_intr(APICState *s)
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| 619 | 616 |
{
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APICState *s = env->apic_state; |
|
| 621 | 617 |
uint32_t lvt0; |
| 622 | 618 |
|
| 623 | 619 |
if (!s) |
| ... | ... | |
| 679 | 675 |
{
|
| 680 | 676 |
APICState *s = opaque; |
| 681 | 677 |
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apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
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apic_local_deliver(s, APIC_LVT_TIMER); |
|
| 683 | 679 |
apic_timer_update(s, s->next_time); |
| 684 | 680 |
} |
| 685 | 681 |
|
| b/hw/apic.h | ||
|---|---|---|
| 1 | 1 |
#ifndef APIC_H |
| 2 | 2 |
#define APIC_H |
| 3 | 3 |
|
| 4 |
/* apic.c */ |
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| 5 |
typedef struct APICState APICState; |
|
| 4 | 6 |
void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, |
| 5 | 7 |
uint8_t delivery_mode, |
| 6 | 8 |
uint8_t vector_num, uint8_t polarity, |
| 7 | 9 |
uint8_t trigger_mode); |
| 8 | 10 |
int apic_init(CPUState *env); |
| 9 |
int apic_accept_pic_intr(CPUState *env);
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void apic_deliver_pic_intr(CPUState *env, int level);
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int apic_get_interrupt(CPUState *env);
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int apic_accept_pic_intr(APICState *s);
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void apic_deliver_pic_intr(APICState *s, int level);
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int apic_get_interrupt(APICState *s);
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| 12 | 14 |
void apic_reset_irq_delivered(void); |
| 13 | 15 |
int apic_get_irq_delivered(void); |
| 14 | 16 |
|
| b/hw/pc.c | ||
|---|---|---|
| 145 | 145 |
{
|
| 146 | 146 |
int intno; |
| 147 | 147 |
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| 148 |
intno = apic_get_interrupt(env); |
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intno = apic_get_interrupt(env->apic_state);
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|
| 149 | 149 |
if (intno >= 0) {
|
| 150 | 150 |
/* set irq request if a PIC irq is still pending */ |
| 151 | 151 |
/* XXX: improve that */ |
| ... | ... | |
| 153 | 153 |
return intno; |
| 154 | 154 |
} |
| 155 | 155 |
/* read the irq from the PIC */ |
| 156 |
if (!apic_accept_pic_intr(env))
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| 156 |
if (!apic_accept_pic_intr(env->apic_state)) {
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|
| 157 | 157 |
return -1; |
| 158 |
} |
|
| 158 | 159 |
|
| 159 | 160 |
intno = pic_read_irq(isa_pic); |
| 160 | 161 |
return intno; |
| ... | ... | |
| 167 | 168 |
DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
|
| 168 | 169 |
if (env->apic_state) {
|
| 169 | 170 |
while (env) {
|
| 170 |
if (apic_accept_pic_intr(env)) |
|
| 171 |
apic_deliver_pic_intr(env, level); |
|
| 171 |
if (apic_accept_pic_intr(env->apic_state)) {
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| 172 |
apic_deliver_pic_intr(env->apic_state, level); |
|
| 173 |
} |
|
| 172 | 174 |
env = env->next_cpu; |
| 173 | 175 |
} |
| 174 | 176 |
} else {
|
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