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/*
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* APIC support
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "apic.h" |
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#include "pci.h" |
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#include "msix.h" |
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#include "qemu-timer.h" |
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#include "host-utils.h" |
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#include "kvm.h" |
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//#define DEBUG_APIC
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//#define DEBUG_COALESCING
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#ifdef DEBUG_APIC
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#define DPRINTF(fmt, ...) \
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do { printf("apic: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#ifdef DEBUG_COALESCING
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#define DPRINTF_C(fmt, ...) \
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do { printf("apic: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF_C(fmt, ...)
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#endif
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/* APIC Local Vector Table */
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#define APIC_LVT_TIMER 0 |
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#define APIC_LVT_THERMAL 1 |
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#define APIC_LVT_PERFORM 2 |
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#define APIC_LVT_LINT0 3 |
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#define APIC_LVT_LINT1 4 |
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#define APIC_LVT_ERROR 5 |
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#define APIC_LVT_NB 6 |
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/* APIC delivery modes */
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#define APIC_DM_FIXED 0 |
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#define APIC_DM_LOWPRI 1 |
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#define APIC_DM_SMI 2 |
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#define APIC_DM_NMI 4 |
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#define APIC_DM_INIT 5 |
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#define APIC_DM_SIPI 6 |
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#define APIC_DM_EXTINT 7 |
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/* APIC destination mode */
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#define APIC_DESTMODE_FLAT 0xf |
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#define APIC_DESTMODE_CLUSTER 1 |
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#define APIC_TRIGGER_EDGE 0 |
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#define APIC_TRIGGER_LEVEL 1 |
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#define APIC_LVT_TIMER_PERIODIC (1<<17) |
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#define APIC_LVT_MASKED (1<<16) |
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#define APIC_LVT_LEVEL_TRIGGER (1<<15) |
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#define APIC_LVT_REMOTE_IRR (1<<14) |
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#define APIC_INPUT_POLARITY (1<<13) |
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#define APIC_SEND_PENDING (1<<12) |
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#define ESR_ILLEGAL_ADDRESS (1 << 7) |
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#define APIC_SV_ENABLE (1 << 8) |
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#define MAX_APICS 255 |
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#define MAX_APIC_WORDS 8 |
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/* Intel APIC constants: from include/asm/msidef.h */
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#define MSI_DATA_VECTOR_SHIFT 0 |
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#define MSI_DATA_VECTOR_MASK 0x000000ff |
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#define MSI_DATA_DELIVERY_MODE_SHIFT 8 |
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#define MSI_DATA_TRIGGER_SHIFT 15 |
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#define MSI_DATA_LEVEL_SHIFT 14 |
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#define MSI_ADDR_DEST_MODE_SHIFT 2 |
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#define MSI_ADDR_DEST_ID_SHIFT 12 |
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#define MSI_ADDR_DEST_ID_MASK 0x00ffff0 |
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#define MSI_ADDR_BASE 0xfee00000 |
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#define MSI_ADDR_SIZE 0x100000 |
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struct APICState {
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CPUState *cpu_env; |
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uint32_t apicbase; |
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uint8_t id; |
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uint8_t arb_id; |
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uint8_t tpr; |
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uint32_t spurious_vec; |
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uint8_t log_dest; |
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uint8_t dest_mode; |
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uint32_t isr[8]; /* in service register */ |
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uint32_t tmr[8]; /* trigger mode register */ |
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uint32_t irr[8]; /* interrupt request register */ |
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uint32_t lvt[APIC_LVT_NB]; |
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uint32_t esr; /* error register */
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uint32_t icr[2];
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uint32_t divide_conf; |
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int count_shift;
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uint32_t initial_count; |
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int64_t initial_count_load_time, next_time; |
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uint32_t idx; |
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QEMUTimer *timer; |
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int sipi_vector;
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int wait_for_sipi;
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}; |
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static int apic_io_memory; |
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static APICState *local_apics[MAX_APICS + 1]; |
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static int last_apic_idx = 0; |
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static int apic_irq_delivered; |
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static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
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static void apic_update_irq(APICState *s); |
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static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
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uint8_t dest, uint8_t dest_mode); |
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/* Find first bit starting from msb */
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static int fls_bit(uint32_t value) |
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{ |
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return 31 - clz32(value); |
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} |
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/* Find first bit starting from lsb */
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static int ffs_bit(uint32_t value) |
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{ |
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return ctz32(value);
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} |
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static inline void set_bit(uint32_t *tab, int index) |
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{ |
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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tab[i] |= mask; |
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} |
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static inline void reset_bit(uint32_t *tab, int index) |
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{ |
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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tab[i] &= ~mask; |
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} |
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static inline int get_bit(uint32_t *tab, int index) |
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{ |
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f); |
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return !!(tab[i] & mask);
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} |
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static void apic_local_deliver(APICState *s, int vector) |
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{ |
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uint32_t lvt = s->lvt[vector]; |
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int trigger_mode;
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DPRINTF("%s: vector %d delivery mode %d\n", __func__, vector,
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(lvt >> 8) & 7); |
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if (lvt & APIC_LVT_MASKED)
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return;
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switch ((lvt >> 8) & 7) { |
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case APIC_DM_SMI:
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); |
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break;
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case APIC_DM_NMI:
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); |
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break;
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case APIC_DM_EXTINT:
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
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break;
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case APIC_DM_FIXED:
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trigger_mode = APIC_TRIGGER_EDGE; |
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if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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(lvt & APIC_LVT_LEVEL_TRIGGER)) |
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trigger_mode = APIC_TRIGGER_LEVEL; |
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apic_set_irq(s, lvt & 0xff, trigger_mode);
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} |
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} |
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void apic_deliver_pic_intr(APICState *s, int level) |
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{ |
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if (level) {
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apic_local_deliver(s, APIC_LVT_LINT0); |
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} else {
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uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
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switch ((lvt >> 8) & 7) { |
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case APIC_DM_FIXED:
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if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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break;
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reset_bit(s->irr, lvt & 0xff);
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/* fall through */
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case APIC_DM_EXTINT:
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cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
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break;
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} |
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} |
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} |
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#define foreach_apic(apic, deliver_bitmask, code) \
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{\ |
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int __i, __j, __mask;\
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for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
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__mask = deliver_bitmask[__i];\ |
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if (__mask) {\
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for(__j = 0; __j < 32; __j++) {\ |
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if (__mask & (1 << __j)) {\ |
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apic = local_apics[__i * 32 + __j];\
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if (apic) {\
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code;\ |
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}\ |
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}\ |
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}\ |
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}\ |
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}\ |
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} |
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static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
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uint8_t delivery_mode, |
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uint8_t vector_num, uint8_t polarity, |
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uint8_t trigger_mode) |
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{ |
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APICState *apic_iter; |
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switch (delivery_mode) {
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case APIC_DM_LOWPRI:
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/* XXX: search for focus processor, arbitration */
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{ |
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int i, d;
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d = -1;
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for(i = 0; i < MAX_APIC_WORDS; i++) { |
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if (deliver_bitmask[i]) {
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d = i * 32 + ffs_bit(deliver_bitmask[i]);
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break;
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} |
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} |
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if (d >= 0) { |
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apic_iter = local_apics[d]; |
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if (apic_iter) {
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apic_set_irq(apic_iter, vector_num, trigger_mode); |
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} |
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} |
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} |
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return;
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case APIC_DM_FIXED:
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break;
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case APIC_DM_SMI:
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); |
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return;
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case APIC_DM_NMI:
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); |
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return;
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case APIC_DM_INIT:
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/* normal INIT IPI sent to processors */
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foreach_apic(apic_iter, deliver_bitmask, |
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cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); |
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return;
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case APIC_DM_EXTINT:
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/* handled in I/O APIC code */
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break;
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default:
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return;
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} |
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foreach_apic(apic_iter, deliver_bitmask, |
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apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
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} |
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
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uint8_t delivery_mode, uint8_t vector_num, |
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uint8_t polarity, uint8_t trigger_mode) |
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{ |
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uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
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DPRINTF("%s: dest %d dest_mode %d delivery_mode %d vector %d"
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" polarity %d trigger_mode %d\n", __func__, dest, dest_mode,
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delivery_mode, vector_num, polarity, trigger_mode); |
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
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apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
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trigger_mode); |
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} |
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void cpu_set_apic_base(CPUState *env, uint64_t val)
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{ |
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APICState *s = env->apic_state; |
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DPRINTF("cpu_set_apic_base: %016" PRIx64 "\n", val); |
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if (!s)
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return;
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s->apicbase = (val & 0xfffff000) |
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(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
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/* if disabled, cannot be enabled again */
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if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
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env->cpuid_features &= ~CPUID_APIC; |
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s->spurious_vec &= ~APIC_SV_ENABLE; |
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} |
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} |
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uint64_t cpu_get_apic_base(CPUState *env) |
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{ |
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APICState *s = env->apic_state; |
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DPRINTF("cpu_get_apic_base: %016" PRIx64 "\n", |
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s ? (uint64_t)s->apicbase: 0);
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return s ? s->apicbase : 0; |
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} |
338 |
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void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
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{ |
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APICState *s = env->apic_state; |
342 |
if (!s)
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return;
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s->tpr = (val & 0x0f) << 4; |
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apic_update_irq(s); |
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} |
347 |
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uint8_t cpu_get_apic_tpr(CPUX86State *env) |
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{ |
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APICState *s = env->apic_state; |
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return s ? s->tpr >> 4 : 0; |
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} |
353 |
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/* return -1 if no bit is set */
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static int get_highest_priority_int(uint32_t *tab) |
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{ |
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int i;
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for(i = 7; i >= 0; i--) { |
359 |
if (tab[i] != 0) { |
360 |
return i * 32 + fls_bit(tab[i]); |
361 |
} |
362 |
} |
363 |
return -1; |
364 |
} |
365 |
|
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static int apic_get_ppr(APICState *s) |
367 |
{ |
368 |
int tpr, isrv, ppr;
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tpr = (s->tpr >> 4);
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isrv = get_highest_priority_int(s->isr); |
372 |
if (isrv < 0) |
373 |
isrv = 0;
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isrv >>= 4;
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if (tpr >= isrv)
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ppr = s->tpr; |
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else
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ppr = isrv << 4;
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return ppr;
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} |
381 |
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static int apic_get_arb_pri(APICState *s) |
383 |
{ |
384 |
/* XXX: arbitration */
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return 0; |
386 |
} |
387 |
|
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/* signal the CPU if an irq is pending */
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static void apic_update_irq(APICState *s) |
390 |
{ |
391 |
int irrv, ppr;
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if (!(s->spurious_vec & APIC_SV_ENABLE))
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return;
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irrv = get_highest_priority_int(s->irr); |
395 |
if (irrv < 0) |
396 |
return;
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ppr = apic_get_ppr(s); |
398 |
if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) |
399 |
return;
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cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
401 |
} |
402 |
|
403 |
void apic_reset_irq_delivered(void) |
404 |
{ |
405 |
DPRINTF_C("%s: old coalescing %d\n", __func__, apic_irq_delivered);
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apic_irq_delivered = 0;
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} |
408 |
|
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int apic_get_irq_delivered(void) |
410 |
{ |
411 |
DPRINTF_C("%s: returning coalescing %d\n", __func__, apic_irq_delivered);
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412 |
return apic_irq_delivered;
|
413 |
} |
414 |
|
415 |
static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
416 |
{ |
417 |
apic_irq_delivered += !get_bit(s->irr, vector_num); |
418 |
DPRINTF_C("%s: coalescing %d\n", __func__, apic_irq_delivered);
|
419 |
|
420 |
set_bit(s->irr, vector_num); |
421 |
if (trigger_mode)
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set_bit(s->tmr, vector_num); |
423 |
else
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reset_bit(s->tmr, vector_num); |
425 |
apic_update_irq(s); |
426 |
} |
427 |
|
428 |
static void apic_eoi(APICState *s) |
429 |
{ |
430 |
int isrv;
|
431 |
isrv = get_highest_priority_int(s->isr); |
432 |
if (isrv < 0) |
433 |
return;
|
434 |
reset_bit(s->isr, isrv); |
435 |
/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
|
436 |
set the remote IRR bit for level triggered interrupts. */
|
437 |
apic_update_irq(s); |
438 |
} |
439 |
|
440 |
static int apic_find_dest(uint8_t dest) |
441 |
{ |
442 |
APICState *apic = local_apics[dest]; |
443 |
int i;
|
444 |
|
445 |
if (apic && apic->id == dest)
|
446 |
return dest; /* shortcut in case apic->id == apic->idx */ |
447 |
|
448 |
for (i = 0; i < MAX_APICS; i++) { |
449 |
apic = local_apics[i]; |
450 |
if (apic && apic->id == dest)
|
451 |
return i;
|
452 |
} |
453 |
|
454 |
return -1; |
455 |
} |
456 |
|
457 |
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
458 |
uint8_t dest, uint8_t dest_mode) |
459 |
{ |
460 |
APICState *apic_iter; |
461 |
int i;
|
462 |
|
463 |
if (dest_mode == 0) { |
464 |
if (dest == 0xff) { |
465 |
memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); |
466 |
} else {
|
467 |
int idx = apic_find_dest(dest);
|
468 |
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
469 |
if (idx >= 0) |
470 |
set_bit(deliver_bitmask, idx); |
471 |
} |
472 |
} else {
|
473 |
/* XXX: cluster mode */
|
474 |
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
475 |
for(i = 0; i < MAX_APICS; i++) { |
476 |
apic_iter = local_apics[i]; |
477 |
if (apic_iter) {
|
478 |
if (apic_iter->dest_mode == 0xf) { |
479 |
if (dest & apic_iter->log_dest)
|
480 |
set_bit(deliver_bitmask, i); |
481 |
} else if (apic_iter->dest_mode == 0x0) { |
482 |
if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && |
483 |
(dest & apic_iter->log_dest & 0x0f)) {
|
484 |
set_bit(deliver_bitmask, i); |
485 |
} |
486 |
} |
487 |
} |
488 |
} |
489 |
} |
490 |
} |
491 |
|
492 |
|
493 |
void apic_init_reset(CPUState *env)
|
494 |
{ |
495 |
APICState *s = env->apic_state; |
496 |
int i;
|
497 |
|
498 |
if (!s)
|
499 |
return;
|
500 |
|
501 |
s->tpr = 0;
|
502 |
s->spurious_vec = 0xff;
|
503 |
s->log_dest = 0;
|
504 |
s->dest_mode = 0xf;
|
505 |
memset(s->isr, 0, sizeof(s->isr)); |
506 |
memset(s->tmr, 0, sizeof(s->tmr)); |
507 |
memset(s->irr, 0, sizeof(s->irr)); |
508 |
for(i = 0; i < APIC_LVT_NB; i++) |
509 |
s->lvt[i] = 1 << 16; /* mask LVT */ |
510 |
s->esr = 0;
|
511 |
memset(s->icr, 0, sizeof(s->icr)); |
512 |
s->divide_conf = 0;
|
513 |
s->count_shift = 0;
|
514 |
s->initial_count = 0;
|
515 |
s->initial_count_load_time = 0;
|
516 |
s->next_time = 0;
|
517 |
s->wait_for_sipi = 1;
|
518 |
|
519 |
env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP); |
520 |
} |
521 |
|
522 |
static void apic_startup(APICState *s, int vector_num) |
523 |
{ |
524 |
s->sipi_vector = vector_num; |
525 |
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); |
526 |
} |
527 |
|
528 |
void apic_sipi(CPUState *env)
|
529 |
{ |
530 |
APICState *s = env->apic_state; |
531 |
|
532 |
cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI); |
533 |
|
534 |
if (!s->wait_for_sipi)
|
535 |
return;
|
536 |
|
537 |
env->eip = 0;
|
538 |
cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12, |
539 |
env->segs[R_CS].limit, env->segs[R_CS].flags); |
540 |
env->halted = 0;
|
541 |
s->wait_for_sipi = 0;
|
542 |
} |
543 |
|
544 |
static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, |
545 |
uint8_t delivery_mode, uint8_t vector_num, |
546 |
uint8_t polarity, uint8_t trigger_mode) |
547 |
{ |
548 |
uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
549 |
int dest_shorthand = (s->icr[0] >> 18) & 3; |
550 |
APICState *apic_iter; |
551 |
|
552 |
switch (dest_shorthand) {
|
553 |
case 0: |
554 |
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
555 |
break;
|
556 |
case 1: |
557 |
memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); |
558 |
set_bit(deliver_bitmask, s->idx); |
559 |
break;
|
560 |
case 2: |
561 |
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
562 |
break;
|
563 |
case 3: |
564 |
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
565 |
reset_bit(deliver_bitmask, s->idx); |
566 |
break;
|
567 |
} |
568 |
|
569 |
switch (delivery_mode) {
|
570 |
case APIC_DM_INIT:
|
571 |
{ |
572 |
int trig_mode = (s->icr[0] >> 15) & 1; |
573 |
int level = (s->icr[0] >> 14) & 1; |
574 |
if (level == 0 && trig_mode == 1) { |
575 |
foreach_apic(apic_iter, deliver_bitmask, |
576 |
apic_iter->arb_id = apic_iter->id ); |
577 |
return;
|
578 |
} |
579 |
} |
580 |
break;
|
581 |
|
582 |
case APIC_DM_SIPI:
|
583 |
foreach_apic(apic_iter, deliver_bitmask, |
584 |
apic_startup(apic_iter, vector_num) ); |
585 |
return;
|
586 |
} |
587 |
|
588 |
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
589 |
trigger_mode); |
590 |
} |
591 |
|
592 |
int apic_get_interrupt(APICState *s)
|
593 |
{ |
594 |
int intno;
|
595 |
|
596 |
/* if the APIC is installed or enabled, we let the 8259 handle the
|
597 |
IRQs */
|
598 |
if (!s)
|
599 |
return -1; |
600 |
if (!(s->spurious_vec & APIC_SV_ENABLE))
|
601 |
return -1; |
602 |
|
603 |
/* XXX: spurious IRQ handling */
|
604 |
intno = get_highest_priority_int(s->irr); |
605 |
if (intno < 0) |
606 |
return -1; |
607 |
if (s->tpr && intno <= s->tpr)
|
608 |
return s->spurious_vec & 0xff; |
609 |
reset_bit(s->irr, intno); |
610 |
set_bit(s->isr, intno); |
611 |
apic_update_irq(s); |
612 |
return intno;
|
613 |
} |
614 |
|
615 |
int apic_accept_pic_intr(APICState *s)
|
616 |
{ |
617 |
uint32_t lvt0; |
618 |
|
619 |
if (!s)
|
620 |
return -1; |
621 |
|
622 |
lvt0 = s->lvt[APIC_LVT_LINT0]; |
623 |
|
624 |
if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
625 |
(lvt0 & APIC_LVT_MASKED) == 0)
|
626 |
return 1; |
627 |
|
628 |
return 0; |
629 |
} |
630 |
|
631 |
static uint32_t apic_get_current_count(APICState *s)
|
632 |
{ |
633 |
int64_t d; |
634 |
uint32_t val; |
635 |
d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> |
636 |
s->count_shift; |
637 |
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
638 |
/* periodic */
|
639 |
val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
640 |
} else {
|
641 |
if (d >= s->initial_count)
|
642 |
val = 0;
|
643 |
else
|
644 |
val = s->initial_count - d; |
645 |
} |
646 |
return val;
|
647 |
} |
648 |
|
649 |
static void apic_timer_update(APICState *s, int64_t current_time) |
650 |
{ |
651 |
int64_t next_time, d; |
652 |
|
653 |
if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
|
654 |
d = (current_time - s->initial_count_load_time) >> |
655 |
s->count_shift; |
656 |
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
657 |
if (!s->initial_count)
|
658 |
goto no_timer;
|
659 |
d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
660 |
} else {
|
661 |
if (d >= s->initial_count)
|
662 |
goto no_timer;
|
663 |
d = (uint64_t)s->initial_count + 1;
|
664 |
} |
665 |
next_time = s->initial_count_load_time + (d << s->count_shift); |
666 |
qemu_mod_timer(s->timer, next_time); |
667 |
s->next_time = next_time; |
668 |
} else {
|
669 |
no_timer:
|
670 |
qemu_del_timer(s->timer); |
671 |
} |
672 |
} |
673 |
|
674 |
static void apic_timer(void *opaque) |
675 |
{ |
676 |
APICState *s = opaque; |
677 |
|
678 |
apic_local_deliver(s, APIC_LVT_TIMER); |
679 |
apic_timer_update(s, s->next_time); |
680 |
} |
681 |
|
682 |
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
683 |
{ |
684 |
return 0; |
685 |
} |
686 |
|
687 |
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
688 |
{ |
689 |
return 0; |
690 |
} |
691 |
|
692 |
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
693 |
{ |
694 |
} |
695 |
|
696 |
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
697 |
{ |
698 |
} |
699 |
|
700 |
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
701 |
{ |
702 |
CPUState *env; |
703 |
APICState *s; |
704 |
uint32_t val; |
705 |
int index;
|
706 |
|
707 |
env = cpu_single_env; |
708 |
if (!env)
|
709 |
return 0; |
710 |
s = env->apic_state; |
711 |
|
712 |
index = (addr >> 4) & 0xff; |
713 |
switch(index) {
|
714 |
case 0x02: /* id */ |
715 |
val = s->id << 24;
|
716 |
break;
|
717 |
case 0x03: /* version */ |
718 |
val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ |
719 |
break;
|
720 |
case 0x08: |
721 |
val = s->tpr; |
722 |
break;
|
723 |
case 0x09: |
724 |
val = apic_get_arb_pri(s); |
725 |
break;
|
726 |
case 0x0a: |
727 |
/* ppr */
|
728 |
val = apic_get_ppr(s); |
729 |
break;
|
730 |
case 0x0b: |
731 |
val = 0;
|
732 |
break;
|
733 |
case 0x0d: |
734 |
val = s->log_dest << 24;
|
735 |
break;
|
736 |
case 0x0e: |
737 |
val = s->dest_mode << 28;
|
738 |
break;
|
739 |
case 0x0f: |
740 |
val = s->spurious_vec; |
741 |
break;
|
742 |
case 0x10 ... 0x17: |
743 |
val = s->isr[index & 7];
|
744 |
break;
|
745 |
case 0x18 ... 0x1f: |
746 |
val = s->tmr[index & 7];
|
747 |
break;
|
748 |
case 0x20 ... 0x27: |
749 |
val = s->irr[index & 7];
|
750 |
break;
|
751 |
case 0x28: |
752 |
val = s->esr; |
753 |
break;
|
754 |
case 0x30: |
755 |
case 0x31: |
756 |
val = s->icr[index & 1];
|
757 |
break;
|
758 |
case 0x32 ... 0x37: |
759 |
val = s->lvt[index - 0x32];
|
760 |
break;
|
761 |
case 0x38: |
762 |
val = s->initial_count; |
763 |
break;
|
764 |
case 0x39: |
765 |
val = apic_get_current_count(s); |
766 |
break;
|
767 |
case 0x3e: |
768 |
val = s->divide_conf; |
769 |
break;
|
770 |
default:
|
771 |
s->esr |= ESR_ILLEGAL_ADDRESS; |
772 |
val = 0;
|
773 |
break;
|
774 |
} |
775 |
DPRINTF("read: " TARGET_FMT_plx " = %08x\n", addr, val); |
776 |
return val;
|
777 |
} |
778 |
|
779 |
static void apic_send_msi(target_phys_addr_t addr, uint32 data) |
780 |
{ |
781 |
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT; |
782 |
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT; |
783 |
uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
|
784 |
uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
|
785 |
uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
|
786 |
/* XXX: Ignore redirection hint. */
|
787 |
apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
|
788 |
} |
789 |
|
790 |
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
791 |
{ |
792 |
CPUState *env; |
793 |
APICState *s; |
794 |
int index = (addr >> 4) & 0xff; |
795 |
if (addr > 0xfff || !index) { |
796 |
/* MSI and MMIO APIC are at the same memory location,
|
797 |
* but actually not on the global bus: MSI is on PCI bus
|
798 |
* APIC is connected directly to the CPU.
|
799 |
* Mapping them on the global bus happens to work because
|
800 |
* MSI registers are reserved in APIC MMIO and vice versa. */
|
801 |
apic_send_msi(addr, val); |
802 |
return;
|
803 |
} |
804 |
|
805 |
env = cpu_single_env; |
806 |
if (!env)
|
807 |
return;
|
808 |
s = env->apic_state; |
809 |
|
810 |
DPRINTF("write: " TARGET_FMT_plx " = %08x\n", addr, val); |
811 |
|
812 |
switch(index) {
|
813 |
case 0x02: |
814 |
s->id = (val >> 24);
|
815 |
break;
|
816 |
case 0x03: |
817 |
break;
|
818 |
case 0x08: |
819 |
s->tpr = val; |
820 |
apic_update_irq(s); |
821 |
break;
|
822 |
case 0x09: |
823 |
case 0x0a: |
824 |
break;
|
825 |
case 0x0b: /* EOI */ |
826 |
apic_eoi(s); |
827 |
break;
|
828 |
case 0x0d: |
829 |
s->log_dest = val >> 24;
|
830 |
break;
|
831 |
case 0x0e: |
832 |
s->dest_mode = val >> 28;
|
833 |
break;
|
834 |
case 0x0f: |
835 |
s->spurious_vec = val & 0x1ff;
|
836 |
apic_update_irq(s); |
837 |
break;
|
838 |
case 0x10 ... 0x17: |
839 |
case 0x18 ... 0x1f: |
840 |
case 0x20 ... 0x27: |
841 |
case 0x28: |
842 |
break;
|
843 |
case 0x30: |
844 |
s->icr[0] = val;
|
845 |
apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
846 |
(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
847 |
(s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); |
848 |
break;
|
849 |
case 0x31: |
850 |
s->icr[1] = val;
|
851 |
break;
|
852 |
case 0x32 ... 0x37: |
853 |
{ |
854 |
int n = index - 0x32; |
855 |
s->lvt[n] = val; |
856 |
if (n == APIC_LVT_TIMER)
|
857 |
apic_timer_update(s, qemu_get_clock(vm_clock)); |
858 |
} |
859 |
break;
|
860 |
case 0x38: |
861 |
s->initial_count = val; |
862 |
s->initial_count_load_time = qemu_get_clock(vm_clock); |
863 |
apic_timer_update(s, s->initial_count_load_time); |
864 |
break;
|
865 |
case 0x39: |
866 |
break;
|
867 |
case 0x3e: |
868 |
{ |
869 |
int v;
|
870 |
s->divide_conf = val & 0xb;
|
871 |
v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
872 |
s->count_shift = (v + 1) & 7; |
873 |
} |
874 |
break;
|
875 |
default:
|
876 |
s->esr |= ESR_ILLEGAL_ADDRESS; |
877 |
break;
|
878 |
} |
879 |
} |
880 |
|
881 |
/* This function is only used for old state version 1 and 2 */
|
882 |
static int apic_load_old(QEMUFile *f, void *opaque, int version_id) |
883 |
{ |
884 |
APICState *s = opaque; |
885 |
int i;
|
886 |
|
887 |
if (version_id > 2) |
888 |
return -EINVAL;
|
889 |
|
890 |
/* XXX: what if the base changes? (registered memory regions) */
|
891 |
qemu_get_be32s(f, &s->apicbase); |
892 |
qemu_get_8s(f, &s->id); |
893 |
qemu_get_8s(f, &s->arb_id); |
894 |
qemu_get_8s(f, &s->tpr); |
895 |
qemu_get_be32s(f, &s->spurious_vec); |
896 |
qemu_get_8s(f, &s->log_dest); |
897 |
qemu_get_8s(f, &s->dest_mode); |
898 |
for (i = 0; i < 8; i++) { |
899 |
qemu_get_be32s(f, &s->isr[i]); |
900 |
qemu_get_be32s(f, &s->tmr[i]); |
901 |
qemu_get_be32s(f, &s->irr[i]); |
902 |
} |
903 |
for (i = 0; i < APIC_LVT_NB; i++) { |
904 |
qemu_get_be32s(f, &s->lvt[i]); |
905 |
} |
906 |
qemu_get_be32s(f, &s->esr); |
907 |
qemu_get_be32s(f, &s->icr[0]);
|
908 |
qemu_get_be32s(f, &s->icr[1]);
|
909 |
qemu_get_be32s(f, &s->divide_conf); |
910 |
s->count_shift=qemu_get_be32(f); |
911 |
qemu_get_be32s(f, &s->initial_count); |
912 |
s->initial_count_load_time=qemu_get_be64(f); |
913 |
s->next_time=qemu_get_be64(f); |
914 |
|
915 |
if (version_id >= 2) |
916 |
qemu_get_timer(f, s->timer); |
917 |
return 0; |
918 |
} |
919 |
|
920 |
static const VMStateDescription vmstate_apic = { |
921 |
.name = "apic",
|
922 |
.version_id = 3,
|
923 |
.minimum_version_id = 3,
|
924 |
.minimum_version_id_old = 1,
|
925 |
.load_state_old = apic_load_old, |
926 |
.fields = (VMStateField []) { |
927 |
VMSTATE_UINT32(apicbase, APICState), |
928 |
VMSTATE_UINT8(id, APICState), |
929 |
VMSTATE_UINT8(arb_id, APICState), |
930 |
VMSTATE_UINT8(tpr, APICState), |
931 |
VMSTATE_UINT32(spurious_vec, APICState), |
932 |
VMSTATE_UINT8(log_dest, APICState), |
933 |
VMSTATE_UINT8(dest_mode, APICState), |
934 |
VMSTATE_UINT32_ARRAY(isr, APICState, 8),
|
935 |
VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
|
936 |
VMSTATE_UINT32_ARRAY(irr, APICState, 8),
|
937 |
VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB), |
938 |
VMSTATE_UINT32(esr, APICState), |
939 |
VMSTATE_UINT32_ARRAY(icr, APICState, 2),
|
940 |
VMSTATE_UINT32(divide_conf, APICState), |
941 |
VMSTATE_INT32(count_shift, APICState), |
942 |
VMSTATE_UINT32(initial_count, APICState), |
943 |
VMSTATE_INT64(initial_count_load_time, APICState), |
944 |
VMSTATE_INT64(next_time, APICState), |
945 |
VMSTATE_TIMER(timer, APICState), |
946 |
VMSTATE_END_OF_LIST() |
947 |
} |
948 |
}; |
949 |
|
950 |
static void apic_reset(void *opaque) |
951 |
{ |
952 |
APICState *s = opaque; |
953 |
int bsp;
|
954 |
|
955 |
bsp = cpu_is_bsp(s->cpu_env); |
956 |
s->apicbase = 0xfee00000 |
|
957 |
(bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
|
958 |
|
959 |
cpu_reset(s->cpu_env); |
960 |
apic_init_reset(s->cpu_env); |
961 |
|
962 |
if (bsp) {
|
963 |
/*
|
964 |
* LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
|
965 |
* time typically by BIOS, so PIC interrupt can be delivered to the
|
966 |
* processor when local APIC is enabled.
|
967 |
*/
|
968 |
s->lvt[APIC_LVT_LINT0] = 0x700;
|
969 |
} |
970 |
} |
971 |
|
972 |
static CPUReadMemoryFunc * const apic_mem_read[3] = { |
973 |
apic_mem_readb, |
974 |
apic_mem_readw, |
975 |
apic_mem_readl, |
976 |
}; |
977 |
|
978 |
static CPUWriteMemoryFunc * const apic_mem_write[3] = { |
979 |
apic_mem_writeb, |
980 |
apic_mem_writew, |
981 |
apic_mem_writel, |
982 |
}; |
983 |
|
984 |
int apic_init(CPUState *env)
|
985 |
{ |
986 |
APICState *s; |
987 |
|
988 |
if (last_apic_idx >= MAX_APICS)
|
989 |
return -1; |
990 |
s = qemu_mallocz(sizeof(APICState));
|
991 |
env->apic_state = s; |
992 |
s->idx = last_apic_idx++; |
993 |
s->id = env->cpuid_apic_id; |
994 |
s->cpu_env = env; |
995 |
|
996 |
msix_supported = 1;
|
997 |
|
998 |
/* XXX: mapping more APICs at the same memory location */
|
999 |
if (apic_io_memory == 0) { |
1000 |
/* NOTE: the APIC is directly connected to the CPU - it is not
|
1001 |
on the global memory bus. */
|
1002 |
apic_io_memory = cpu_register_io_memory(apic_mem_read, |
1003 |
apic_mem_write, NULL);
|
1004 |
/* XXX: what if the base changes? */
|
1005 |
cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE, |
1006 |
apic_io_memory); |
1007 |
} |
1008 |
s->timer = qemu_new_timer(vm_clock, apic_timer, s); |
1009 |
|
1010 |
vmstate_register(s->idx, &vmstate_apic, s); |
1011 |
qemu_register_reset(apic_reset, s); |
1012 |
|
1013 |
local_apics[s->idx] = s; |
1014 |
return 0; |
1015 |
} |