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Revision cf965d24

     static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
+    {
         struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
         int offset = addr - s->timer.base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         switch (offset) {
         case 0x00:	/* TVR */
-...
                     uint32_t value)
+    {
         struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
         int offset = addr - s->timer.base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         switch (offset) {
         case 0x00:	/* TVR */
-...
     static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr)
+    {
         struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
         int offset = addr - s->base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         uint16_t ret;
         switch (offset) {
-...
                     uint32_t value)
+    {
         struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
         int offset = addr - s->base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         uint16_t diff;
         int ln;
-...
     static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr)
+    {
         struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
         int offset = addr - s->base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         switch (offset) {
         case 0x00:	/* DATA_INPUT */
-...
                     uint32_t value)
+    {
         struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
         int offset = addr - s->base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         uint16_t diff;
         int ln;
-...
     static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr)
+    {
         struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
         int offset = addr - s->base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         switch (offset) {
         case 0x00:	/* RDR */
-...
                     uint32_t value)
+    {
         struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
         int offset = addr - s->base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         switch (offset) {
         case 0x00:	/* TDR */
             s->txbuf = value;				/* TD */
             s->control |= 1 << 14;				/* CSRB */
             if ((s->setup[4] & (1 << 2)) &&			/* AUTO_TX_EN */
                             ((s->setup[4] & (1 << 3)) ||	/* CS_TOGGLE_TX_EN */
                              (s->control & (1 << 12))))	/* CS_CMD */
                              (s->control & (1 << 12)))) {	/* CS_CMD */
                 s->control |= 1 << 14;			/* CSRB */
                 omap_uwire_transfer_start(s);
+            }
             break;
         case 0x04:	/* CSR */
-...
     static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr)
+    {
         struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
         int offset = addr - s->pwl.base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         switch (offset) {
         case 0x00:	/* PWL_LEVEL */
-...
                     uint32_t value)
+    {
         struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
         int offset = addr - s->pwl.base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         switch (offset) {
         case 0x00:	/* PWL_LEVEL */
-...
     static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr)
+    {
         struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
         int offset = addr - s->pwt.base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         switch (offset) {
         case 0x00:	/* FRC */
-...
                     uint32_t value)
+    {
         struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
         int offset = addr - s->pwt.base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         switch (offset) {
         case 0x00:	/* FRC */
-...
     static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr)
+    {
         struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
         int offset = addr - s->base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         uint8_t i;
         switch (offset) {
-...
                     uint32_t value)
+    {
         struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
         int offset = addr - s->base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         struct tm new_tm;
         time_t ti[2];
-...
         cpu_reset(mpu->env);
+    }
     static const struct omap_map_s {
         target_phys_addr_t phys_dsp;
         target_phys_addr_t phys_mpu;
         uint32_t size;
         const char *name;
     } omap15xx_dsp_mm[] = {
         /* Strobe 0 */
         { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" },		/* CS0 */
         { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" },		/* CS1 */
         { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" },		/* CS3 */
         { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" },	/* CS4 */
         { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" },	/* CS5 */
         { 0xe1013000, 0xfffb3000, 0x800, "uWire" },			/* CS6 */
         { 0xe1013800, 0xfffb3800, 0x800, "I^2C" },			/* CS7 */
         { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" },		/* CS8 */
         { 0xe1014800, 0xfffb4800, 0x800, "RTC" },			/* CS9 */
         { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" },			/* CS10 */
         { 0xe1015800, 0xfffb5800, 0x800, "PWL" },			/* CS11 */
         { 0xe1016000, 0xfffb6000, 0x800, "PWT" },			/* CS12 */
         { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" },		/* CS14 */
         { 0xe1017800, 0xfffb7800, 0x800, "MMC" },			/* CS15 */
         { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" },		/* CS18 */
         { 0xe1019800, 0xfffb9800, 0x800, "UART3" },			/* CS19 */
         { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" },		/* CS25 */
         /* Strobe 1 */
         { 0xe101e000, 0xfffce000, 0x800, "GPIOs" },			/* CS28 */
         { 0 }
     };
     static void omap_setup_dsp_mapping(const struct omap_map_s *map)
+    {
         int io;
         for (; map->phys_dsp; map ++) {
             io = cpu_get_physical_page_desc(map->phys_mpu);
             cpu_register_physical_memory(map->phys_dsp, map->size, io);
+        }
+    }
     static void omap_mpu_wakeup(void *opaque, int irq, int req)
+    {
         struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
-...
          * DSP MMU		fffed200 - fffed2ff
          */
         omap_setup_dsp_mapping(omap15xx_dsp_mm);
         qemu_register_reset(omap_mpu_reset, s);
         return s;

         struct omap_uwire_s *microwire;
         struct {
             target_phys_addr_t base;
             uint8_t output;
             uint8_t level;
             uint8_t enable;
-...
         } pwl;
         struct {
             target_phys_addr_t base;
             uint8_t frc;
             uint8_t vrc;
             uint8_t gcr;
-...
     #  define OMAP_32B_REG(paddr)
     # endif
     # define OMAP_MPUI_REG_MASK		0x000007ff
     #endif /* hw_omap_h */

     static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
+    {
         struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
         int offset = addr - s->base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         uint16_t ret;
         switch (offset) {
-...
                     uint32_t value)
+    {
         struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
         int offset = addr - s->base;
         int offset = addr & OMAP_MPUI_REG_MASK;
         int nack;
         switch (offset) {

+    {
         uint16_t i;
         struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
         offset -= s->base;
         offset &= OMAP_MPUI_REG_MASK;
         switch (offset) {
         case 0x00:	/* MMC_CMD */
-...
+    {
         int i;
         struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
         offset -= s->base;
         offset &= OMAP_MPUI_REG_MASK;
         switch (offset) {
         case 0x00:	/* MMC_CMD */

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Revision cf965d24