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1 | a541f297 | bellard | /*
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2 | e9df014c | j_mayer | * QEMU generic PowerPC hardware System Emulator
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3 | a541f297 | bellard | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | a541f297 | bellard | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | a541f297 | bellard | #include "vl.h" |
25 | fd0bbb12 | bellard | #include "m48t59.h" |
26 | a541f297 | bellard | |
27 | e9df014c | j_mayer | //#define PPC_DEBUG_IRQ
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28 | e9df014c | j_mayer | |
29 | 47103572 | j_mayer | extern FILE *logfile;
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30 | 47103572 | j_mayer | extern int loglevel; |
31 | 47103572 | j_mayer | |
32 | e9df014c | j_mayer | void ppc_set_irq (CPUState *env, int n_IRQ, int level) |
33 | 47103572 | j_mayer | { |
34 | 47103572 | j_mayer | if (level) {
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35 | 47103572 | j_mayer | env->pending_interrupts |= 1 << n_IRQ;
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36 | 47103572 | j_mayer | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
37 | 47103572 | j_mayer | } else {
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38 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << n_IRQ);
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39 | 47103572 | j_mayer | if (env->pending_interrupts == 0) |
40 | 47103572 | j_mayer | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
41 | 47103572 | j_mayer | } |
42 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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43 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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44 | a496775f | j_mayer | fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
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45 | a496775f | j_mayer | __func__, env, n_IRQ, level, |
46 | a496775f | j_mayer | env->pending_interrupts, env->interrupt_request); |
47 | a496775f | j_mayer | } |
48 | 47103572 | j_mayer | #endif
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49 | 47103572 | j_mayer | } |
50 | 47103572 | j_mayer | |
51 | e9df014c | j_mayer | /* PowerPC 6xx / 7xx internal IRQ controller */
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52 | e9df014c | j_mayer | static void ppc6xx_set_irq (void *opaque, int pin, int level) |
53 | d537cf6c | pbrook | { |
54 | e9df014c | j_mayer | CPUState *env = opaque; |
55 | e9df014c | j_mayer | int cur_level;
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56 | d537cf6c | pbrook | |
57 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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58 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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59 | a496775f | j_mayer | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
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60 | a496775f | j_mayer | env, pin, level); |
61 | a496775f | j_mayer | } |
62 | e9df014c | j_mayer | #endif
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63 | e9df014c | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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64 | e9df014c | j_mayer | /* Don't generate spurious events */
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65 | 24be5ae3 | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
66 | e9df014c | j_mayer | switch (pin) {
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67 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_INT:
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68 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
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69 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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70 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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71 | a496775f | j_mayer | fprintf(logfile, "%s: set the external IRQ state to %d\n",
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72 | a496775f | j_mayer | __func__, level); |
73 | a496775f | j_mayer | } |
74 | e9df014c | j_mayer | #endif
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75 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
76 | e9df014c | j_mayer | break;
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77 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_SMI:
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78 | e9df014c | j_mayer | /* Level sensitive - active high */
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79 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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80 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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81 | a496775f | j_mayer | fprintf(logfile, "%s: set the SMI IRQ state to %d\n",
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82 | a496775f | j_mayer | __func__, level); |
83 | a496775f | j_mayer | } |
84 | e9df014c | j_mayer | #endif
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85 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_SMI, level); |
86 | e9df014c | j_mayer | break;
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87 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_MCP:
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88 | e9df014c | j_mayer | /* Negative edge sensitive */
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89 | e9df014c | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
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90 | e9df014c | j_mayer | * 603/604/740/750: check HID0[EMCP]
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91 | e9df014c | j_mayer | */
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92 | e9df014c | j_mayer | if (cur_level == 1 && level == 0) { |
93 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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94 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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95 | a496775f | j_mayer | fprintf(logfile, "%s: raise machine check state\n",
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96 | a496775f | j_mayer | __func__); |
97 | a496775f | j_mayer | } |
98 | e9df014c | j_mayer | #endif
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99 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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100 | e9df014c | j_mayer | } |
101 | e9df014c | j_mayer | break;
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102 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_CKSTP_IN:
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103 | e9df014c | j_mayer | /* Level sensitive - active low */
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104 | e9df014c | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
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105 | e9df014c | j_mayer | if (level) {
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106 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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107 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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108 | a496775f | j_mayer | fprintf(logfile, "%s: stop the CPU\n", __func__);
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109 | a496775f | j_mayer | } |
110 | e9df014c | j_mayer | #endif
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111 | e9df014c | j_mayer | env->halted = 1;
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112 | e9df014c | j_mayer | } else {
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113 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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114 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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115 | a496775f | j_mayer | fprintf(logfile, "%s: restart the CPU\n", __func__);
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116 | a496775f | j_mayer | } |
117 | e9df014c | j_mayer | #endif
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118 | e9df014c | j_mayer | env->halted = 0;
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119 | e9df014c | j_mayer | } |
120 | e9df014c | j_mayer | break;
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121 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_HRESET:
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122 | e9df014c | j_mayer | /* Level sensitive - active low */
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123 | e9df014c | j_mayer | if (level) {
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124 | e9df014c | j_mayer | #if 0 // XXX: TOFIX
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125 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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126 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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127 | a496775f | j_mayer | fprintf(logfile, "%s: reset the CPU\n", __func__);
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128 | a496775f | j_mayer | }
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129 | e9df014c | j_mayer | #endif
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130 | e9df014c | j_mayer | cpu_reset(env); |
131 | e9df014c | j_mayer | #endif
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132 | e9df014c | j_mayer | } |
133 | e9df014c | j_mayer | break;
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134 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_SRESET:
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135 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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136 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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137 | a496775f | j_mayer | fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
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138 | a496775f | j_mayer | __func__, level); |
139 | a496775f | j_mayer | } |
140 | e9df014c | j_mayer | #endif
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141 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
142 | e9df014c | j_mayer | break;
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143 | e9df014c | j_mayer | default:
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144 | e9df014c | j_mayer | /* Unknown pin - do nothing */
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145 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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146 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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147 | a496775f | j_mayer | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
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148 | a496775f | j_mayer | } |
149 | e9df014c | j_mayer | #endif
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150 | e9df014c | j_mayer | return;
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151 | e9df014c | j_mayer | } |
152 | e9df014c | j_mayer | if (level)
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153 | e9df014c | j_mayer | env->irq_input_state |= 1 << pin;
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154 | e9df014c | j_mayer | else
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155 | e9df014c | j_mayer | env->irq_input_state &= ~(1 << pin);
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156 | d537cf6c | pbrook | } |
157 | d537cf6c | pbrook | } |
158 | d537cf6c | pbrook | |
159 | e9df014c | j_mayer | void ppc6xx_irq_init (CPUState *env)
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160 | 47103572 | j_mayer | { |
161 | e9df014c | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6); |
162 | 47103572 | j_mayer | } |
163 | 47103572 | j_mayer | |
164 | d0dfae6e | j_mayer | /* PowerPC 970 internal IRQ controller */
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165 | d0dfae6e | j_mayer | static void ppc970_set_irq (void *opaque, int pin, int level) |
166 | d0dfae6e | j_mayer | { |
167 | d0dfae6e | j_mayer | CPUState *env = opaque; |
168 | d0dfae6e | j_mayer | int cur_level;
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169 | d0dfae6e | j_mayer | |
170 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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171 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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172 | d0dfae6e | j_mayer | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
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173 | d0dfae6e | j_mayer | env, pin, level); |
174 | d0dfae6e | j_mayer | } |
175 | d0dfae6e | j_mayer | #endif
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176 | d0dfae6e | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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177 | d0dfae6e | j_mayer | /* Don't generate spurious events */
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178 | d0dfae6e | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
179 | d0dfae6e | j_mayer | switch (pin) {
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180 | d0dfae6e | j_mayer | case PPC970_INPUT_INT:
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181 | d0dfae6e | j_mayer | /* Level sensitive - active high */
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182 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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183 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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184 | d0dfae6e | j_mayer | fprintf(logfile, "%s: set the external IRQ state to %d\n",
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185 | d0dfae6e | j_mayer | __func__, level); |
186 | d0dfae6e | j_mayer | } |
187 | d0dfae6e | j_mayer | #endif
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188 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
189 | d0dfae6e | j_mayer | break;
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190 | d0dfae6e | j_mayer | case PPC970_INPUT_THINT:
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191 | d0dfae6e | j_mayer | /* Level sensitive - active high */
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192 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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193 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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194 | d0dfae6e | j_mayer | fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
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195 | d0dfae6e | j_mayer | level); |
196 | d0dfae6e | j_mayer | } |
197 | d0dfae6e | j_mayer | #endif
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198 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_THERM, level); |
199 | d0dfae6e | j_mayer | break;
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200 | d0dfae6e | j_mayer | case PPC970_INPUT_MCP:
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201 | d0dfae6e | j_mayer | /* Negative edge sensitive */
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202 | d0dfae6e | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
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203 | d0dfae6e | j_mayer | * 603/604/740/750: check HID0[EMCP]
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204 | d0dfae6e | j_mayer | */
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205 | d0dfae6e | j_mayer | if (cur_level == 1 && level == 0) { |
206 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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207 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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208 | d0dfae6e | j_mayer | fprintf(logfile, "%s: raise machine check state\n",
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209 | d0dfae6e | j_mayer | __func__); |
210 | d0dfae6e | j_mayer | } |
211 | d0dfae6e | j_mayer | #endif
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212 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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213 | d0dfae6e | j_mayer | } |
214 | d0dfae6e | j_mayer | break;
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215 | d0dfae6e | j_mayer | case PPC970_INPUT_CKSTP:
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216 | d0dfae6e | j_mayer | /* Level sensitive - active low */
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217 | d0dfae6e | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
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218 | d0dfae6e | j_mayer | if (level) {
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219 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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220 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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221 | d0dfae6e | j_mayer | fprintf(logfile, "%s: stop the CPU\n", __func__);
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222 | d0dfae6e | j_mayer | } |
223 | d0dfae6e | j_mayer | #endif
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224 | d0dfae6e | j_mayer | env->halted = 1;
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225 | d0dfae6e | j_mayer | } else {
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226 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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227 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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228 | d0dfae6e | j_mayer | fprintf(logfile, "%s: restart the CPU\n", __func__);
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229 | d0dfae6e | j_mayer | } |
230 | d0dfae6e | j_mayer | #endif
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231 | d0dfae6e | j_mayer | env->halted = 0;
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232 | d0dfae6e | j_mayer | } |
233 | d0dfae6e | j_mayer | break;
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234 | d0dfae6e | j_mayer | case PPC970_INPUT_HRESET:
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235 | d0dfae6e | j_mayer | /* Level sensitive - active low */
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236 | d0dfae6e | j_mayer | if (level) {
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237 | d0dfae6e | j_mayer | #if 0 // XXX: TOFIX
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238 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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239 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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240 | d0dfae6e | j_mayer | fprintf(logfile, "%s: reset the CPU\n", __func__);
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241 | d0dfae6e | j_mayer | }
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242 | d0dfae6e | j_mayer | #endif
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243 | d0dfae6e | j_mayer | cpu_reset(env); |
244 | d0dfae6e | j_mayer | #endif
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245 | d0dfae6e | j_mayer | } |
246 | d0dfae6e | j_mayer | break;
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247 | d0dfae6e | j_mayer | case PPC970_INPUT_SRESET:
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248 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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249 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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250 | d0dfae6e | j_mayer | fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
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251 | d0dfae6e | j_mayer | __func__, level); |
252 | d0dfae6e | j_mayer | } |
253 | d0dfae6e | j_mayer | #endif
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254 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
255 | d0dfae6e | j_mayer | break;
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256 | d0dfae6e | j_mayer | case PPC970_INPUT_TBEN:
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257 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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258 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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259 | d0dfae6e | j_mayer | fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
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260 | d0dfae6e | j_mayer | level); |
261 | d0dfae6e | j_mayer | } |
262 | d0dfae6e | j_mayer | #endif
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263 | d0dfae6e | j_mayer | /* XXX: TODO */
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264 | d0dfae6e | j_mayer | break;
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265 | d0dfae6e | j_mayer | default:
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266 | d0dfae6e | j_mayer | /* Unknown pin - do nothing */
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267 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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268 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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269 | d0dfae6e | j_mayer | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
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270 | d0dfae6e | j_mayer | } |
271 | d0dfae6e | j_mayer | #endif
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272 | d0dfae6e | j_mayer | return;
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273 | d0dfae6e | j_mayer | } |
274 | d0dfae6e | j_mayer | if (level)
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275 | d0dfae6e | j_mayer | env->irq_input_state |= 1 << pin;
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276 | d0dfae6e | j_mayer | else
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277 | d0dfae6e | j_mayer | env->irq_input_state &= ~(1 << pin);
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278 | d0dfae6e | j_mayer | } |
279 | d0dfae6e | j_mayer | } |
280 | d0dfae6e | j_mayer | |
281 | d0dfae6e | j_mayer | void ppc970_irq_init (CPUState *env)
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282 | d0dfae6e | j_mayer | { |
283 | d0dfae6e | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7); |
284 | d0dfae6e | j_mayer | } |
285 | d0dfae6e | j_mayer | |
286 | 24be5ae3 | j_mayer | /* PowerPC 405 internal IRQ controller */
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287 | 24be5ae3 | j_mayer | static void ppc405_set_irq (void *opaque, int pin, int level) |
288 | 24be5ae3 | j_mayer | { |
289 | 24be5ae3 | j_mayer | CPUState *env = opaque; |
290 | 24be5ae3 | j_mayer | int cur_level;
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291 | 24be5ae3 | j_mayer | |
292 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
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293 | 24be5ae3 | j_mayer | printf("%s: env %p pin %d level %d\n", __func__, env, pin, level);
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294 | 24be5ae3 | j_mayer | #endif
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295 | 24be5ae3 | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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296 | 24be5ae3 | j_mayer | /* Don't generate spurious events */
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297 | 24be5ae3 | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
298 | 24be5ae3 | j_mayer | switch (pin) {
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299 | 24be5ae3 | j_mayer | case PPC405_INPUT_RESET_SYS:
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300 | 24be5ae3 | j_mayer | /* XXX: TODO: reset all peripherals */
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301 | 24be5ae3 | j_mayer | /* No break here */
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302 | 24be5ae3 | j_mayer | case PPC405_INPUT_RESET_CHIP:
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303 | 24be5ae3 | j_mayer | /* XXX: TODO: reset on-chip peripherals */
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304 | 24be5ae3 | j_mayer | /* No break here */
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305 | 24be5ae3 | j_mayer | case PPC405_INPUT_RESET_CORE:
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306 | 24be5ae3 | j_mayer | /* XXX: TODO: update DBSR[MRR] */
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307 | 24be5ae3 | j_mayer | if (level) {
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308 | 24be5ae3 | j_mayer | #if 0 // XXX: TOFIX
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309 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
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310 | 24be5ae3 | j_mayer | printf("%s: reset the CPU\n", __func__);
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311 | 24be5ae3 | j_mayer | #endif
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312 | 24be5ae3 | j_mayer | cpu_reset(env); |
313 | 24be5ae3 | j_mayer | #endif
|
314 | 24be5ae3 | j_mayer | } |
315 | 24be5ae3 | j_mayer | break;
|
316 | 24be5ae3 | j_mayer | case PPC405_INPUT_CINT:
|
317 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
318 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
319 | 24be5ae3 | j_mayer | printf("%s: set the critical IRQ state to %d\n", __func__, level);
|
320 | 24be5ae3 | j_mayer | #endif
|
321 | 24be5ae3 | j_mayer | /* XXX: TOFIX */
|
322 | 24be5ae3 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
323 | 24be5ae3 | j_mayer | break;
|
324 | 24be5ae3 | j_mayer | case PPC405_INPUT_INT:
|
325 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
326 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
327 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
328 | a496775f | j_mayer | fprintf(logfile, "%s: set the external IRQ state to %d\n",
|
329 | a496775f | j_mayer | __func__, level); |
330 | a496775f | j_mayer | } |
331 | 24be5ae3 | j_mayer | #endif
|
332 | 24be5ae3 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
333 | 24be5ae3 | j_mayer | break;
|
334 | 24be5ae3 | j_mayer | case PPC405_INPUT_HALT:
|
335 | 24be5ae3 | j_mayer | /* Level sensitive - active low */
|
336 | 24be5ae3 | j_mayer | if (level) {
|
337 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
338 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
339 | a496775f | j_mayer | fprintf(logfile, "%s: stop the CPU\n", __func__);
|
340 | a496775f | j_mayer | } |
341 | 24be5ae3 | j_mayer | #endif
|
342 | 24be5ae3 | j_mayer | env->halted = 1;
|
343 | 24be5ae3 | j_mayer | } else {
|
344 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
345 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
346 | a496775f | j_mayer | fprintf(logfile, "%s: restart the CPU\n", __func__);
|
347 | a496775f | j_mayer | } |
348 | 24be5ae3 | j_mayer | #endif
|
349 | 24be5ae3 | j_mayer | env->halted = 0;
|
350 | 24be5ae3 | j_mayer | } |
351 | 24be5ae3 | j_mayer | break;
|
352 | 24be5ae3 | j_mayer | case PPC405_INPUT_DEBUG:
|
353 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
354 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
355 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
356 | a496775f | j_mayer | fprintf(logfile, "%s: set the external IRQ state to %d\n",
|
357 | a496775f | j_mayer | __func__, level); |
358 | a496775f | j_mayer | } |
359 | 24be5ae3 | j_mayer | #endif
|
360 | 24be5ae3 | j_mayer | ppc_set_irq(env, EXCP_40x_DEBUG, level); |
361 | 24be5ae3 | j_mayer | break;
|
362 | 24be5ae3 | j_mayer | default:
|
363 | 24be5ae3 | j_mayer | /* Unknown pin - do nothing */
|
364 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
365 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
366 | a496775f | j_mayer | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
|
367 | a496775f | j_mayer | } |
368 | 24be5ae3 | j_mayer | #endif
|
369 | 24be5ae3 | j_mayer | return;
|
370 | 24be5ae3 | j_mayer | } |
371 | 24be5ae3 | j_mayer | if (level)
|
372 | 24be5ae3 | j_mayer | env->irq_input_state |= 1 << pin;
|
373 | 24be5ae3 | j_mayer | else
|
374 | 24be5ae3 | j_mayer | env->irq_input_state &= ~(1 << pin);
|
375 | 24be5ae3 | j_mayer | } |
376 | 24be5ae3 | j_mayer | } |
377 | 24be5ae3 | j_mayer | |
378 | 24be5ae3 | j_mayer | void ppc405_irq_init (CPUState *env)
|
379 | 24be5ae3 | j_mayer | { |
380 | 24be5ae3 | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc405_set_irq, env, 7); |
381 | 24be5ae3 | j_mayer | } |
382 | 24be5ae3 | j_mayer | |
383 | 9fddaa0c | bellard | /*****************************************************************************/
|
384 | e9df014c | j_mayer | /* PowerPC time base and decrementer emulation */
|
385 | 9fddaa0c | bellard | //#define DEBUG_TB
|
386 | 9fddaa0c | bellard | |
387 | 9fddaa0c | bellard | struct ppc_tb_t {
|
388 | 9fddaa0c | bellard | /* Time base management */
|
389 | 9fddaa0c | bellard | int64_t tb_offset; /* Compensation */
|
390 | 9fddaa0c | bellard | uint32_t tb_freq; /* TB frequency */
|
391 | 9fddaa0c | bellard | /* Decrementer management */
|
392 | 9fddaa0c | bellard | uint64_t decr_next; /* Tick for next decr interrupt */
|
393 | 9fddaa0c | bellard | struct QEMUTimer *decr_timer;
|
394 | 47103572 | j_mayer | void *opaque;
|
395 | 9fddaa0c | bellard | }; |
396 | 9fddaa0c | bellard | |
397 | 9fddaa0c | bellard | static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env) |
398 | 9fddaa0c | bellard | { |
399 | 9fddaa0c | bellard | /* TB time in tb periods */
|
400 | 9fddaa0c | bellard | return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
|
401 | 76a66253 | j_mayer | tb_env->tb_freq, ticks_per_sec); |
402 | 9fddaa0c | bellard | } |
403 | 9fddaa0c | bellard | |
404 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbl (CPUState *env) |
405 | 9fddaa0c | bellard | { |
406 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
407 | 9fddaa0c | bellard | uint64_t tb; |
408 | 9fddaa0c | bellard | |
409 | 9fddaa0c | bellard | tb = cpu_ppc_get_tb(tb_env); |
410 | 9fddaa0c | bellard | #ifdef DEBUG_TB
|
411 | 9fddaa0c | bellard | { |
412 | 76a66253 | j_mayer | static int last_time; |
413 | 76a66253 | j_mayer | int now;
|
414 | 76a66253 | j_mayer | now = time(NULL);
|
415 | 76a66253 | j_mayer | if (last_time != now) {
|
416 | 76a66253 | j_mayer | last_time = now; |
417 | a496775f | j_mayer | if (loglevel) {
|
418 | a496775f | j_mayer | fprintf(logfile, "%s: tb=0x%016lx %d %08lx\n",
|
419 | a496775f | j_mayer | __func__, tb, now, tb_env->tb_offset); |
420 | a496775f | j_mayer | } |
421 | 76a66253 | j_mayer | } |
422 | 9fddaa0c | bellard | } |
423 | 9fddaa0c | bellard | #endif
|
424 | 9fddaa0c | bellard | |
425 | 9fddaa0c | bellard | return tb & 0xFFFFFFFF; |
426 | 9fddaa0c | bellard | } |
427 | 9fddaa0c | bellard | |
428 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbu (CPUState *env) |
429 | 9fddaa0c | bellard | { |
430 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
431 | 9fddaa0c | bellard | uint64_t tb; |
432 | 9fddaa0c | bellard | |
433 | 9fddaa0c | bellard | tb = cpu_ppc_get_tb(tb_env); |
434 | 9fddaa0c | bellard | #ifdef DEBUG_TB
|
435 | a496775f | j_mayer | if (loglevel) {
|
436 | a496775f | j_mayer | fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
|
437 | a496775f | j_mayer | } |
438 | 9fddaa0c | bellard | #endif
|
439 | 76a66253 | j_mayer | |
440 | 9fddaa0c | bellard | return tb >> 32; |
441 | 9fddaa0c | bellard | } |
442 | 9fddaa0c | bellard | |
443 | 9fddaa0c | bellard | static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value) |
444 | 9fddaa0c | bellard | { |
445 | 9fddaa0c | bellard | tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq) |
446 | 9fddaa0c | bellard | - qemu_get_clock(vm_clock); |
447 | 9fddaa0c | bellard | #ifdef DEBUG_TB
|
448 | a496775f | j_mayer | if (loglevel) {
|
449 | a496775f | j_mayer | fprintf(logfile, "%s: tb=0x%016lx offset=%08x\n", __func__, value);
|
450 | a496775f | j_mayer | } |
451 | 9fddaa0c | bellard | #endif
|
452 | 9fddaa0c | bellard | } |
453 | 9fddaa0c | bellard | |
454 | 9fddaa0c | bellard | void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
|
455 | 9fddaa0c | bellard | { |
456 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
457 | 9fddaa0c | bellard | |
458 | 9fddaa0c | bellard | cpu_ppc_store_tb(tb_env, |
459 | 9fddaa0c | bellard | ((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
|
460 | 9fddaa0c | bellard | } |
461 | 9fddaa0c | bellard | |
462 | 9fddaa0c | bellard | void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
|
463 | 9fddaa0c | bellard | { |
464 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
465 | 9fddaa0c | bellard | |
466 | 9fddaa0c | bellard | cpu_ppc_store_tb(tb_env, |
467 | 9fddaa0c | bellard | ((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
|
468 | 9fddaa0c | bellard | } |
469 | 9fddaa0c | bellard | |
470 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_decr (CPUState *env) |
471 | 9fddaa0c | bellard | { |
472 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
473 | 9fddaa0c | bellard | uint32_t decr; |
474 | 4e588a4d | bellard | int64_t diff; |
475 | 9fddaa0c | bellard | |
476 | 4e588a4d | bellard | diff = tb_env->decr_next - qemu_get_clock(vm_clock); |
477 | 4e588a4d | bellard | if (diff >= 0) |
478 | 4e588a4d | bellard | decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec); |
479 | 4e588a4d | bellard | else
|
480 | 4e588a4d | bellard | decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec); |
481 | fd0bbb12 | bellard | #if defined(DEBUG_TB)
|
482 | a496775f | j_mayer | if (loglevel) {
|
483 | a496775f | j_mayer | fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
|
484 | a496775f | j_mayer | } |
485 | 9fddaa0c | bellard | #endif
|
486 | 76a66253 | j_mayer | |
487 | 9fddaa0c | bellard | return decr;
|
488 | 9fddaa0c | bellard | } |
489 | 9fddaa0c | bellard | |
490 | 9fddaa0c | bellard | /* When decrementer expires,
|
491 | 9fddaa0c | bellard | * all we need to do is generate or queue a CPU exception
|
492 | 9fddaa0c | bellard | */
|
493 | 9fddaa0c | bellard | static inline void cpu_ppc_decr_excp (CPUState *env) |
494 | 9fddaa0c | bellard | { |
495 | 9fddaa0c | bellard | /* Raise it */
|
496 | 9fddaa0c | bellard | #ifdef DEBUG_TB
|
497 | a496775f | j_mayer | if (loglevel) {
|
498 | a496775f | j_mayer | fprintf(logfile, "raise decrementer exception\n");
|
499 | a496775f | j_mayer | } |
500 | 9fddaa0c | bellard | #endif
|
501 | 47103572 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
|
502 | 9fddaa0c | bellard | } |
503 | 9fddaa0c | bellard | |
504 | 9fddaa0c | bellard | static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, |
505 | 9fddaa0c | bellard | uint32_t value, int is_excp)
|
506 | 9fddaa0c | bellard | { |
507 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
508 | 9fddaa0c | bellard | uint64_t now, next; |
509 | 9fddaa0c | bellard | |
510 | 9fddaa0c | bellard | #ifdef DEBUG_TB
|
511 | a496775f | j_mayer | if (loglevel) {
|
512 | a496775f | j_mayer | fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
|
513 | a496775f | j_mayer | } |
514 | 9fddaa0c | bellard | #endif
|
515 | 9fddaa0c | bellard | now = qemu_get_clock(vm_clock); |
516 | 9fddaa0c | bellard | next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq); |
517 | 9fddaa0c | bellard | if (is_excp)
|
518 | 9fddaa0c | bellard | next += tb_env->decr_next - now; |
519 | 9fddaa0c | bellard | if (next == now)
|
520 | 76a66253 | j_mayer | next++; |
521 | 9fddaa0c | bellard | tb_env->decr_next = next; |
522 | 9fddaa0c | bellard | /* Adjust timer */
|
523 | 9fddaa0c | bellard | qemu_mod_timer(tb_env->decr_timer, next); |
524 | 9fddaa0c | bellard | /* If we set a negative value and the decrementer was positive,
|
525 | 9fddaa0c | bellard | * raise an exception.
|
526 | 9fddaa0c | bellard | */
|
527 | 9fddaa0c | bellard | if ((value & 0x80000000) && !(decr & 0x80000000)) |
528 | 76a66253 | j_mayer | cpu_ppc_decr_excp(env); |
529 | 9fddaa0c | bellard | } |
530 | 9fddaa0c | bellard | |
531 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUState *env, uint32_t value)
|
532 | 9fddaa0c | bellard | { |
533 | 9fddaa0c | bellard | _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
|
534 | 9fddaa0c | bellard | } |
535 | 9fddaa0c | bellard | |
536 | 9fddaa0c | bellard | static void cpu_ppc_decr_cb (void *opaque) |
537 | 9fddaa0c | bellard | { |
538 | 9fddaa0c | bellard | _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
539 | 9fddaa0c | bellard | } |
540 | 9fddaa0c | bellard | |
541 | 9fddaa0c | bellard | /* Set up (once) timebase frequency (in Hz) */
|
542 | 9fddaa0c | bellard | ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
543 | 9fddaa0c | bellard | { |
544 | 9fddaa0c | bellard | ppc_tb_t *tb_env; |
545 | 9fddaa0c | bellard | |
546 | 9fddaa0c | bellard | tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
547 | 9fddaa0c | bellard | if (tb_env == NULL) |
548 | 9fddaa0c | bellard | return NULL; |
549 | 9fddaa0c | bellard | env->tb_env = tb_env; |
550 | 9fddaa0c | bellard | if (tb_env->tb_freq == 0 || 1) { |
551 | 76a66253 | j_mayer | tb_env->tb_freq = freq; |
552 | 76a66253 | j_mayer | /* Create new timer */
|
553 | 76a66253 | j_mayer | tb_env->decr_timer = |
554 | 9fddaa0c | bellard | qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); |
555 | 76a66253 | j_mayer | /* There is a bug in Linux 2.4 kernels:
|
556 | 76a66253 | j_mayer | * if a decrementer exception is pending when it enables msr_ee,
|
557 | 76a66253 | j_mayer | * it's not ready to handle it...
|
558 | 76a66253 | j_mayer | */
|
559 | 76a66253 | j_mayer | _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
560 | 9fddaa0c | bellard | } |
561 | 9fddaa0c | bellard | |
562 | 9fddaa0c | bellard | return tb_env;
|
563 | 9fddaa0c | bellard | } |
564 | 9fddaa0c | bellard | |
565 | 76a66253 | j_mayer | /* Specific helpers for POWER & PowerPC 601 RTC */
|
566 | 76a66253 | j_mayer | ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env) |
567 | 76a66253 | j_mayer | { |
568 | 76a66253 | j_mayer | return cpu_ppc_tb_init(env, 7812500); |
569 | 76a66253 | j_mayer | } |
570 | 76a66253 | j_mayer | |
571 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
|
572 | 76a66253 | j_mayer | __attribute__ (( alias ("cpu_ppc_store_tbu") ));
|
573 | 76a66253 | j_mayer | |
574 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcu (CPUState *env) |
575 | 76a66253 | j_mayer | __attribute__ (( alias ("cpu_ppc_load_tbu") ));
|
576 | 76a66253 | j_mayer | |
577 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
|
578 | 76a66253 | j_mayer | { |
579 | 76a66253 | j_mayer | cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
|
580 | 76a66253 | j_mayer | } |
581 | 76a66253 | j_mayer | |
582 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcl (CPUState *env) |
583 | 76a66253 | j_mayer | { |
584 | 76a66253 | j_mayer | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
585 | 76a66253 | j_mayer | } |
586 | 76a66253 | j_mayer | |
587 | 636aaad7 | j_mayer | /*****************************************************************************/
|
588 | 76a66253 | j_mayer | /* Embedded PowerPC timers */
|
589 | 636aaad7 | j_mayer | |
590 | 636aaad7 | j_mayer | /* PIT, FIT & WDT */
|
591 | 636aaad7 | j_mayer | typedef struct ppcemb_timer_t ppcemb_timer_t; |
592 | 636aaad7 | j_mayer | struct ppcemb_timer_t {
|
593 | 636aaad7 | j_mayer | uint64_t pit_reload; /* PIT auto-reload value */
|
594 | 636aaad7 | j_mayer | uint64_t fit_next; /* Tick for next FIT interrupt */
|
595 | 636aaad7 | j_mayer | struct QEMUTimer *fit_timer;
|
596 | 636aaad7 | j_mayer | uint64_t wdt_next; /* Tick for next WDT interrupt */
|
597 | 636aaad7 | j_mayer | struct QEMUTimer *wdt_timer;
|
598 | 636aaad7 | j_mayer | }; |
599 | 636aaad7 | j_mayer | |
600 | 636aaad7 | j_mayer | /* Fixed interval timer */
|
601 | 636aaad7 | j_mayer | static void cpu_4xx_fit_cb (void *opaque) |
602 | 636aaad7 | j_mayer | { |
603 | 636aaad7 | j_mayer | CPUState *env; |
604 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
605 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
606 | 636aaad7 | j_mayer | uint64_t now, next; |
607 | 636aaad7 | j_mayer | |
608 | 636aaad7 | j_mayer | env = opaque; |
609 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
610 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
611 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
612 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
613 | 636aaad7 | j_mayer | case 0: |
614 | 636aaad7 | j_mayer | next = 1 << 9; |
615 | 636aaad7 | j_mayer | break;
|
616 | 636aaad7 | j_mayer | case 1: |
617 | 636aaad7 | j_mayer | next = 1 << 13; |
618 | 636aaad7 | j_mayer | break;
|
619 | 636aaad7 | j_mayer | case 2: |
620 | 636aaad7 | j_mayer | next = 1 << 17; |
621 | 636aaad7 | j_mayer | break;
|
622 | 636aaad7 | j_mayer | case 3: |
623 | 636aaad7 | j_mayer | next = 1 << 21; |
624 | 636aaad7 | j_mayer | break;
|
625 | 636aaad7 | j_mayer | default:
|
626 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
627 | 636aaad7 | j_mayer | return;
|
628 | 636aaad7 | j_mayer | } |
629 | 636aaad7 | j_mayer | next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); |
630 | 636aaad7 | j_mayer | if (next == now)
|
631 | 636aaad7 | j_mayer | next++; |
632 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->fit_timer, next); |
633 | 636aaad7 | j_mayer | tb_env->decr_next = next; |
634 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 26; |
635 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) |
636 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
|
637 | 636aaad7 | j_mayer | if (loglevel) {
|
638 | e96efcfc | j_mayer | fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__, |
639 | e96efcfc | j_mayer | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), |
640 | 636aaad7 | j_mayer | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
641 | 636aaad7 | j_mayer | } |
642 | 636aaad7 | j_mayer | } |
643 | 636aaad7 | j_mayer | |
644 | 636aaad7 | j_mayer | /* Programmable interval timer */
|
645 | 636aaad7 | j_mayer | static void cpu_4xx_pit_cb (void *opaque) |
646 | 76a66253 | j_mayer | { |
647 | 636aaad7 | j_mayer | CPUState *env; |
648 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
649 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
650 | 636aaad7 | j_mayer | uint64_t now, next; |
651 | 636aaad7 | j_mayer | |
652 | 636aaad7 | j_mayer | env = opaque; |
653 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
654 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
655 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
656 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 22) & 0x1) { |
657 | 636aaad7 | j_mayer | /* Auto reload */
|
658 | 636aaad7 | j_mayer | next = now + muldiv64(ppcemb_timer->pit_reload, |
659 | 636aaad7 | j_mayer | ticks_per_sec, tb_env->tb_freq); |
660 | 636aaad7 | j_mayer | if (next == now)
|
661 | 636aaad7 | j_mayer | next++; |
662 | 636aaad7 | j_mayer | qemu_mod_timer(tb_env->decr_timer, next); |
663 | 636aaad7 | j_mayer | tb_env->decr_next = next; |
664 | 636aaad7 | j_mayer | } |
665 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 27; |
666 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) |
667 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
|
668 | 636aaad7 | j_mayer | if (loglevel) {
|
669 | e96efcfc | j_mayer | fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " " |
670 | e96efcfc | j_mayer | "%016" PRIx64 "\n", __func__, |
671 | e96efcfc | j_mayer | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), |
672 | e96efcfc | j_mayer | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), |
673 | 636aaad7 | j_mayer | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
674 | 636aaad7 | j_mayer | ppcemb_timer->pit_reload); |
675 | 636aaad7 | j_mayer | } |
676 | 636aaad7 | j_mayer | } |
677 | 636aaad7 | j_mayer | |
678 | 636aaad7 | j_mayer | /* Watchdog timer */
|
679 | 636aaad7 | j_mayer | static void cpu_4xx_wdt_cb (void *opaque) |
680 | 636aaad7 | j_mayer | { |
681 | 636aaad7 | j_mayer | CPUState *env; |
682 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
683 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
684 | 636aaad7 | j_mayer | uint64_t now, next; |
685 | 636aaad7 | j_mayer | |
686 | 636aaad7 | j_mayer | env = opaque; |
687 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
688 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
689 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
690 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
691 | 636aaad7 | j_mayer | case 0: |
692 | 636aaad7 | j_mayer | next = 1 << 17; |
693 | 636aaad7 | j_mayer | break;
|
694 | 636aaad7 | j_mayer | case 1: |
695 | 636aaad7 | j_mayer | next = 1 << 21; |
696 | 636aaad7 | j_mayer | break;
|
697 | 636aaad7 | j_mayer | case 2: |
698 | 636aaad7 | j_mayer | next = 1 << 25; |
699 | 636aaad7 | j_mayer | break;
|
700 | 636aaad7 | j_mayer | case 3: |
701 | 636aaad7 | j_mayer | next = 1 << 29; |
702 | 636aaad7 | j_mayer | break;
|
703 | 636aaad7 | j_mayer | default:
|
704 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
705 | 636aaad7 | j_mayer | return;
|
706 | 636aaad7 | j_mayer | } |
707 | 636aaad7 | j_mayer | next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); |
708 | 636aaad7 | j_mayer | if (next == now)
|
709 | 636aaad7 | j_mayer | next++; |
710 | 636aaad7 | j_mayer | if (loglevel) {
|
711 | e96efcfc | j_mayer | fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__, |
712 | 636aaad7 | j_mayer | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
713 | 636aaad7 | j_mayer | } |
714 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
715 | 636aaad7 | j_mayer | case 0x0: |
716 | 636aaad7 | j_mayer | case 0x1: |
717 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
718 | 636aaad7 | j_mayer | ppcemb_timer->wdt_next = next; |
719 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 31; |
720 | 636aaad7 | j_mayer | break;
|
721 | 636aaad7 | j_mayer | case 0x2: |
722 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
723 | 636aaad7 | j_mayer | ppcemb_timer->wdt_next = next; |
724 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 30; |
725 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) |
726 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
|
727 | 636aaad7 | j_mayer | break;
|
728 | 636aaad7 | j_mayer | case 0x3: |
729 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] &= ~0x30000000;
|
730 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
|
731 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { |
732 | 636aaad7 | j_mayer | case 0x0: |
733 | 636aaad7 | j_mayer | /* No reset */
|
734 | 636aaad7 | j_mayer | break;
|
735 | 636aaad7 | j_mayer | case 0x1: /* Core reset */ |
736 | 636aaad7 | j_mayer | case 0x2: /* Chip reset */ |
737 | 636aaad7 | j_mayer | case 0x3: /* System reset */ |
738 | 636aaad7 | j_mayer | qemu_system_reset_request(); |
739 | 636aaad7 | j_mayer | return;
|
740 | 636aaad7 | j_mayer | } |
741 | 636aaad7 | j_mayer | } |
742 | 76a66253 | j_mayer | } |
743 | 76a66253 | j_mayer | |
744 | 76a66253 | j_mayer | void store_40x_pit (CPUState *env, target_ulong val)
|
745 | 76a66253 | j_mayer | { |
746 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
747 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
748 | 636aaad7 | j_mayer | uint64_t now, next; |
749 | 636aaad7 | j_mayer | |
750 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
751 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
752 | a496775f | j_mayer | if (loglevel) {
|
753 | 636aaad7 | j_mayer | fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
|
754 | a496775f | j_mayer | } |
755 | 636aaad7 | j_mayer | ppcemb_timer->pit_reload = val; |
756 | 636aaad7 | j_mayer | if (val == 0) { |
757 | 636aaad7 | j_mayer | /* Stop PIT */
|
758 | a496775f | j_mayer | if (loglevel) {
|
759 | 636aaad7 | j_mayer | fprintf(logfile, "%s: stop PIT\n", __func__);
|
760 | a496775f | j_mayer | } |
761 | 636aaad7 | j_mayer | qemu_del_timer(tb_env->decr_timer); |
762 | 636aaad7 | j_mayer | } else {
|
763 | a496775f | j_mayer | if (loglevel) {
|
764 | e96efcfc | j_mayer | fprintf(logfile, "%s: start PIT 0x" ADDRX "\n", __func__, val); |
765 | a496775f | j_mayer | } |
766 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
767 | 636aaad7 | j_mayer | next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq); |
768 | 636aaad7 | j_mayer | if (next == now)
|
769 | 636aaad7 | j_mayer | next++; |
770 | 636aaad7 | j_mayer | qemu_mod_timer(tb_env->decr_timer, next); |
771 | 636aaad7 | j_mayer | tb_env->decr_next = next; |
772 | 636aaad7 | j_mayer | } |
773 | 76a66253 | j_mayer | } |
774 | 76a66253 | j_mayer | |
775 | 636aaad7 | j_mayer | target_ulong load_40x_pit (CPUState *env) |
776 | 76a66253 | j_mayer | { |
777 | 636aaad7 | j_mayer | return cpu_ppc_load_decr(env);
|
778 | 76a66253 | j_mayer | } |
779 | 76a66253 | j_mayer | |
780 | 76a66253 | j_mayer | void store_booke_tsr (CPUState *env, target_ulong val)
|
781 | 76a66253 | j_mayer | { |
782 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] = val & 0xFC000000;
|
783 | 636aaad7 | j_mayer | } |
784 | 636aaad7 | j_mayer | |
785 | 636aaad7 | j_mayer | void store_booke_tcr (CPUState *env, target_ulong val)
|
786 | 636aaad7 | j_mayer | { |
787 | 636aaad7 | j_mayer | /* We don't update timers now. Maybe we should... */
|
788 | 636aaad7 | j_mayer | env->spr[SPR_40x_TCR] = val & 0xFF800000;
|
789 | 636aaad7 | j_mayer | } |
790 | 636aaad7 | j_mayer | |
791 | 636aaad7 | j_mayer | void ppc_emb_timers_init (CPUState *env)
|
792 | 636aaad7 | j_mayer | { |
793 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
794 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
795 | 636aaad7 | j_mayer | |
796 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
797 | 636aaad7 | j_mayer | ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
|
798 | 636aaad7 | j_mayer | tb_env->opaque = ppcemb_timer; |
799 | 636aaad7 | j_mayer | if (loglevel)
|
800 | 636aaad7 | j_mayer | fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
|
801 | 636aaad7 | j_mayer | if (ppcemb_timer != NULL) { |
802 | 636aaad7 | j_mayer | /* We use decr timer for PIT */
|
803 | 636aaad7 | j_mayer | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); |
804 | 636aaad7 | j_mayer | ppcemb_timer->fit_timer = |
805 | 636aaad7 | j_mayer | qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); |
806 | 636aaad7 | j_mayer | ppcemb_timer->wdt_timer = |
807 | 636aaad7 | j_mayer | qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); |
808 | 636aaad7 | j_mayer | } |
809 | 76a66253 | j_mayer | } |
810 | 76a66253 | j_mayer | |
811 | 2e719ba3 | j_mayer | /*****************************************************************************/
|
812 | 2e719ba3 | j_mayer | /* Embedded PowerPC Device Control Registers */
|
813 | 2e719ba3 | j_mayer | typedef struct ppc_dcrn_t ppc_dcrn_t; |
814 | 2e719ba3 | j_mayer | struct ppc_dcrn_t {
|
815 | 2e719ba3 | j_mayer | dcr_read_cb dcr_read; |
816 | 2e719ba3 | j_mayer | dcr_write_cb dcr_write; |
817 | 2e719ba3 | j_mayer | void *opaque;
|
818 | 2e719ba3 | j_mayer | }; |
819 | 2e719ba3 | j_mayer | |
820 | 2e719ba3 | j_mayer | #define DCRN_NB 1024 |
821 | 2e719ba3 | j_mayer | struct ppc_dcr_t {
|
822 | 2e719ba3 | j_mayer | ppc_dcrn_t dcrn[DCRN_NB]; |
823 | 2e719ba3 | j_mayer | int (*read_error)(int dcrn); |
824 | 2e719ba3 | j_mayer | int (*write_error)(int dcrn); |
825 | 2e719ba3 | j_mayer | }; |
826 | 2e719ba3 | j_mayer | |
827 | 2e719ba3 | j_mayer | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) |
828 | 2e719ba3 | j_mayer | { |
829 | 2e719ba3 | j_mayer | ppc_dcrn_t *dcr; |
830 | 2e719ba3 | j_mayer | |
831 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
832 | 2e719ba3 | j_mayer | goto error;
|
833 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
834 | 2e719ba3 | j_mayer | if (dcr->dcr_read == NULL) |
835 | 2e719ba3 | j_mayer | goto error;
|
836 | 2e719ba3 | j_mayer | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); |
837 | 2e719ba3 | j_mayer | |
838 | 2e719ba3 | j_mayer | return 0; |
839 | 2e719ba3 | j_mayer | |
840 | 2e719ba3 | j_mayer | error:
|
841 | 2e719ba3 | j_mayer | if (dcr_env->read_error != NULL) |
842 | 2e719ba3 | j_mayer | return (*dcr_env->read_error)(dcrn);
|
843 | 2e719ba3 | j_mayer | |
844 | 2e719ba3 | j_mayer | return -1; |
845 | 2e719ba3 | j_mayer | } |
846 | 2e719ba3 | j_mayer | |
847 | 2e719ba3 | j_mayer | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) |
848 | 2e719ba3 | j_mayer | { |
849 | 2e719ba3 | j_mayer | ppc_dcrn_t *dcr; |
850 | 2e719ba3 | j_mayer | |
851 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
852 | 2e719ba3 | j_mayer | goto error;
|
853 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
854 | 2e719ba3 | j_mayer | if (dcr->dcr_write == NULL) |
855 | 2e719ba3 | j_mayer | goto error;
|
856 | 2e719ba3 | j_mayer | (*dcr->dcr_write)(dcr->opaque, dcrn, val); |
857 | 2e719ba3 | j_mayer | |
858 | 2e719ba3 | j_mayer | return 0; |
859 | 2e719ba3 | j_mayer | |
860 | 2e719ba3 | j_mayer | error:
|
861 | 2e719ba3 | j_mayer | if (dcr_env->write_error != NULL) |
862 | 2e719ba3 | j_mayer | return (*dcr_env->write_error)(dcrn);
|
863 | 2e719ba3 | j_mayer | |
864 | 2e719ba3 | j_mayer | return -1; |
865 | 2e719ba3 | j_mayer | } |
866 | 2e719ba3 | j_mayer | |
867 | 2e719ba3 | j_mayer | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
868 | 2e719ba3 | j_mayer | dcr_read_cb dcr_read, dcr_write_cb dcr_write) |
869 | 2e719ba3 | j_mayer | { |
870 | 2e719ba3 | j_mayer | ppc_dcr_t *dcr_env; |
871 | 2e719ba3 | j_mayer | ppc_dcrn_t *dcr; |
872 | 2e719ba3 | j_mayer | |
873 | 2e719ba3 | j_mayer | dcr_env = env->dcr_env; |
874 | 2e719ba3 | j_mayer | if (dcr_env == NULL) |
875 | 2e719ba3 | j_mayer | return -1; |
876 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
877 | 2e719ba3 | j_mayer | return -1; |
878 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
879 | 2e719ba3 | j_mayer | if (dcr->opaque != NULL || |
880 | 2e719ba3 | j_mayer | dcr->dcr_read != NULL ||
|
881 | 2e719ba3 | j_mayer | dcr->dcr_write != NULL)
|
882 | 2e719ba3 | j_mayer | return -1; |
883 | 2e719ba3 | j_mayer | dcr->opaque = opaque; |
884 | 2e719ba3 | j_mayer | dcr->dcr_read = dcr_read; |
885 | 2e719ba3 | j_mayer | dcr->dcr_write = dcr_write; |
886 | 2e719ba3 | j_mayer | |
887 | 2e719ba3 | j_mayer | return 0; |
888 | 2e719ba3 | j_mayer | } |
889 | 2e719ba3 | j_mayer | |
890 | 2e719ba3 | j_mayer | int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), |
891 | 2e719ba3 | j_mayer | int (*write_error)(int dcrn)) |
892 | 2e719ba3 | j_mayer | { |
893 | 2e719ba3 | j_mayer | ppc_dcr_t *dcr_env; |
894 | 2e719ba3 | j_mayer | |
895 | 2e719ba3 | j_mayer | dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
|
896 | 2e719ba3 | j_mayer | if (dcr_env == NULL) |
897 | 2e719ba3 | j_mayer | return -1; |
898 | 2e719ba3 | j_mayer | dcr_env->read_error = read_error; |
899 | 2e719ba3 | j_mayer | dcr_env->write_error = write_error; |
900 | 2e719ba3 | j_mayer | env->dcr_env = dcr_env; |
901 | 2e719ba3 | j_mayer | |
902 | 2e719ba3 | j_mayer | return 0; |
903 | 2e719ba3 | j_mayer | } |
904 | 2e719ba3 | j_mayer | |
905 | 2e719ba3 | j_mayer | |
906 | 9fddaa0c | bellard | #if 0
|
907 | 9fddaa0c | bellard | /*****************************************************************************/
|
908 | 9fddaa0c | bellard | /* Handle system reset (for now, just stop emulation) */
|
909 | 9fddaa0c | bellard | void cpu_ppc_reset (CPUState *env)
|
910 | 9fddaa0c | bellard | {
|
911 | 9fddaa0c | bellard | printf("Reset asked... Stop emulation\n");
|
912 | 9fddaa0c | bellard | abort();
|
913 | 9fddaa0c | bellard | }
|
914 | 9fddaa0c | bellard | #endif
|
915 | 9fddaa0c | bellard | |
916 | 64201201 | bellard | /*****************************************************************************/
|
917 | 64201201 | bellard | /* Debug port */
|
918 | fd0bbb12 | bellard | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
919 | 64201201 | bellard | { |
920 | 64201201 | bellard | addr &= 0xF;
|
921 | 64201201 | bellard | switch (addr) {
|
922 | 64201201 | bellard | case 0: |
923 | 64201201 | bellard | printf("%c", val);
|
924 | 64201201 | bellard | break;
|
925 | 64201201 | bellard | case 1: |
926 | 64201201 | bellard | printf("\n");
|
927 | 64201201 | bellard | fflush(stdout); |
928 | 64201201 | bellard | break;
|
929 | 64201201 | bellard | case 2: |
930 | 64201201 | bellard | printf("Set loglevel to %04x\n", val);
|
931 | fd0bbb12 | bellard | cpu_set_log(val | 0x100);
|
932 | 64201201 | bellard | break;
|
933 | 64201201 | bellard | } |
934 | 64201201 | bellard | } |
935 | 64201201 | bellard | |
936 | 64201201 | bellard | /*****************************************************************************/
|
937 | 64201201 | bellard | /* NVRAM helpers */
|
938 | 64201201 | bellard | void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
|
939 | 64201201 | bellard | { |
940 | 819385c5 | bellard | m48t59_write(nvram, addr, value); |
941 | 64201201 | bellard | } |
942 | 64201201 | bellard | |
943 | 64201201 | bellard | uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr) |
944 | 64201201 | bellard | { |
945 | 819385c5 | bellard | return m48t59_read(nvram, addr);
|
946 | 64201201 | bellard | } |
947 | 64201201 | bellard | |
948 | 64201201 | bellard | void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
|
949 | 64201201 | bellard | { |
950 | 819385c5 | bellard | m48t59_write(nvram, addr, value >> 8);
|
951 | 819385c5 | bellard | m48t59_write(nvram, addr + 1, value & 0xFF); |
952 | 64201201 | bellard | } |
953 | 64201201 | bellard | |
954 | 64201201 | bellard | uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr) |
955 | 64201201 | bellard | { |
956 | 64201201 | bellard | uint16_t tmp; |
957 | 64201201 | bellard | |
958 | 819385c5 | bellard | tmp = m48t59_read(nvram, addr) << 8;
|
959 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 1);
|
960 | 64201201 | bellard | return tmp;
|
961 | 64201201 | bellard | } |
962 | 64201201 | bellard | |
963 | 64201201 | bellard | void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
|
964 | 64201201 | bellard | { |
965 | 819385c5 | bellard | m48t59_write(nvram, addr, value >> 24);
|
966 | 819385c5 | bellard | m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF); |
967 | 819385c5 | bellard | m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF); |
968 | 819385c5 | bellard | m48t59_write(nvram, addr + 3, value & 0xFF); |
969 | 64201201 | bellard | } |
970 | 64201201 | bellard | |
971 | 64201201 | bellard | uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr) |
972 | 64201201 | bellard | { |
973 | 64201201 | bellard | uint32_t tmp; |
974 | 64201201 | bellard | |
975 | 819385c5 | bellard | tmp = m48t59_read(nvram, addr) << 24;
|
976 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 1) << 16; |
977 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 2) << 8; |
978 | 819385c5 | bellard | tmp |= m48t59_read(nvram, addr + 3);
|
979 | 76a66253 | j_mayer | |
980 | 64201201 | bellard | return tmp;
|
981 | 64201201 | bellard | } |
982 | 64201201 | bellard | |
983 | 64201201 | bellard | void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
|
984 | 64201201 | bellard | const unsigned char *str, uint32_t max) |
985 | 64201201 | bellard | { |
986 | 64201201 | bellard | int i;
|
987 | 64201201 | bellard | |
988 | 64201201 | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
989 | 819385c5 | bellard | m48t59_write(nvram, addr + i, str[i]); |
990 | 64201201 | bellard | } |
991 | 819385c5 | bellard | m48t59_write(nvram, addr + max - 1, '\0'); |
992 | 64201201 | bellard | } |
993 | 64201201 | bellard | |
994 | 64201201 | bellard | int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max) |
995 | 64201201 | bellard | { |
996 | 64201201 | bellard | int i;
|
997 | 64201201 | bellard | |
998 | 64201201 | bellard | memset(dst, 0, max);
|
999 | 64201201 | bellard | for (i = 0; i < max; i++) { |
1000 | 64201201 | bellard | dst[i] = NVRAM_get_byte(nvram, addr + i); |
1001 | 64201201 | bellard | if (dst[i] == '\0') |
1002 | 64201201 | bellard | break;
|
1003 | 64201201 | bellard | } |
1004 | 64201201 | bellard | |
1005 | 64201201 | bellard | return i;
|
1006 | 64201201 | bellard | } |
1007 | 64201201 | bellard | |
1008 | 64201201 | bellard | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
|
1009 | 64201201 | bellard | { |
1010 | 64201201 | bellard | uint16_t tmp; |
1011 | 64201201 | bellard | uint16_t pd, pd1, pd2; |
1012 | 64201201 | bellard | |
1013 | 64201201 | bellard | tmp = prev >> 8;
|
1014 | 64201201 | bellard | pd = prev ^ value; |
1015 | 64201201 | bellard | pd1 = pd & 0x000F;
|
1016 | 64201201 | bellard | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
1017 | 64201201 | bellard | tmp ^= (pd1 << 3) | (pd1 << 8); |
1018 | 64201201 | bellard | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
1019 | 64201201 | bellard | |
1020 | 64201201 | bellard | return tmp;
|
1021 | 64201201 | bellard | } |
1022 | 64201201 | bellard | |
1023 | 64201201 | bellard | uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count) |
1024 | 64201201 | bellard | { |
1025 | 64201201 | bellard | uint32_t i; |
1026 | 64201201 | bellard | uint16_t crc = 0xFFFF;
|
1027 | 64201201 | bellard | int odd;
|
1028 | 64201201 | bellard | |
1029 | 64201201 | bellard | odd = count & 1;
|
1030 | 64201201 | bellard | count &= ~1;
|
1031 | 64201201 | bellard | for (i = 0; i != count; i++) { |
1032 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
1033 | 64201201 | bellard | } |
1034 | 64201201 | bellard | if (odd) {
|
1035 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
1036 | 64201201 | bellard | } |
1037 | 64201201 | bellard | |
1038 | 64201201 | bellard | return crc;
|
1039 | 64201201 | bellard | } |
1040 | 64201201 | bellard | |
1041 | fd0bbb12 | bellard | #define CMDLINE_ADDR 0x017ff000 |
1042 | fd0bbb12 | bellard | |
1043 | 64201201 | bellard | int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
1044 | 64201201 | bellard | const unsigned char *arch, |
1045 | 64201201 | bellard | uint32_t RAM_size, int boot_device,
|
1046 | 64201201 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
1047 | fd0bbb12 | bellard | const char *cmdline, |
1048 | 64201201 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
1049 | fd0bbb12 | bellard | uint32_t NVRAM_image, |
1050 | fd0bbb12 | bellard | int width, int height, int depth) |
1051 | 64201201 | bellard | { |
1052 | 64201201 | bellard | uint16_t crc; |
1053 | 64201201 | bellard | |
1054 | 64201201 | bellard | /* Set parameters for Open Hack'Ware BIOS */
|
1055 | 64201201 | bellard | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
1056 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
1057 | 64201201 | bellard | NVRAM_set_word(nvram, 0x14, NVRAM_size);
|
1058 | 64201201 | bellard | NVRAM_set_string(nvram, 0x20, arch, 16); |
1059 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x30, RAM_size);
|
1060 | 64201201 | bellard | NVRAM_set_byte(nvram, 0x34, boot_device);
|
1061 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x38, kernel_image);
|
1062 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x3C, kernel_size);
|
1063 | fd0bbb12 | bellard | if (cmdline) {
|
1064 | fd0bbb12 | bellard | /* XXX: put the cmdline in NVRAM too ? */
|
1065 | fd0bbb12 | bellard | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
1066 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
1067 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
|
1068 | fd0bbb12 | bellard | } else {
|
1069 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, 0); |
1070 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, 0); |
1071 | fd0bbb12 | bellard | } |
1072 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x48, initrd_image);
|
1073 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x4C, initrd_size);
|
1074 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x50, NVRAM_image);
|
1075 | fd0bbb12 | bellard | |
1076 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x54, width);
|
1077 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x56, height);
|
1078 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x58, depth);
|
1079 | fd0bbb12 | bellard | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
1080 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0xFC, crc);
|
1081 | 64201201 | bellard | |
1082 | 64201201 | bellard | return 0; |
1083 | a541f297 | bellard | } |