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/*
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 * QEMU generic PowerPC hardware System Emulator
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 * 
4
 * Copyright (c) 2003-2007 Jocelyn Mayer
5
 * 
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "vl.h"
25
#include "m48t59.h"
26

    
27
//#define PPC_DEBUG_IRQ
28

    
29
extern FILE *logfile;
30
extern int loglevel;
31

    
32
void ppc_set_irq (CPUState *env, int n_IRQ, int level)
33
{
34
    if (level) {
35
        env->pending_interrupts |= 1 << n_IRQ;
36
        cpu_interrupt(env, CPU_INTERRUPT_HARD);
37
    } else {
38
        env->pending_interrupts &= ~(1 << n_IRQ);
39
        if (env->pending_interrupts == 0)
40
            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
41
    }
42
#if defined(PPC_DEBUG_IRQ)
43
    if (loglevel & CPU_LOG_INT) {
44
        fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08x req %08x\n",
45
                __func__, env, n_IRQ, level,
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                env->pending_interrupts, env->interrupt_request);
47
    }
48
#endif
49
}
50

    
51
/* PowerPC 6xx / 7xx internal IRQ controller */
52
static void ppc6xx_set_irq (void *opaque, int pin, int level)
53
{
54
    CPUState *env = opaque;
55
    int cur_level;
56

    
57
#if defined(PPC_DEBUG_IRQ)
58
    if (loglevel & CPU_LOG_INT) {
59
        fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
60
                env, pin, level);
61
    }
62
#endif
63
    cur_level = (env->irq_input_state >> pin) & 1;
64
    /* Don't generate spurious events */
65
    if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
66
        switch (pin) {
67
        case PPC6xx_INPUT_INT:
68
            /* Level sensitive - active high */
69
#if defined(PPC_DEBUG_IRQ)
70
            if (loglevel & CPU_LOG_INT) {
71
                fprintf(logfile, "%s: set the external IRQ state to %d\n",
72
                        __func__, level);
73
            }
74
#endif
75
            ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
76
            break;
77
        case PPC6xx_INPUT_SMI:
78
            /* Level sensitive - active high */
79
#if defined(PPC_DEBUG_IRQ)
80
            if (loglevel & CPU_LOG_INT) {
81
                fprintf(logfile, "%s: set the SMI IRQ state to %d\n",
82
                        __func__, level);
83
            }
84
#endif
85
            ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
86
            break;
87
        case PPC6xx_INPUT_MCP:
88
            /* Negative edge sensitive */
89
            /* XXX: TODO: actual reaction may depends on HID0 status
90
             *            603/604/740/750: check HID0[EMCP]
91
             */
92
            if (cur_level == 1 && level == 0) {
93
#if defined(PPC_DEBUG_IRQ)
94
                if (loglevel & CPU_LOG_INT) {
95
                    fprintf(logfile, "%s: raise machine check state\n",
96
                            __func__);
97
                }
98
#endif
99
                ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
100
            }
101
            break;
102
        case PPC6xx_INPUT_CKSTP_IN:
103
            /* Level sensitive - active low */
104
            /* XXX: TODO: relay the signal to CKSTP_OUT pin */
105
            if (level) {
106
#if defined(PPC_DEBUG_IRQ)
107
                if (loglevel & CPU_LOG_INT) {
108
                    fprintf(logfile, "%s: stop the CPU\n", __func__);
109
                }
110
#endif
111
                env->halted = 1;
112
            } else {
113
#if defined(PPC_DEBUG_IRQ)
114
                if (loglevel & CPU_LOG_INT) {
115
                    fprintf(logfile, "%s: restart the CPU\n", __func__);
116
                }
117
#endif
118
                env->halted = 0;
119
            }
120
            break;
121
        case PPC6xx_INPUT_HRESET:
122
            /* Level sensitive - active low */
123
            if (level) {
124
#if 0 // XXX: TOFIX
125
#if defined(PPC_DEBUG_IRQ)
126
                if (loglevel & CPU_LOG_INT) {
127
                    fprintf(logfile, "%s: reset the CPU\n", __func__);
128
                }
129
#endif
130
                cpu_reset(env);
131
#endif
132
            }
133
            break;
134
        case PPC6xx_INPUT_SRESET:
135
#if defined(PPC_DEBUG_IRQ)
136
            if (loglevel & CPU_LOG_INT) {
137
                fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
138
                        __func__, level);
139
            }
140
#endif
141
            ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
142
            break;
143
        default:
144
            /* Unknown pin - do nothing */
145
#if defined(PPC_DEBUG_IRQ)
146
            if (loglevel & CPU_LOG_INT) {
147
                fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
148
            }
149
#endif
150
            return;
151
        }
152
        if (level)
153
            env->irq_input_state |= 1 << pin;
154
        else
155
            env->irq_input_state &= ~(1 << pin);
156
    }
157
}
158

    
159
void ppc6xx_irq_init (CPUState *env)
160
{
161
    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, 6);
162
}
163

    
164
/* PowerPC 970 internal IRQ controller */
165
static void ppc970_set_irq (void *opaque, int pin, int level)
166
{
167
    CPUState *env = opaque;
168
    int cur_level;
169

    
170
#if defined(PPC_DEBUG_IRQ)
171
    if (loglevel & CPU_LOG_INT) {
172
        fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
173
                env, pin, level);
174
    }
175
#endif
176
    cur_level = (env->irq_input_state >> pin) & 1;
177
    /* Don't generate spurious events */
178
    if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
179
        switch (pin) {
180
        case PPC970_INPUT_INT:
181
            /* Level sensitive - active high */
182
#if defined(PPC_DEBUG_IRQ)
183
            if (loglevel & CPU_LOG_INT) {
184
                fprintf(logfile, "%s: set the external IRQ state to %d\n",
185
                        __func__, level);
186
            }
187
#endif
188
            ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
189
            break;
190
        case PPC970_INPUT_THINT:
191
            /* Level sensitive - active high */
192
#if defined(PPC_DEBUG_IRQ)
193
            if (loglevel & CPU_LOG_INT) {
194
                fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
195
                        level);
196
            }
197
#endif
198
            ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
199
            break;
200
        case PPC970_INPUT_MCP:
201
            /* Negative edge sensitive */
202
            /* XXX: TODO: actual reaction may depends on HID0 status
203
             *            603/604/740/750: check HID0[EMCP]
204
             */
205
            if (cur_level == 1 && level == 0) {
206
#if defined(PPC_DEBUG_IRQ)
207
                if (loglevel & CPU_LOG_INT) {
208
                    fprintf(logfile, "%s: raise machine check state\n",
209
                            __func__);
210
                }
211
#endif
212
                ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
213
            }
214
            break;
215
        case PPC970_INPUT_CKSTP:
216
            /* Level sensitive - active low */
217
            /* XXX: TODO: relay the signal to CKSTP_OUT pin */
218
            if (level) {
219
#if defined(PPC_DEBUG_IRQ)
220
                if (loglevel & CPU_LOG_INT) {
221
                    fprintf(logfile, "%s: stop the CPU\n", __func__);
222
                }
223
#endif
224
                env->halted = 1;
225
            } else {
226
#if defined(PPC_DEBUG_IRQ)
227
                if (loglevel & CPU_LOG_INT) {
228
                    fprintf(logfile, "%s: restart the CPU\n", __func__);
229
                }
230
#endif
231
                env->halted = 0;
232
            }
233
            break;
234
        case PPC970_INPUT_HRESET:
235
            /* Level sensitive - active low */
236
            if (level) {
237
#if 0 // XXX: TOFIX
238
#if defined(PPC_DEBUG_IRQ)
239
                if (loglevel & CPU_LOG_INT) {
240
                    fprintf(logfile, "%s: reset the CPU\n", __func__);
241
                }
242
#endif
243
                cpu_reset(env);
244
#endif
245
            }
246
            break;
247
        case PPC970_INPUT_SRESET:
248
#if defined(PPC_DEBUG_IRQ)
249
            if (loglevel & CPU_LOG_INT) {
250
                fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
251
                        __func__, level);
252
            }
253
#endif
254
            ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
255
            break;
256
        case PPC970_INPUT_TBEN:
257
#if defined(PPC_DEBUG_IRQ)
258
            if (loglevel & CPU_LOG_INT) {
259
                fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
260
                        level);
261
            }
262
#endif
263
            /* XXX: TODO */
264
            break;
265
        default:
266
            /* Unknown pin - do nothing */
267
#if defined(PPC_DEBUG_IRQ)
268
            if (loglevel & CPU_LOG_INT) {
269
                fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
270
            }
271
#endif
272
            return;
273
        }
274
        if (level)
275
            env->irq_input_state |= 1 << pin;
276
        else
277
            env->irq_input_state &= ~(1 << pin);
278
    }
279
}
280

    
281
void ppc970_irq_init (CPUState *env)
282
{
283
    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, 7);
284
}
285

    
286
/* PowerPC 405 internal IRQ controller */
287
static void ppc405_set_irq (void *opaque, int pin, int level)
288
{
289
    CPUState *env = opaque;
290
    int cur_level;
291

    
292
#if defined(PPC_DEBUG_IRQ)
293
    printf("%s: env %p pin %d level %d\n", __func__, env, pin, level);
294
#endif
295
    cur_level = (env->irq_input_state >> pin) & 1;
296
    /* Don't generate spurious events */
297
    if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
298
        switch (pin) {
299
        case PPC405_INPUT_RESET_SYS:
300
            /* XXX: TODO: reset all peripherals */
301
            /* No break here */
302
        case PPC405_INPUT_RESET_CHIP:
303
            /* XXX: TODO: reset on-chip peripherals */
304
            /* No break here */
305
        case PPC405_INPUT_RESET_CORE:
306
            /* XXX: TODO: update DBSR[MRR] */
307
            if (level) {
308
#if 0 // XXX: TOFIX
309
#if defined(PPC_DEBUG_IRQ)
310
                printf("%s: reset the CPU\n", __func__);
311
#endif
312
                cpu_reset(env);
313
#endif
314
            }
315
            break;
316
        case PPC405_INPUT_CINT:
317
            /* Level sensitive - active high */
318
#if defined(PPC_DEBUG_IRQ)
319
            printf("%s: set the critical IRQ state to %d\n", __func__, level);
320
#endif
321
            /* XXX: TOFIX */
322
            ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
323
            break;
324
        case PPC405_INPUT_INT:
325
            /* Level sensitive - active high */
326
#if defined(PPC_DEBUG_IRQ)
327
            if (loglevel & CPU_LOG_INT) {
328
                fprintf(logfile, "%s: set the external IRQ state to %d\n",
329
                        __func__, level);
330
            }
331
#endif
332
            ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
333
            break;
334
        case PPC405_INPUT_HALT:
335
            /* Level sensitive - active low */
336
            if (level) {
337
#if defined(PPC_DEBUG_IRQ)
338
                if (loglevel & CPU_LOG_INT) {
339
                    fprintf(logfile, "%s: stop the CPU\n", __func__);
340
                }
341
#endif
342
                env->halted = 1;
343
            } else {
344
#if defined(PPC_DEBUG_IRQ)
345
                if (loglevel & CPU_LOG_INT) {
346
                    fprintf(logfile, "%s: restart the CPU\n", __func__);
347
                }
348
#endif
349
                env->halted = 0;
350
            }
351
            break;
352
        case PPC405_INPUT_DEBUG:
353
            /* Level sensitive - active high */
354
#if defined(PPC_DEBUG_IRQ)
355
            if (loglevel & CPU_LOG_INT) {
356
                fprintf(logfile, "%s: set the external IRQ state to %d\n",
357
                        __func__, level);
358
            }
359
#endif
360
            ppc_set_irq(env, EXCP_40x_DEBUG, level);
361
            break;
362
        default:
363
            /* Unknown pin - do nothing */
364
#if defined(PPC_DEBUG_IRQ)
365
            if (loglevel & CPU_LOG_INT) {
366
                fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
367
            }
368
#endif
369
            return;
370
        }
371
        if (level)
372
            env->irq_input_state |= 1 << pin;
373
        else
374
            env->irq_input_state &= ~(1 << pin);
375
    }
376
}
377

    
378
void ppc405_irq_init (CPUState *env)
379
{
380
    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc405_set_irq, env, 7);
381
}
382

    
383
/*****************************************************************************/
384
/* PowerPC time base and decrementer emulation */
385
//#define DEBUG_TB
386

    
387
struct ppc_tb_t {
388
    /* Time base management */
389
    int64_t  tb_offset;    /* Compensation               */
390
    uint32_t tb_freq;      /* TB frequency               */
391
    /* Decrementer management */
392
    uint64_t decr_next;    /* Tick for next decr interrupt  */
393
    struct QEMUTimer *decr_timer;
394
    void *opaque;
395
};
396

    
397
static inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env)
398
{
399
    /* TB time in tb periods */
400
    return muldiv64(qemu_get_clock(vm_clock) + tb_env->tb_offset,
401
                    tb_env->tb_freq, ticks_per_sec);
402
}
403

    
404
uint32_t cpu_ppc_load_tbl (CPUState *env)
405
{
406
    ppc_tb_t *tb_env = env->tb_env;
407
    uint64_t tb;
408

    
409
    tb = cpu_ppc_get_tb(tb_env);
410
#ifdef DEBUG_TB
411
    {
412
        static int last_time;
413
        int now;
414
        now = time(NULL);
415
        if (last_time != now) {
416
            last_time = now;
417
            if (loglevel) {
418
                fprintf(logfile, "%s: tb=0x%016lx %d %08lx\n",
419
                        __func__, tb, now, tb_env->tb_offset);
420
            }
421
        }
422
    }
423
#endif
424

    
425
    return tb & 0xFFFFFFFF;
426
}
427

    
428
uint32_t cpu_ppc_load_tbu (CPUState *env)
429
{
430
    ppc_tb_t *tb_env = env->tb_env;
431
    uint64_t tb;
432

    
433
    tb = cpu_ppc_get_tb(tb_env);
434
#ifdef DEBUG_TB
435
    if (loglevel) {
436
        fprintf(logfile, "%s: tb=0x%016lx\n", __func__, tb);
437
    }
438
#endif
439

    
440
    return tb >> 32;
441
}
442

    
443
static void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t value)
444
{
445
    tb_env->tb_offset = muldiv64(value, ticks_per_sec, tb_env->tb_freq)
446
        - qemu_get_clock(vm_clock);
447
#ifdef DEBUG_TB
448
    if (loglevel) {
449
        fprintf(logfile, "%s: tb=0x%016lx offset=%08x\n", __func__, value);
450
    }
451
#endif
452
}
453

    
454
void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
455
{
456
    ppc_tb_t *tb_env = env->tb_env;
457

    
458
    cpu_ppc_store_tb(tb_env,
459
                     ((uint64_t)value << 32) | cpu_ppc_load_tbl(env));
460
}
461

    
462
void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
463
{
464
    ppc_tb_t *tb_env = env->tb_env;
465

    
466
    cpu_ppc_store_tb(tb_env,
467
                     ((uint64_t)cpu_ppc_load_tbu(env) << 32) | value);
468
}
469

    
470
uint32_t cpu_ppc_load_decr (CPUState *env)
471
{
472
    ppc_tb_t *tb_env = env->tb_env;
473
    uint32_t decr;
474
    int64_t diff;
475

    
476
    diff = tb_env->decr_next - qemu_get_clock(vm_clock);
477
    if (diff >= 0)
478
        decr = muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
479
    else
480
        decr = -muldiv64(-diff, tb_env->tb_freq, ticks_per_sec);
481
#if defined(DEBUG_TB)
482
    if (loglevel) {
483
        fprintf(logfile, "%s: 0x%08x\n", __func__, decr);
484
    }
485
#endif
486

    
487
    return decr;
488
}
489

    
490
/* When decrementer expires,
491
 * all we need to do is generate or queue a CPU exception
492
 */
493
static inline void cpu_ppc_decr_excp (CPUState *env)
494
{
495
    /* Raise it */
496
#ifdef DEBUG_TB
497
    if (loglevel) {
498
        fprintf(logfile, "raise decrementer exception\n");
499
    }
500
#endif
501
    ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
502
}
503

    
504
static void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,
505
                                 uint32_t value, int is_excp)
506
{
507
    ppc_tb_t *tb_env = env->tb_env;
508
    uint64_t now, next;
509

    
510
#ifdef DEBUG_TB
511
    if (loglevel) {
512
        fprintf(logfile, "%s: 0x%08x => 0x%08x\n", __func__, decr, value);
513
    }
514
#endif
515
    now = qemu_get_clock(vm_clock);
516
    next = now + muldiv64(value, ticks_per_sec, tb_env->tb_freq);
517
    if (is_excp)
518
        next += tb_env->decr_next - now;
519
    if (next == now)
520
        next++;
521
    tb_env->decr_next = next;
522
    /* Adjust timer */
523
    qemu_mod_timer(tb_env->decr_timer, next);
524
    /* If we set a negative value and the decrementer was positive,
525
     * raise an exception.
526
     */
527
    if ((value & 0x80000000) && !(decr & 0x80000000))
528
        cpu_ppc_decr_excp(env);
529
}
530

    
531
void cpu_ppc_store_decr (CPUState *env, uint32_t value)
532
{
533
    _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
534
}
535

    
536
static void cpu_ppc_decr_cb (void *opaque)
537
{
538
    _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);
539
}
540

    
541
/* Set up (once) timebase frequency (in Hz) */
542
ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq)
543
{
544
    ppc_tb_t *tb_env;
545

    
546
    tb_env = qemu_mallocz(sizeof(ppc_tb_t));
547
    if (tb_env == NULL)
548
        return NULL;
549
    env->tb_env = tb_env;
550
    if (tb_env->tb_freq == 0 || 1) {
551
        tb_env->tb_freq = freq;
552
        /* Create new timer */
553
        tb_env->decr_timer =
554
            qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);
555
        /* There is a bug in Linux 2.4 kernels:
556
         * if a decrementer exception is pending when it enables msr_ee,
557
         * it's not ready to handle it...
558
         */
559
        _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);
560
    }
561

    
562
    return tb_env;
563
}
564

    
565
/* Specific helpers for POWER & PowerPC 601 RTC */
566
ppc_tb_t *cpu_ppc601_rtc_init (CPUState *env)
567
{
568
    return cpu_ppc_tb_init(env, 7812500);
569
}
570

    
571
void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
572
__attribute__ (( alias ("cpu_ppc_store_tbu") ));
573

    
574
uint32_t cpu_ppc601_load_rtcu (CPUState *env)
575
__attribute__ (( alias ("cpu_ppc_load_tbu") ));
576

    
577
void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
578
{
579
    cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
580
}
581

    
582
uint32_t cpu_ppc601_load_rtcl (CPUState *env)
583
{
584
    return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
585
}
586

    
587
/*****************************************************************************/
588
/* Embedded PowerPC timers */
589

    
590
/* PIT, FIT & WDT */
591
typedef struct ppcemb_timer_t ppcemb_timer_t;
592
struct ppcemb_timer_t {
593
    uint64_t pit_reload;  /* PIT auto-reload value        */
594
    uint64_t fit_next;    /* Tick for next FIT interrupt  */
595
    struct QEMUTimer *fit_timer;
596
    uint64_t wdt_next;    /* Tick for next WDT interrupt  */
597
    struct QEMUTimer *wdt_timer;
598
};
599
   
600
/* Fixed interval timer */
601
static void cpu_4xx_fit_cb (void *opaque)
602
{
603
    CPUState *env;
604
    ppc_tb_t *tb_env;
605
    ppcemb_timer_t *ppcemb_timer;
606
    uint64_t now, next;
607

    
608
    env = opaque;
609
    tb_env = env->tb_env;
610
    ppcemb_timer = tb_env->opaque;
611
    now = qemu_get_clock(vm_clock);
612
    switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
613
    case 0:
614
        next = 1 << 9;
615
        break;
616
    case 1:
617
        next = 1 << 13;
618
        break;
619
    case 2:
620
        next = 1 << 17;
621
        break;
622
    case 3:
623
        next = 1 << 21;
624
        break;
625
    default:
626
        /* Cannot occur, but makes gcc happy */
627
        return;
628
    }
629
    next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
630
    if (next == now)
631
        next++;
632
    qemu_mod_timer(ppcemb_timer->fit_timer, next);
633
    tb_env->decr_next = next;
634
    env->spr[SPR_40x_TSR] |= 1 << 26;
635
    if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
636
        ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
637
    if (loglevel) {
638
        fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
639
                (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
640
                env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
641
    }
642
}
643

    
644
/* Programmable interval timer */
645
static void cpu_4xx_pit_cb (void *opaque)
646
{
647
    CPUState *env;
648
    ppc_tb_t *tb_env;
649
    ppcemb_timer_t *ppcemb_timer;
650
    uint64_t now, next;
651

    
652
    env = opaque;
653
    tb_env = env->tb_env;
654
    ppcemb_timer = tb_env->opaque;
655
    now = qemu_get_clock(vm_clock);
656
    if ((env->spr[SPR_40x_TCR] >> 22) & 0x1) {
657
        /* Auto reload */
658
        next = now + muldiv64(ppcemb_timer->pit_reload,
659
                              ticks_per_sec, tb_env->tb_freq);
660
        if (next == now)
661
            next++;
662
        qemu_mod_timer(tb_env->decr_timer, next);
663
        tb_env->decr_next = next;
664
    }
665
    env->spr[SPR_40x_TSR] |= 1 << 27;
666
    if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
667
        ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
668
    if (loglevel) {
669
        fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
670
                "%016" PRIx64 "\n", __func__,
671
                (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
672
                (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
673
                env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
674
                ppcemb_timer->pit_reload);
675
    }
676
}
677

    
678
/* Watchdog timer */
679
static void cpu_4xx_wdt_cb (void *opaque)
680
{
681
    CPUState *env;
682
    ppc_tb_t *tb_env;
683
    ppcemb_timer_t *ppcemb_timer;
684
    uint64_t now, next;
685

    
686
    env = opaque;
687
    tb_env = env->tb_env;
688
    ppcemb_timer = tb_env->opaque;
689
    now = qemu_get_clock(vm_clock);
690
    switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
691
    case 0:
692
        next = 1 << 17;
693
        break;
694
    case 1:
695
        next = 1 << 21;
696
        break;
697
    case 2:
698
        next = 1 << 25;
699
        break;
700
    case 3:
701
        next = 1 << 29;
702
        break;
703
    default:
704
        /* Cannot occur, but makes gcc happy */
705
        return;
706
    }
707
    next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);
708
    if (next == now)
709
        next++;
710
    if (loglevel) {
711
        fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
712
                env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
713
    }
714
    switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
715
    case 0x0:
716
    case 0x1:
717
        qemu_mod_timer(ppcemb_timer->wdt_timer, next);
718
        ppcemb_timer->wdt_next = next;
719
        env->spr[SPR_40x_TSR] |= 1 << 31;
720
        break;
721
    case 0x2:
722
        qemu_mod_timer(ppcemb_timer->wdt_timer, next);
723
        ppcemb_timer->wdt_next = next;
724
        env->spr[SPR_40x_TSR] |= 1 << 30;
725
        if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)
726
            ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
727
        break;
728
    case 0x3:
729
        env->spr[SPR_40x_TSR] &= ~0x30000000;
730
        env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
731
        switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
732
        case 0x0:
733
            /* No reset */
734
            break;
735
        case 0x1: /* Core reset */
736
        case 0x2: /* Chip reset */
737
        case 0x3: /* System reset */
738
            qemu_system_reset_request();
739
            return;
740
        }
741
    }
742
}
743

    
744
void store_40x_pit (CPUState *env, target_ulong val)
745
{
746
    ppc_tb_t *tb_env;
747
    ppcemb_timer_t *ppcemb_timer;
748
    uint64_t now, next;
749

    
750
    tb_env = env->tb_env;
751
    ppcemb_timer = tb_env->opaque;
752
    if (loglevel) {
753
        fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
754
    }
755
    ppcemb_timer->pit_reload = val;
756
    if (val == 0) {
757
        /* Stop PIT */
758
        if (loglevel) {
759
            fprintf(logfile, "%s: stop PIT\n", __func__);
760
        }
761
        qemu_del_timer(tb_env->decr_timer);
762
    } else {
763
        if (loglevel) {
764
            fprintf(logfile, "%s: start PIT 0x" ADDRX "\n", __func__, val);
765
        }
766
        now = qemu_get_clock(vm_clock);
767
        next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq);
768
         if (next == now)
769
            next++;
770
        qemu_mod_timer(tb_env->decr_timer, next);
771
        tb_env->decr_next = next;
772
    }
773
}
774

    
775
target_ulong load_40x_pit (CPUState *env)
776
{
777
    return cpu_ppc_load_decr(env);
778
}
779

    
780
void store_booke_tsr (CPUState *env, target_ulong val)
781
{
782
    env->spr[SPR_40x_TSR] = val & 0xFC000000;
783
}
784

    
785
void store_booke_tcr (CPUState *env, target_ulong val)
786
{
787
    /* We don't update timers now. Maybe we should... */
788
    env->spr[SPR_40x_TCR] = val & 0xFF800000;
789
}
790

    
791
void ppc_emb_timers_init (CPUState *env)
792
{
793
    ppc_tb_t *tb_env;
794
    ppcemb_timer_t *ppcemb_timer;
795

    
796
    tb_env = env->tb_env;
797
    ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
798
    tb_env->opaque = ppcemb_timer;
799
    if (loglevel)
800
        fprintf(logfile, "%s %p %p\n", __func__, tb_env, ppcemb_timer);
801
    if (ppcemb_timer != NULL) {
802
        /* We use decr timer for PIT */
803
        tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);
804
        ppcemb_timer->fit_timer =
805
            qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env);
806
        ppcemb_timer->wdt_timer =
807
            qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);
808
    }
809
}
810

    
811
/*****************************************************************************/
812
/* Embedded PowerPC Device Control Registers */
813
typedef struct ppc_dcrn_t ppc_dcrn_t;
814
struct ppc_dcrn_t {
815
    dcr_read_cb dcr_read;
816
    dcr_write_cb dcr_write;
817
    void *opaque;
818
};
819

    
820
#define DCRN_NB 1024
821
struct ppc_dcr_t {
822
    ppc_dcrn_t dcrn[DCRN_NB];
823
    int (*read_error)(int dcrn);
824
    int (*write_error)(int dcrn);
825
};
826

    
827
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
828
{
829
    ppc_dcrn_t *dcr;
830

    
831
    if (dcrn < 0 || dcrn >= DCRN_NB)
832
        goto error;
833
    dcr = &dcr_env->dcrn[dcrn];
834
    if (dcr->dcr_read == NULL)
835
        goto error;
836
    *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
837

    
838
    return 0;
839

    
840
 error:
841
    if (dcr_env->read_error != NULL)
842
        return (*dcr_env->read_error)(dcrn);
843

    
844
    return -1;
845
}
846

    
847
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
848
{
849
    ppc_dcrn_t *dcr;
850

    
851
    if (dcrn < 0 || dcrn >= DCRN_NB)
852
        goto error;
853
    dcr = &dcr_env->dcrn[dcrn];
854
    if (dcr->dcr_write == NULL)
855
        goto error;
856
    (*dcr->dcr_write)(dcr->opaque, dcrn, val);
857

    
858
    return 0;
859

    
860
 error:
861
    if (dcr_env->write_error != NULL)
862
        return (*dcr_env->write_error)(dcrn);
863

    
864
    return -1;
865
}
866

    
867
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
868
                      dcr_read_cb dcr_read, dcr_write_cb dcr_write)
869
{
870
    ppc_dcr_t *dcr_env;
871
    ppc_dcrn_t *dcr;
872

    
873
    dcr_env = env->dcr_env;
874
    if (dcr_env == NULL)
875
        return -1;
876
    if (dcrn < 0 || dcrn >= DCRN_NB)
877
        return -1;
878
    dcr = &dcr_env->dcrn[dcrn];
879
    if (dcr->opaque != NULL ||
880
        dcr->dcr_read != NULL ||
881
        dcr->dcr_write != NULL)
882
        return -1;
883
    dcr->opaque = opaque;
884
    dcr->dcr_read = dcr_read;
885
    dcr->dcr_write = dcr_write;
886

    
887
    return 0;
888
}
889

    
890
int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
891
                  int (*write_error)(int dcrn))
892
{
893
    ppc_dcr_t *dcr_env;
894

    
895
    dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
896
    if (dcr_env == NULL)
897
        return -1;
898
    dcr_env->read_error = read_error;
899
    dcr_env->write_error = write_error;
900
    env->dcr_env = dcr_env;
901

    
902
    return 0;
903
}
904

    
905

    
906
#if 0
907
/*****************************************************************************/
908
/* Handle system reset (for now, just stop emulation) */
909
void cpu_ppc_reset (CPUState *env)
910
{
911
    printf("Reset asked... Stop emulation\n");
912
    abort();
913
}
914
#endif
915

    
916
/*****************************************************************************/
917
/* Debug port */
918
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
919
{
920
    addr &= 0xF;
921
    switch (addr) {
922
    case 0:
923
        printf("%c", val);
924
        break;
925
    case 1:
926
        printf("\n");
927
        fflush(stdout);
928
        break;
929
    case 2:
930
        printf("Set loglevel to %04x\n", val);
931
        cpu_set_log(val | 0x100);
932
        break;
933
    }
934
}
935

    
936
/*****************************************************************************/
937
/* NVRAM helpers */
938
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
939
{
940
    m48t59_write(nvram, addr, value);
941
}
942

    
943
uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
944
{
945
    return m48t59_read(nvram, addr);
946
}
947

    
948
void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
949
{
950
    m48t59_write(nvram, addr, value >> 8);
951
    m48t59_write(nvram, addr + 1, value & 0xFF);
952
}
953

    
954
uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
955
{
956
    uint16_t tmp;
957

    
958
    tmp = m48t59_read(nvram, addr) << 8;
959
    tmp |= m48t59_read(nvram, addr + 1);
960
    return tmp;
961
}
962

    
963
void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
964
{
965
    m48t59_write(nvram, addr, value >> 24);
966
    m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
967
    m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
968
    m48t59_write(nvram, addr + 3, value & 0xFF);
969
}
970

    
971
uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
972
{
973
    uint32_t tmp;
974

    
975
    tmp = m48t59_read(nvram, addr) << 24;
976
    tmp |= m48t59_read(nvram, addr + 1) << 16;
977
    tmp |= m48t59_read(nvram, addr + 2) << 8;
978
    tmp |= m48t59_read(nvram, addr + 3);
979

    
980
    return tmp;
981
}
982

    
983
void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
984
                       const unsigned char *str, uint32_t max)
985
{
986
    int i;
987

    
988
    for (i = 0; i < max && str[i] != '\0'; i++) {
989
        m48t59_write(nvram, addr + i, str[i]);
990
    }
991
    m48t59_write(nvram, addr + max - 1, '\0');
992
}
993

    
994
int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
995
{
996
    int i;
997

    
998
    memset(dst, 0, max);
999
    for (i = 0; i < max; i++) {
1000
        dst[i] = NVRAM_get_byte(nvram, addr + i);
1001
        if (dst[i] == '\0')
1002
            break;
1003
    }
1004

    
1005
    return i;
1006
}
1007

    
1008
static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
1009
{
1010
    uint16_t tmp;
1011
    uint16_t pd, pd1, pd2;
1012

    
1013
    tmp = prev >> 8;
1014
    pd = prev ^ value;
1015
    pd1 = pd & 0x000F;
1016
    pd2 = ((pd >> 4) & 0x000F) ^ pd1;
1017
    tmp ^= (pd1 << 3) | (pd1 << 8);
1018
    tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
1019

    
1020
    return tmp;
1021
}
1022

    
1023
uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
1024
{
1025
    uint32_t i;
1026
    uint16_t crc = 0xFFFF;
1027
    int odd;
1028

    
1029
    odd = count & 1;
1030
    count &= ~1;
1031
    for (i = 0; i != count; i++) {
1032
        crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
1033
    }
1034
    if (odd) {
1035
        crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
1036
    }
1037

    
1038
    return crc;
1039
}
1040

    
1041
#define CMDLINE_ADDR 0x017ff000
1042

    
1043
int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1044
                          const unsigned char *arch,
1045
                          uint32_t RAM_size, int boot_device,
1046
                          uint32_t kernel_image, uint32_t kernel_size,
1047
                          const char *cmdline,
1048
                          uint32_t initrd_image, uint32_t initrd_size,
1049
                          uint32_t NVRAM_image,
1050
                          int width, int height, int depth)
1051
{
1052
    uint16_t crc;
1053

    
1054
    /* Set parameters for Open Hack'Ware BIOS */
1055
    NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
1056
    NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
1057
    NVRAM_set_word(nvram,   0x14, NVRAM_size);
1058
    NVRAM_set_string(nvram, 0x20, arch, 16);
1059
    NVRAM_set_lword(nvram,  0x30, RAM_size);
1060
    NVRAM_set_byte(nvram,   0x34, boot_device);
1061
    NVRAM_set_lword(nvram,  0x38, kernel_image);
1062
    NVRAM_set_lword(nvram,  0x3C, kernel_size);
1063
    if (cmdline) {
1064
        /* XXX: put the cmdline in NVRAM too ? */
1065
        strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
1066
        NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
1067
        NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
1068
    } else {
1069
        NVRAM_set_lword(nvram,  0x40, 0);
1070
        NVRAM_set_lword(nvram,  0x44, 0);
1071
    }
1072
    NVRAM_set_lword(nvram,  0x48, initrd_image);
1073
    NVRAM_set_lword(nvram,  0x4C, initrd_size);
1074
    NVRAM_set_lword(nvram,  0x50, NVRAM_image);
1075

    
1076
    NVRAM_set_word(nvram,   0x54, width);
1077
    NVRAM_set_word(nvram,   0x56, height);
1078
    NVRAM_set_word(nvram,   0x58, depth);
1079
    crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
1080
    NVRAM_set_word(nvram,  0xFC, crc);
1081

    
1082
    return 0;
1083
}