root / target-ppc / translate_init.c @ d0dfae6e
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/*
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* PowerPC CPU initialization for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* A lot of PowerPC definition have been included here.
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* Most of them are not usable for now but have been kept
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* inside "#if defined(TODO) ... #endif" statements to make tests easier.
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*/
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//#define PPC_DUMP_CPU
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//#define PPC_DEBUG_SPR
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//#define PPC_DEBUG_IRQ
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struct ppc_def_t {
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const unsigned char *name; |
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uint32_t pvr; |
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uint32_t pvr_mask; |
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uint64_t insns_flags; |
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uint32_t flags; |
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uint64_t msr_mask; |
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}; |
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/* For user-mode emulation, we don't emulate any IRQ controller */
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#if defined(CONFIG_USER_ONLY)
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#define PPC_IRQ_INIT_FN(name) \
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static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \ |
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{ \
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} |
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#else
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#define PPC_IRQ_INIT_FN(name) \
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void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
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#endif
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PPC_IRQ_INIT_FN(405);
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PPC_IRQ_INIT_FN(6xx);
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PPC_IRQ_INIT_FN(970);
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/* Generic callbacks:
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* do nothing but store/retrieve spr value
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*/
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static void spr_read_generic (void *opaque, int sprn) |
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{
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gen_op_load_spr(sprn); |
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} |
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static void spr_write_generic (void *opaque, int sprn) |
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{
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gen_op_store_spr(sprn); |
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} |
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static void spr_read_dump (void *opaque, int sprn) |
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{
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gen_op_load_dump_spr(sprn); |
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} |
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static void spr_write_dump (void *opaque, int sprn) |
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{
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gen_op_store_dump_spr(sprn); |
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} |
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_clear (void *opaque, int sprn) |
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{
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gen_op_mask_spr(sprn); |
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} |
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#endif
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/* SPR common to all PowerPC */
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/* XER */
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static void spr_read_xer (void *opaque, int sprn) |
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{
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gen_op_load_xer(); |
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} |
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static void spr_write_xer (void *opaque, int sprn) |
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{
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gen_op_store_xer(); |
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} |
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/* LR */
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static void spr_read_lr (void *opaque, int sprn) |
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{
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gen_op_load_lr(); |
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} |
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static void spr_write_lr (void *opaque, int sprn) |
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{
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gen_op_store_lr(); |
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} |
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/* CTR */
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static void spr_read_ctr (void *opaque, int sprn) |
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{
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gen_op_load_ctr(); |
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} |
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static void spr_write_ctr (void *opaque, int sprn) |
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{
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gen_op_store_ctr(); |
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} |
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/* User read access to SPR */
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/* USPRx */
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/* UMMCRx */
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/* UPMCx */
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/* USIA */
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/* UDECR */
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static void spr_read_ureg (void *opaque, int sprn) |
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{
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gen_op_load_spr(sprn + 0x10);
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} |
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/* SPR common to all non-embedded PowerPC */
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/* DECR */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_decr (void *opaque, int sprn) |
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{
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gen_op_load_decr(); |
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} |
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static void spr_write_decr (void *opaque, int sprn) |
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{
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gen_op_store_decr(); |
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} |
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#endif
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/* SPR common to all non-embedded PowerPC, except 601 */
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/* Time base */
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static void spr_read_tbl (void *opaque, int sprn) |
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{
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gen_op_load_tbl(); |
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} |
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static void spr_read_tbu (void *opaque, int sprn) |
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{
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gen_op_load_tbu(); |
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} |
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_tbl (void *opaque, int sprn) |
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{
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gen_op_store_tbl(); |
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} |
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static void spr_write_tbu (void *opaque, int sprn) |
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{
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gen_op_store_tbu(); |
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} |
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#endif
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#if !defined(CONFIG_USER_ONLY)
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/* IBAT0U...IBAT0U */
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/* IBAT0L...IBAT7L */
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static void spr_read_ibat (void *opaque, int sprn) |
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{
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gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2); |
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} |
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static void spr_read_ibat_h (void *opaque, int sprn) |
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{
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gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2); |
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} |
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static void spr_write_ibatu (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_ibatu_h (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_ibatl (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_ibatl_h (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
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RET_STOP(ctx); |
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} |
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/* DBAT0U...DBAT7U */
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/* DBAT0L...DBAT7L */
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static void spr_read_dbat (void *opaque, int sprn) |
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{
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gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2); |
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} |
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static void spr_read_dbat_h (void *opaque, int sprn) |
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{
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gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2); |
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} |
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static void spr_write_dbatu (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_dbatu_h (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_dbatl (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_dbatl_h (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
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RET_STOP(ctx); |
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} |
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/* SDR1 */
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static void spr_read_sdr1 (void *opaque, int sprn) |
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{
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gen_op_load_sdr1(); |
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} |
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static void spr_write_sdr1 (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_sdr1(); |
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RET_STOP(ctx); |
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} |
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/* 64 bits PowerPC specific SPRs */
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/* ASR */
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#if defined(TARGET_PPC64)
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static void spr_read_asr (void *opaque, int sprn) |
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{
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gen_op_load_asr(); |
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} |
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static void spr_write_asr (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_asr(); |
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RET_STOP(ctx); |
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} |
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#endif
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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/* PowerPC 601 specific registers */
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/* RTC */
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static void spr_read_601_rtcl (void *opaque, int sprn) |
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{
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gen_op_load_601_rtcl(); |
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} |
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static void spr_read_601_rtcu (void *opaque, int sprn) |
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{
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gen_op_load_601_rtcu(); |
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} |
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#if !defined(CONFIG_USER_ONLY)
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static void spr_write_601_rtcu (void *opaque, int sprn) |
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{
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gen_op_store_601_rtcu(); |
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} |
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static void spr_write_601_rtcl (void *opaque, int sprn) |
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{
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gen_op_store_601_rtcl(); |
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} |
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#endif
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/* Unified bats */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_601_ubat (void *opaque, int sprn) |
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{
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gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2); |
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} |
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static void spr_write_601_ubatu (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
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RET_STOP(ctx); |
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} |
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static void spr_write_601_ubatl (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
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RET_STOP(ctx); |
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} |
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#endif
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/* PowerPC 40x specific registers */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_40x_pit (void *opaque, int sprn) |
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{
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gen_op_load_40x_pit(); |
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} |
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static void spr_write_40x_pit (void *opaque, int sprn) |
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{
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gen_op_store_40x_pit(); |
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} |
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static void spr_write_booke_tcr (void *opaque, int sprn) |
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{
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gen_op_store_booke_tcr(); |
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} |
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static void spr_write_booke_tsr (void *opaque, int sprn) |
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{
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gen_op_store_booke_tsr(); |
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} |
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#endif
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/* PowerPC 403 specific registers */
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/* PBL1 / PBU1 / PBL2 / PBU2 */
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#if !defined(CONFIG_USER_ONLY)
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static void spr_read_403_pbr (void *opaque, int sprn) |
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{
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gen_op_load_403_pb(sprn - SPR_403_PBL1); |
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} |
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static void spr_write_403_pbr (void *opaque, int sprn) |
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{
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DisasContext *ctx = opaque; |
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gen_op_store_403_pb(sprn - SPR_403_PBL1); |
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RET_STOP(ctx); |
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} |
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static void spr_write_pir (void *opaque, int sprn) |
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{
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gen_op_store_pir(); |
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} |
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#endif
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#if defined(CONFIG_USER_ONLY)
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#define spr_register(env, num, name, uea_read, uea_write, \
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oea_read, oea_write, initial_value) \ |
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do { \
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_spr_register(env, num, name, uea_read, uea_write, initial_value); \ |
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} while (0) |
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static inline void _spr_register (CPUPPCState *env, int num, |
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const unsigned char *name, |
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void (*uea_read)(void *opaque, int sprn), |
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void (*uea_write)(void *opaque, int sprn), |
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target_ulong initial_value) |
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#else
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static inline void spr_register (CPUPPCState *env, int num, |
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const unsigned char *name, |
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void (*uea_read)(void *opaque, int sprn), |
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void (*uea_write)(void *opaque, int sprn), |
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void (*oea_read)(void *opaque, int sprn), |
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void (*oea_write)(void *opaque, int sprn), |
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target_ulong initial_value) |
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#endif
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{
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ppc_spr_t *spr; |
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spr = &env->spr_cb[num]; |
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if (spr->name != NULL ||env-> spr[num] != 0x00000000 || |
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#if !defined(CONFIG_USER_ONLY)
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spr->oea_read != NULL || spr->oea_write != NULL || |
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#endif
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spr->uea_read != NULL || spr->uea_write != NULL) { |
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printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
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exit(1);
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} |
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#if defined(PPC_DEBUG_SPR)
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printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name, |
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initial_value); |
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#endif
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spr->name = name; |
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spr->uea_read = uea_read; |
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spr->uea_write = uea_write; |
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#if !defined(CONFIG_USER_ONLY)
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spr->oea_read = oea_read; |
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spr->oea_write = oea_write; |
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#endif
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env->spr[num] = initial_value; |
| 424 |
} |
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/* Generic PowerPC SPRs */
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static void gen_spr_generic (CPUPPCState *env) |
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{
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/* Integer processing */
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spr_register(env, SPR_XER, "XER",
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&spr_read_xer, &spr_write_xer, |
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&spr_read_xer, &spr_write_xer, |
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0x00000000);
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/* Branch contol */
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spr_register(env, SPR_LR, "LR",
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&spr_read_lr, &spr_write_lr, |
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&spr_read_lr, &spr_write_lr, |
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0x00000000);
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spr_register(env, SPR_CTR, "CTR",
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&spr_read_ctr, &spr_write_ctr, |
| 441 |
&spr_read_ctr, &spr_write_ctr, |
| 442 |
0x00000000);
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/* Interrupt processing */
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spr_register(env, SPR_SRR0, "SRR0",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
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0x00000000);
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spr_register(env, SPR_SRR1, "SRR1",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
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0x00000000);
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/* Processor control */
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spr_register(env, SPR_SPRG0, "SPRG0",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
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0x00000000);
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spr_register(env, SPR_SPRG1, "SPRG1",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
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0x00000000);
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spr_register(env, SPR_SPRG2, "SPRG2",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
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0x00000000);
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spr_register(env, SPR_SPRG3, "SPRG3",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
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0x00000000);
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} |
| 470 |
|
| 471 |
/* SPR common to all non-embedded PowerPC, including 601 */
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| 472 |
static void gen_spr_ne_601 (CPUPPCState *env) |
| 473 |
{
|
| 474 |
/* Exception processing */
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| 475 |
spr_register(env, SPR_DSISR, "DSISR",
|
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
| 478 |
0x00000000);
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spr_register(env, SPR_DAR, "DAR",
|
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_generic, &spr_write_generic, |
| 482 |
0x00000000);
|
| 483 |
/* Timer */
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| 484 |
spr_register(env, SPR_DECR, "DECR",
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SPR_NOACCESS, SPR_NOACCESS, |
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&spr_read_decr, &spr_write_decr, |
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0x00000000);
|
| 488 |
/* Memory management */
|
| 489 |
spr_register(env, SPR_SDR1, "SDR1",
|
| 490 |
SPR_NOACCESS, SPR_NOACCESS, |
| 491 |
&spr_read_sdr1, &spr_write_sdr1, |
| 492 |
0x00000000);
|
| 493 |
} |
| 494 |
|
| 495 |
/* BATs 0-3 */
|
| 496 |
static void gen_low_BATs (CPUPPCState *env) |
| 497 |
{
|
| 498 |
spr_register(env, SPR_IBAT0U, "IBAT0U",
|
| 499 |
SPR_NOACCESS, SPR_NOACCESS, |
| 500 |
&spr_read_ibat, &spr_write_ibatu, |
| 501 |
0x00000000);
|
| 502 |
spr_register(env, SPR_IBAT0L, "IBAT0L",
|
| 503 |
SPR_NOACCESS, SPR_NOACCESS, |
| 504 |
&spr_read_ibat, &spr_write_ibatl, |
| 505 |
0x00000000);
|
| 506 |
spr_register(env, SPR_IBAT1U, "IBAT1U",
|
| 507 |
SPR_NOACCESS, SPR_NOACCESS, |
| 508 |
&spr_read_ibat, &spr_write_ibatu, |
| 509 |
0x00000000);
|
| 510 |
spr_register(env, SPR_IBAT1L, "IBAT1L",
|
| 511 |
SPR_NOACCESS, SPR_NOACCESS, |
| 512 |
&spr_read_ibat, &spr_write_ibatl, |
| 513 |
0x00000000);
|
| 514 |
spr_register(env, SPR_IBAT2U, "IBAT2U",
|
| 515 |
SPR_NOACCESS, SPR_NOACCESS, |
| 516 |
&spr_read_ibat, &spr_write_ibatu, |
| 517 |
0x00000000);
|
| 518 |
spr_register(env, SPR_IBAT2L, "IBAT2L",
|
| 519 |
SPR_NOACCESS, SPR_NOACCESS, |
| 520 |
&spr_read_ibat, &spr_write_ibatl, |
| 521 |
0x00000000);
|
| 522 |
spr_register(env, SPR_IBAT3U, "IBAT3U",
|
| 523 |
SPR_NOACCESS, SPR_NOACCESS, |
| 524 |
&spr_read_ibat, &spr_write_ibatu, |
| 525 |
0x00000000);
|
| 526 |
spr_register(env, SPR_IBAT3L, "IBAT3L",
|
| 527 |
SPR_NOACCESS, SPR_NOACCESS, |
| 528 |
&spr_read_ibat, &spr_write_ibatl, |
| 529 |
0x00000000);
|
| 530 |
spr_register(env, SPR_DBAT0U, "DBAT0U",
|
| 531 |
SPR_NOACCESS, SPR_NOACCESS, |
| 532 |
&spr_read_dbat, &spr_write_dbatu, |
| 533 |
0x00000000);
|
| 534 |
spr_register(env, SPR_DBAT0L, "DBAT0L",
|
| 535 |
SPR_NOACCESS, SPR_NOACCESS, |
| 536 |
&spr_read_dbat, &spr_write_dbatl, |
| 537 |
0x00000000);
|
| 538 |
spr_register(env, SPR_DBAT1U, "DBAT1U",
|
| 539 |
SPR_NOACCESS, SPR_NOACCESS, |
| 540 |
&spr_read_dbat, &spr_write_dbatu, |
| 541 |
0x00000000);
|
| 542 |
spr_register(env, SPR_DBAT1L, "DBAT1L",
|
| 543 |
SPR_NOACCESS, SPR_NOACCESS, |
| 544 |
&spr_read_dbat, &spr_write_dbatl, |
| 545 |
0x00000000);
|
| 546 |
spr_register(env, SPR_DBAT2U, "DBAT2U",
|
| 547 |
SPR_NOACCESS, SPR_NOACCESS, |
| 548 |
&spr_read_dbat, &spr_write_dbatu, |
| 549 |
0x00000000);
|
| 550 |
spr_register(env, SPR_DBAT2L, "DBAT2L",
|
| 551 |
SPR_NOACCESS, SPR_NOACCESS, |
| 552 |
&spr_read_dbat, &spr_write_dbatl, |
| 553 |
0x00000000);
|
| 554 |
spr_register(env, SPR_DBAT3U, "DBAT3U",
|
| 555 |
SPR_NOACCESS, SPR_NOACCESS, |
| 556 |
&spr_read_dbat, &spr_write_dbatu, |
| 557 |
0x00000000);
|
| 558 |
spr_register(env, SPR_DBAT3L, "DBAT3L",
|
| 559 |
SPR_NOACCESS, SPR_NOACCESS, |
| 560 |
&spr_read_dbat, &spr_write_dbatl, |
| 561 |
0x00000000);
|
| 562 |
env->nb_BATs = 4;
|
| 563 |
} |
| 564 |
|
| 565 |
/* BATs 4-7 */
|
| 566 |
static void gen_high_BATs (CPUPPCState *env) |
| 567 |
{
|
| 568 |
spr_register(env, SPR_IBAT4U, "IBAT4U",
|
| 569 |
SPR_NOACCESS, SPR_NOACCESS, |
| 570 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
| 571 |
0x00000000);
|
| 572 |
spr_register(env, SPR_IBAT4L, "IBAT4L",
|
| 573 |
SPR_NOACCESS, SPR_NOACCESS, |
| 574 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
| 575 |
0x00000000);
|
| 576 |
spr_register(env, SPR_IBAT5U, "IBAT5U",
|
| 577 |
SPR_NOACCESS, SPR_NOACCESS, |
| 578 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
| 579 |
0x00000000);
|
| 580 |
spr_register(env, SPR_IBAT5L, "IBAT5L",
|
| 581 |
SPR_NOACCESS, SPR_NOACCESS, |
| 582 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
| 583 |
0x00000000);
|
| 584 |
spr_register(env, SPR_IBAT6U, "IBAT6U",
|
| 585 |
SPR_NOACCESS, SPR_NOACCESS, |
| 586 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
| 587 |
0x00000000);
|
| 588 |
spr_register(env, SPR_IBAT6L, "IBAT6L",
|
| 589 |
SPR_NOACCESS, SPR_NOACCESS, |
| 590 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
| 591 |
0x00000000);
|
| 592 |
spr_register(env, SPR_IBAT7U, "IBAT7U",
|
| 593 |
SPR_NOACCESS, SPR_NOACCESS, |
| 594 |
&spr_read_ibat_h, &spr_write_ibatu_h, |
| 595 |
0x00000000);
|
| 596 |
spr_register(env, SPR_IBAT7L, "IBAT7L",
|
| 597 |
SPR_NOACCESS, SPR_NOACCESS, |
| 598 |
&spr_read_ibat_h, &spr_write_ibatl_h, |
| 599 |
0x00000000);
|
| 600 |
spr_register(env, SPR_DBAT4U, "DBAT4U",
|
| 601 |
SPR_NOACCESS, SPR_NOACCESS, |
| 602 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
| 603 |
0x00000000);
|
| 604 |
spr_register(env, SPR_DBAT4L, "DBAT4L",
|
| 605 |
SPR_NOACCESS, SPR_NOACCESS, |
| 606 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
| 607 |
0x00000000);
|
| 608 |
spr_register(env, SPR_DBAT5U, "DBAT5U",
|
| 609 |
SPR_NOACCESS, SPR_NOACCESS, |
| 610 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
| 611 |
0x00000000);
|
| 612 |
spr_register(env, SPR_DBAT5L, "DBAT5L",
|
| 613 |
SPR_NOACCESS, SPR_NOACCESS, |
| 614 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
| 615 |
0x00000000);
|
| 616 |
spr_register(env, SPR_DBAT6U, "DBAT6U",
|
| 617 |
SPR_NOACCESS, SPR_NOACCESS, |
| 618 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
| 619 |
0x00000000);
|
| 620 |
spr_register(env, SPR_DBAT6L, "DBAT6L",
|
| 621 |
SPR_NOACCESS, SPR_NOACCESS, |
| 622 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
| 623 |
0x00000000);
|
| 624 |
spr_register(env, SPR_DBAT7U, "DBAT7U",
|
| 625 |
SPR_NOACCESS, SPR_NOACCESS, |
| 626 |
&spr_read_dbat_h, &spr_write_dbatu_h, |
| 627 |
0x00000000);
|
| 628 |
spr_register(env, SPR_DBAT7L, "DBAT7L",
|
| 629 |
SPR_NOACCESS, SPR_NOACCESS, |
| 630 |
&spr_read_dbat_h, &spr_write_dbatl_h, |
| 631 |
0x00000000);
|
| 632 |
env->nb_BATs = 8;
|
| 633 |
} |
| 634 |
|
| 635 |
/* Generic PowerPC time base */
|
| 636 |
static void gen_tbl (CPUPPCState *env) |
| 637 |
{
|
| 638 |
spr_register(env, SPR_VTBL, "TBL",
|
| 639 |
&spr_read_tbl, SPR_NOACCESS, |
| 640 |
&spr_read_tbl, SPR_NOACCESS, |
| 641 |
0x00000000);
|
| 642 |
spr_register(env, SPR_TBL, "TBL",
|
| 643 |
SPR_NOACCESS, SPR_NOACCESS, |
| 644 |
SPR_NOACCESS, &spr_write_tbl, |
| 645 |
0x00000000);
|
| 646 |
spr_register(env, SPR_VTBU, "TBU",
|
| 647 |
&spr_read_tbu, SPR_NOACCESS, |
| 648 |
&spr_read_tbu, SPR_NOACCESS, |
| 649 |
0x00000000);
|
| 650 |
spr_register(env, SPR_TBU, "TBU",
|
| 651 |
SPR_NOACCESS, SPR_NOACCESS, |
| 652 |
SPR_NOACCESS, &spr_write_tbu, |
| 653 |
0x00000000);
|
| 654 |
} |
| 655 |
|
| 656 |
/* Softare table search registers */
|
| 657 |
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) |
| 658 |
{
|
| 659 |
env->nb_tlb = nb_tlbs; |
| 660 |
env->nb_ways = nb_ways; |
| 661 |
env->id_tlbs = 1;
|
| 662 |
spr_register(env, SPR_DMISS, "DMISS",
|
| 663 |
SPR_NOACCESS, SPR_NOACCESS, |
| 664 |
&spr_read_generic, SPR_NOACCESS, |
| 665 |
0x00000000);
|
| 666 |
spr_register(env, SPR_DCMP, "DCMP",
|
| 667 |
SPR_NOACCESS, SPR_NOACCESS, |
| 668 |
&spr_read_generic, SPR_NOACCESS, |
| 669 |
0x00000000);
|
| 670 |
spr_register(env, SPR_HASH1, "HASH1",
|
| 671 |
SPR_NOACCESS, SPR_NOACCESS, |
| 672 |
&spr_read_generic, SPR_NOACCESS, |
| 673 |
0x00000000);
|
| 674 |
spr_register(env, SPR_HASH2, "HASH2",
|
| 675 |
SPR_NOACCESS, SPR_NOACCESS, |
| 676 |
&spr_read_generic, SPR_NOACCESS, |
| 677 |
0x00000000);
|
| 678 |
spr_register(env, SPR_IMISS, "IMISS",
|
| 679 |
SPR_NOACCESS, SPR_NOACCESS, |
| 680 |
&spr_read_generic, SPR_NOACCESS, |
| 681 |
0x00000000);
|
| 682 |
spr_register(env, SPR_ICMP, "ICMP",
|
| 683 |
SPR_NOACCESS, SPR_NOACCESS, |
| 684 |
&spr_read_generic, SPR_NOACCESS, |
| 685 |
0x00000000);
|
| 686 |
spr_register(env, SPR_RPA, "RPA",
|
| 687 |
SPR_NOACCESS, SPR_NOACCESS, |
| 688 |
&spr_read_generic, &spr_write_generic, |
| 689 |
0x00000000);
|
| 690 |
} |
| 691 |
|
| 692 |
/* SPR common to MPC755 and G2 */
|
| 693 |
static void gen_spr_G2_755 (CPUPPCState *env) |
| 694 |
{
|
| 695 |
/* SGPRs */
|
| 696 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
| 697 |
SPR_NOACCESS, SPR_NOACCESS, |
| 698 |
&spr_read_generic, &spr_write_generic, |
| 699 |
0x00000000);
|
| 700 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
| 701 |
SPR_NOACCESS, SPR_NOACCESS, |
| 702 |
&spr_read_generic, &spr_write_generic, |
| 703 |
0x00000000);
|
| 704 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
| 705 |
SPR_NOACCESS, SPR_NOACCESS, |
| 706 |
&spr_read_generic, &spr_write_generic, |
| 707 |
0x00000000);
|
| 708 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
| 709 |
SPR_NOACCESS, SPR_NOACCESS, |
| 710 |
&spr_read_generic, &spr_write_generic, |
| 711 |
0x00000000);
|
| 712 |
/* External access control */
|
| 713 |
/* XXX : not implemented */
|
| 714 |
spr_register(env, SPR_EAR, "EAR",
|
| 715 |
SPR_NOACCESS, SPR_NOACCESS, |
| 716 |
&spr_read_generic, &spr_write_generic, |
| 717 |
0x00000000);
|
| 718 |
} |
| 719 |
|
| 720 |
/* SPR common to all 7xx PowerPC implementations */
|
| 721 |
static void gen_spr_7xx (CPUPPCState *env) |
| 722 |
{
|
| 723 |
/* Breakpoints */
|
| 724 |
/* XXX : not implemented */
|
| 725 |
spr_register(env, SPR_DABR, "DABR",
|
| 726 |
SPR_NOACCESS, SPR_NOACCESS, |
| 727 |
&spr_read_generic, &spr_write_generic, |
| 728 |
0x00000000);
|
| 729 |
/* XXX : not implemented */
|
| 730 |
spr_register(env, SPR_IABR, "IABR",
|
| 731 |
SPR_NOACCESS, SPR_NOACCESS, |
| 732 |
&spr_read_generic, &spr_write_generic, |
| 733 |
0x00000000);
|
| 734 |
/* Cache management */
|
| 735 |
/* XXX : not implemented */
|
| 736 |
spr_register(env, SPR_ICTC, "ICTC",
|
| 737 |
SPR_NOACCESS, SPR_NOACCESS, |
| 738 |
&spr_read_generic, &spr_write_generic, |
| 739 |
0x00000000);
|
| 740 |
/* XXX : not implemented */
|
| 741 |
spr_register(env, SPR_L2CR, "L2CR",
|
| 742 |
SPR_NOACCESS, SPR_NOACCESS, |
| 743 |
&spr_read_generic, &spr_write_generic, |
| 744 |
0x00000000);
|
| 745 |
/* Performance monitors */
|
| 746 |
/* XXX : not implemented */
|
| 747 |
spr_register(env, SPR_MMCR0, "MMCR0",
|
| 748 |
SPR_NOACCESS, SPR_NOACCESS, |
| 749 |
&spr_read_generic, &spr_write_generic, |
| 750 |
0x00000000);
|
| 751 |
/* XXX : not implemented */
|
| 752 |
spr_register(env, SPR_MMCR1, "MMCR1",
|
| 753 |
SPR_NOACCESS, SPR_NOACCESS, |
| 754 |
&spr_read_generic, &spr_write_generic, |
| 755 |
0x00000000);
|
| 756 |
/* XXX : not implemented */
|
| 757 |
spr_register(env, SPR_PMC1, "PMC1",
|
| 758 |
SPR_NOACCESS, SPR_NOACCESS, |
| 759 |
&spr_read_generic, &spr_write_generic, |
| 760 |
0x00000000);
|
| 761 |
/* XXX : not implemented */
|
| 762 |
spr_register(env, SPR_PMC2, "PMC2",
|
| 763 |
SPR_NOACCESS, SPR_NOACCESS, |
| 764 |
&spr_read_generic, &spr_write_generic, |
| 765 |
0x00000000);
|
| 766 |
/* XXX : not implemented */
|
| 767 |
spr_register(env, SPR_PMC3, "PMC3",
|
| 768 |
SPR_NOACCESS, SPR_NOACCESS, |
| 769 |
&spr_read_generic, &spr_write_generic, |
| 770 |
0x00000000);
|
| 771 |
/* XXX : not implemented */
|
| 772 |
spr_register(env, SPR_PMC4, "PMC4",
|
| 773 |
SPR_NOACCESS, SPR_NOACCESS, |
| 774 |
&spr_read_generic, &spr_write_generic, |
| 775 |
0x00000000);
|
| 776 |
/* XXX : not implemented */
|
| 777 |
spr_register(env, SPR_SIA, "SIA",
|
| 778 |
SPR_NOACCESS, SPR_NOACCESS, |
| 779 |
&spr_read_generic, SPR_NOACCESS, |
| 780 |
0x00000000);
|
| 781 |
spr_register(env, SPR_UMMCR0, "UMMCR0",
|
| 782 |
&spr_read_ureg, SPR_NOACCESS, |
| 783 |
&spr_read_ureg, SPR_NOACCESS, |
| 784 |
0x00000000);
|
| 785 |
spr_register(env, SPR_UMMCR1, "UMMCR1",
|
| 786 |
&spr_read_ureg, SPR_NOACCESS, |
| 787 |
&spr_read_ureg, SPR_NOACCESS, |
| 788 |
0x00000000);
|
| 789 |
spr_register(env, SPR_UPMC1, "UPMC1",
|
| 790 |
&spr_read_ureg, SPR_NOACCESS, |
| 791 |
&spr_read_ureg, SPR_NOACCESS, |
| 792 |
0x00000000);
|
| 793 |
spr_register(env, SPR_UPMC2, "UPMC2",
|
| 794 |
&spr_read_ureg, SPR_NOACCESS, |
| 795 |
&spr_read_ureg, SPR_NOACCESS, |
| 796 |
0x00000000);
|
| 797 |
spr_register(env, SPR_UPMC3, "UPMC3",
|
| 798 |
&spr_read_ureg, SPR_NOACCESS, |
| 799 |
&spr_read_ureg, SPR_NOACCESS, |
| 800 |
0x00000000);
|
| 801 |
spr_register(env, SPR_UPMC4, "UPMC4",
|
| 802 |
&spr_read_ureg, SPR_NOACCESS, |
| 803 |
&spr_read_ureg, SPR_NOACCESS, |
| 804 |
0x00000000);
|
| 805 |
spr_register(env, SPR_USIA, "USIA",
|
| 806 |
&spr_read_ureg, SPR_NOACCESS, |
| 807 |
&spr_read_ureg, SPR_NOACCESS, |
| 808 |
0x00000000);
|
| 809 |
/* Thermal management */
|
| 810 |
/* XXX : not implemented */
|
| 811 |
spr_register(env, SPR_THRM1, "THRM1",
|
| 812 |
SPR_NOACCESS, SPR_NOACCESS, |
| 813 |
&spr_read_generic, &spr_write_generic, |
| 814 |
0x00000000);
|
| 815 |
/* XXX : not implemented */
|
| 816 |
spr_register(env, SPR_THRM2, "THRM2",
|
| 817 |
SPR_NOACCESS, SPR_NOACCESS, |
| 818 |
&spr_read_generic, &spr_write_generic, |
| 819 |
0x00000000);
|
| 820 |
/* XXX : not implemented */
|
| 821 |
spr_register(env, SPR_THRM3, "THRM3",
|
| 822 |
SPR_NOACCESS, SPR_NOACCESS, |
| 823 |
&spr_read_generic, &spr_write_generic, |
| 824 |
0x00000000);
|
| 825 |
/* External access control */
|
| 826 |
/* XXX : not implemented */
|
| 827 |
spr_register(env, SPR_EAR, "EAR",
|
| 828 |
SPR_NOACCESS, SPR_NOACCESS, |
| 829 |
&spr_read_generic, &spr_write_generic, |
| 830 |
0x00000000);
|
| 831 |
} |
| 832 |
|
| 833 |
/* SPR specific to PowerPC 604 implementation */
|
| 834 |
static void gen_spr_604 (CPUPPCState *env) |
| 835 |
{
|
| 836 |
/* Processor identification */
|
| 837 |
spr_register(env, SPR_PIR, "PIR",
|
| 838 |
SPR_NOACCESS, SPR_NOACCESS, |
| 839 |
&spr_read_generic, &spr_write_pir, |
| 840 |
0x00000000);
|
| 841 |
/* Breakpoints */
|
| 842 |
/* XXX : not implemented */
|
| 843 |
spr_register(env, SPR_IABR, "IABR",
|
| 844 |
SPR_NOACCESS, SPR_NOACCESS, |
| 845 |
&spr_read_generic, &spr_write_generic, |
| 846 |
0x00000000);
|
| 847 |
/* XXX : not implemented */
|
| 848 |
spr_register(env, SPR_DABR, "DABR",
|
| 849 |
SPR_NOACCESS, SPR_NOACCESS, |
| 850 |
&spr_read_generic, &spr_write_generic, |
| 851 |
0x00000000);
|
| 852 |
/* Performance counters */
|
| 853 |
/* XXX : not implemented */
|
| 854 |
spr_register(env, SPR_MMCR0, "MMCR0",
|
| 855 |
SPR_NOACCESS, SPR_NOACCESS, |
| 856 |
&spr_read_generic, &spr_write_generic, |
| 857 |
0x00000000);
|
| 858 |
/* XXX : not implemented */
|
| 859 |
spr_register(env, SPR_MMCR1, "MMCR1",
|
| 860 |
SPR_NOACCESS, SPR_NOACCESS, |
| 861 |
&spr_read_generic, &spr_write_generic, |
| 862 |
0x00000000);
|
| 863 |
/* XXX : not implemented */
|
| 864 |
spr_register(env, SPR_PMC1, "PMC1",
|
| 865 |
SPR_NOACCESS, SPR_NOACCESS, |
| 866 |
&spr_read_generic, &spr_write_generic, |
| 867 |
0x00000000);
|
| 868 |
/* XXX : not implemented */
|
| 869 |
spr_register(env, SPR_PMC2, "PMC2",
|
| 870 |
SPR_NOACCESS, SPR_NOACCESS, |
| 871 |
&spr_read_generic, &spr_write_generic, |
| 872 |
0x00000000);
|
| 873 |
/* XXX : not implemented */
|
| 874 |
spr_register(env, SPR_PMC3, "PMC3",
|
| 875 |
SPR_NOACCESS, SPR_NOACCESS, |
| 876 |
&spr_read_generic, &spr_write_generic, |
| 877 |
0x00000000);
|
| 878 |
/* XXX : not implemented */
|
| 879 |
spr_register(env, SPR_PMC4, "PMC4",
|
| 880 |
SPR_NOACCESS, SPR_NOACCESS, |
| 881 |
&spr_read_generic, &spr_write_generic, |
| 882 |
0x00000000);
|
| 883 |
/* XXX : not implemented */
|
| 884 |
spr_register(env, SPR_SIA, "SIA",
|
| 885 |
SPR_NOACCESS, SPR_NOACCESS, |
| 886 |
&spr_read_generic, SPR_NOACCESS, |
| 887 |
0x00000000);
|
| 888 |
/* XXX : not implemented */
|
| 889 |
spr_register(env, SPR_SDA, "SDA",
|
| 890 |
SPR_NOACCESS, SPR_NOACCESS, |
| 891 |
&spr_read_generic, SPR_NOACCESS, |
| 892 |
0x00000000);
|
| 893 |
/* External access control */
|
| 894 |
/* XXX : not implemented */
|
| 895 |
spr_register(env, SPR_EAR, "EAR",
|
| 896 |
SPR_NOACCESS, SPR_NOACCESS, |
| 897 |
&spr_read_generic, &spr_write_generic, |
| 898 |
0x00000000);
|
| 899 |
} |
| 900 |
|
| 901 |
/* SPR specific to PowerPC 603 implementation */
|
| 902 |
static void gen_spr_603 (CPUPPCState *env) |
| 903 |
{
|
| 904 |
/* External access control */
|
| 905 |
/* XXX : not implemented */
|
| 906 |
spr_register(env, SPR_EAR, "EAR",
|
| 907 |
SPR_NOACCESS, SPR_NOACCESS, |
| 908 |
&spr_read_generic, &spr_write_generic, |
| 909 |
0x00000000);
|
| 910 |
} |
| 911 |
|
| 912 |
/* SPR specific to PowerPC G2 implementation */
|
| 913 |
static void gen_spr_G2 (CPUPPCState *env) |
| 914 |
{
|
| 915 |
/* Memory base address */
|
| 916 |
/* MBAR */
|
| 917 |
spr_register(env, SPR_MBAR, "MBAR",
|
| 918 |
SPR_NOACCESS, SPR_NOACCESS, |
| 919 |
&spr_read_generic, &spr_write_generic, |
| 920 |
0x00000000);
|
| 921 |
/* System version register */
|
| 922 |
/* SVR */
|
| 923 |
spr_register(env, SPR_SVR, "SVR",
|
| 924 |
SPR_NOACCESS, SPR_NOACCESS, |
| 925 |
&spr_read_generic, SPR_NOACCESS, |
| 926 |
0x00000000);
|
| 927 |
/* Exception processing */
|
| 928 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
|
| 929 |
SPR_NOACCESS, SPR_NOACCESS, |
| 930 |
&spr_read_generic, &spr_write_generic, |
| 931 |
0x00000000);
|
| 932 |
spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
|
| 933 |
SPR_NOACCESS, SPR_NOACCESS, |
| 934 |
&spr_read_generic, &spr_write_generic, |
| 935 |
0x00000000);
|
| 936 |
/* Breakpoints */
|
| 937 |
/* XXX : not implemented */
|
| 938 |
spr_register(env, SPR_DABR, "DABR",
|
| 939 |
SPR_NOACCESS, SPR_NOACCESS, |
| 940 |
&spr_read_generic, &spr_write_generic, |
| 941 |
0x00000000);
|
| 942 |
/* XXX : not implemented */
|
| 943 |
spr_register(env, SPR_DABR2, "DABR2",
|
| 944 |
SPR_NOACCESS, SPR_NOACCESS, |
| 945 |
&spr_read_generic, &spr_write_generic, |
| 946 |
0x00000000);
|
| 947 |
/* XXX : not implemented */
|
| 948 |
spr_register(env, SPR_IABR, "IABR",
|
| 949 |
SPR_NOACCESS, SPR_NOACCESS, |
| 950 |
&spr_read_generic, &spr_write_generic, |
| 951 |
0x00000000);
|
| 952 |
/* XXX : not implemented */
|
| 953 |
spr_register(env, SPR_IABR2, "IABR2",
|
| 954 |
SPR_NOACCESS, SPR_NOACCESS, |
| 955 |
&spr_read_generic, &spr_write_generic, |
| 956 |
0x00000000);
|
| 957 |
/* XXX : not implemented */
|
| 958 |
spr_register(env, SPR_IBCR, "IBCR",
|
| 959 |
SPR_NOACCESS, SPR_NOACCESS, |
| 960 |
&spr_read_generic, &spr_write_generic, |
| 961 |
0x00000000);
|
| 962 |
/* XXX : not implemented */
|
| 963 |
spr_register(env, SPR_DBCR, "DBCR",
|
| 964 |
SPR_NOACCESS, SPR_NOACCESS, |
| 965 |
&spr_read_generic, &spr_write_generic, |
| 966 |
0x00000000);
|
| 967 |
} |
| 968 |
|
| 969 |
/* SPR specific to PowerPC 602 implementation */
|
| 970 |
static void gen_spr_602 (CPUPPCState *env) |
| 971 |
{
|
| 972 |
/* ESA registers */
|
| 973 |
/* XXX : not implemented */
|
| 974 |
spr_register(env, SPR_SER, "SER",
|
| 975 |
SPR_NOACCESS, SPR_NOACCESS, |
| 976 |
&spr_read_generic, &spr_write_generic, |
| 977 |
0x00000000);
|
| 978 |
/* XXX : not implemented */
|
| 979 |
spr_register(env, SPR_SEBR, "SEBR",
|
| 980 |
SPR_NOACCESS, SPR_NOACCESS, |
| 981 |
&spr_read_generic, &spr_write_generic, |
| 982 |
0x00000000);
|
| 983 |
/* XXX : not implemented */
|
| 984 |
spr_register(env, SPR_ESASR, "ESASR",
|
| 985 |
SPR_NOACCESS, SPR_NOACCESS, |
| 986 |
&spr_read_generic, &spr_write_generic, |
| 987 |
0x00000000);
|
| 988 |
/* Floating point status */
|
| 989 |
/* XXX : not implemented */
|
| 990 |
spr_register(env, SPR_SP, "SP",
|
| 991 |
SPR_NOACCESS, SPR_NOACCESS, |
| 992 |
&spr_read_generic, &spr_write_generic, |
| 993 |
0x00000000);
|
| 994 |
/* XXX : not implemented */
|
| 995 |
spr_register(env, SPR_LT, "LT",
|
| 996 |
SPR_NOACCESS, SPR_NOACCESS, |
| 997 |
&spr_read_generic, &spr_write_generic, |
| 998 |
0x00000000);
|
| 999 |
/* Watchdog timer */
|
| 1000 |
/* XXX : not implemented */
|
| 1001 |
spr_register(env, SPR_TCR, "TCR",
|
| 1002 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1003 |
&spr_read_generic, &spr_write_generic, |
| 1004 |
0x00000000);
|
| 1005 |
/* Interrupt base */
|
| 1006 |
spr_register(env, SPR_IBR, "IBR",
|
| 1007 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1008 |
&spr_read_generic, &spr_write_generic, |
| 1009 |
0x00000000);
|
| 1010 |
} |
| 1011 |
|
| 1012 |
/* SPR specific to PowerPC 601 implementation */
|
| 1013 |
static void gen_spr_601 (CPUPPCState *env) |
| 1014 |
{
|
| 1015 |
/* Multiplication/division register */
|
| 1016 |
/* MQ */
|
| 1017 |
spr_register(env, SPR_MQ, "MQ",
|
| 1018 |
&spr_read_generic, &spr_write_generic, |
| 1019 |
&spr_read_generic, &spr_write_generic, |
| 1020 |
0x00000000);
|
| 1021 |
/* RTC registers */
|
| 1022 |
spr_register(env, SPR_601_RTCU, "RTCU",
|
| 1023 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1024 |
SPR_NOACCESS, &spr_write_601_rtcu, |
| 1025 |
0x00000000);
|
| 1026 |
spr_register(env, SPR_601_VRTCU, "RTCU",
|
| 1027 |
&spr_read_601_rtcu, SPR_NOACCESS, |
| 1028 |
&spr_read_601_rtcu, SPR_NOACCESS, |
| 1029 |
0x00000000);
|
| 1030 |
spr_register(env, SPR_601_RTCL, "RTCL",
|
| 1031 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1032 |
SPR_NOACCESS, &spr_write_601_rtcl, |
| 1033 |
0x00000000);
|
| 1034 |
spr_register(env, SPR_601_VRTCL, "RTCL",
|
| 1035 |
&spr_read_601_rtcl, SPR_NOACCESS, |
| 1036 |
&spr_read_601_rtcl, SPR_NOACCESS, |
| 1037 |
0x00000000);
|
| 1038 |
/* Timer */
|
| 1039 |
#if 0 /* ? */
|
| 1040 |
spr_register(env, SPR_601_UDECR, "UDECR",
|
| 1041 |
&spr_read_decr, SPR_NOACCESS,
|
| 1042 |
&spr_read_decr, SPR_NOACCESS,
|
| 1043 |
0x00000000);
|
| 1044 |
#endif
|
| 1045 |
/* External access control */
|
| 1046 |
/* XXX : not implemented */
|
| 1047 |
spr_register(env, SPR_EAR, "EAR",
|
| 1048 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1049 |
&spr_read_generic, &spr_write_generic, |
| 1050 |
0x00000000);
|
| 1051 |
/* Memory management */
|
| 1052 |
spr_register(env, SPR_IBAT0U, "IBAT0U",
|
| 1053 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1054 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
| 1055 |
0x00000000);
|
| 1056 |
spr_register(env, SPR_IBAT0L, "IBAT0L",
|
| 1057 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1058 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
| 1059 |
0x00000000);
|
| 1060 |
spr_register(env, SPR_IBAT1U, "IBAT1U",
|
| 1061 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1062 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
| 1063 |
0x00000000);
|
| 1064 |
spr_register(env, SPR_IBAT1L, "IBAT1L",
|
| 1065 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1066 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
| 1067 |
0x00000000);
|
| 1068 |
spr_register(env, SPR_IBAT2U, "IBAT2U",
|
| 1069 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1070 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
| 1071 |
0x00000000);
|
| 1072 |
spr_register(env, SPR_IBAT2L, "IBAT2L",
|
| 1073 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1074 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
| 1075 |
0x00000000);
|
| 1076 |
spr_register(env, SPR_IBAT3U, "IBAT3U",
|
| 1077 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1078 |
&spr_read_601_ubat, &spr_write_601_ubatu, |
| 1079 |
0x00000000);
|
| 1080 |
spr_register(env, SPR_IBAT3L, "IBAT3L",
|
| 1081 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1082 |
&spr_read_601_ubat, &spr_write_601_ubatl, |
| 1083 |
0x00000000);
|
| 1084 |
} |
| 1085 |
|
| 1086 |
/* PowerPC BookE SPR */
|
| 1087 |
static void gen_spr_BookE (CPUPPCState *env) |
| 1088 |
{
|
| 1089 |
/* Processor identification */
|
| 1090 |
spr_register(env, SPR_BOOKE_PIR, "PIR",
|
| 1091 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1092 |
&spr_read_generic, &spr_write_pir, |
| 1093 |
0x00000000);
|
| 1094 |
/* Interrupt processing */
|
| 1095 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
|
| 1096 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1097 |
&spr_read_generic, &spr_write_generic, |
| 1098 |
0x00000000);
|
| 1099 |
spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
|
| 1100 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1101 |
&spr_read_generic, &spr_write_generic, |
| 1102 |
0x00000000);
|
| 1103 |
spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
|
| 1104 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1105 |
&spr_read_generic, &spr_write_generic, |
| 1106 |
0x00000000);
|
| 1107 |
spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
|
| 1108 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1109 |
&spr_read_generic, &spr_write_generic, |
| 1110 |
0x00000000);
|
| 1111 |
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
|
| 1112 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1113 |
&spr_read_generic, &spr_write_generic, |
| 1114 |
0x00000000);
|
| 1115 |
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
|
| 1116 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1117 |
&spr_read_generic, &spr_write_generic, |
| 1118 |
0x00000000);
|
| 1119 |
/* Debug */
|
| 1120 |
/* XXX : not implemented */
|
| 1121 |
spr_register(env, SPR_BOOKE_IAC1, "IAC1",
|
| 1122 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1123 |
&spr_read_generic, &spr_write_generic, |
| 1124 |
0x00000000);
|
| 1125 |
/* XXX : not implemented */
|
| 1126 |
spr_register(env, SPR_BOOKE_IAC2, "IAC2",
|
| 1127 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1128 |
&spr_read_generic, &spr_write_generic, |
| 1129 |
0x00000000);
|
| 1130 |
/* XXX : not implemented */
|
| 1131 |
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
|
| 1132 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1133 |
&spr_read_generic, &spr_write_generic, |
| 1134 |
0x00000000);
|
| 1135 |
/* XXX : not implemented */
|
| 1136 |
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
|
| 1137 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1138 |
&spr_read_generic, &spr_write_generic, |
| 1139 |
0x00000000);
|
| 1140 |
/* XXX : not implemented */
|
| 1141 |
spr_register(env, SPR_BOOKE_DAC1, "DAC1",
|
| 1142 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1143 |
&spr_read_generic, &spr_write_generic, |
| 1144 |
0x00000000);
|
| 1145 |
/* XXX : not implemented */
|
| 1146 |
spr_register(env, SPR_BOOKE_DAC2, "DAC2",
|
| 1147 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1148 |
&spr_read_generic, &spr_write_generic, |
| 1149 |
0x00000000);
|
| 1150 |
/* XXX : not implemented */
|
| 1151 |
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
|
| 1152 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1153 |
&spr_read_generic, &spr_write_generic, |
| 1154 |
0x00000000);
|
| 1155 |
/* XXX : not implemented */
|
| 1156 |
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
|
| 1157 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1158 |
&spr_read_generic, &spr_write_generic, |
| 1159 |
0x00000000);
|
| 1160 |
/* XXX : not implemented */
|
| 1161 |
spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
|
| 1162 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1163 |
&spr_read_generic, &spr_write_generic, |
| 1164 |
0x00000000);
|
| 1165 |
/* XXX : not implemented */
|
| 1166 |
spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
|
| 1167 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1168 |
&spr_read_generic, &spr_write_generic, |
| 1169 |
0x00000000);
|
| 1170 |
/* XXX : not implemented */
|
| 1171 |
spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
|
| 1172 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1173 |
&spr_read_generic, &spr_write_generic, |
| 1174 |
0x00000000);
|
| 1175 |
/* XXX : not implemented */
|
| 1176 |
spr_register(env, SPR_BOOKE_DBSR, "DBSR",
|
| 1177 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1178 |
&spr_read_generic, &spr_write_generic, |
| 1179 |
0x00000000);
|
| 1180 |
spr_register(env, SPR_BOOKE_DEAR, "DEAR",
|
| 1181 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1182 |
&spr_read_generic, &spr_write_generic, |
| 1183 |
0x00000000);
|
| 1184 |
spr_register(env, SPR_BOOKE_ESR, "ESR",
|
| 1185 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1186 |
&spr_read_generic, &spr_write_generic, |
| 1187 |
0x00000000);
|
| 1188 |
spr_register(env, SPR_BOOKE_IVPR, "IVPR",
|
| 1189 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1190 |
&spr_read_generic, &spr_write_generic, |
| 1191 |
0x00000000);
|
| 1192 |
/* Exception vectors */
|
| 1193 |
spr_register(env, SPR_BOOKE_IVPR, "IVPR",
|
| 1194 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1195 |
&spr_read_generic, &spr_write_generic, |
| 1196 |
0x00000000);
|
| 1197 |
spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
|
| 1198 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1199 |
&spr_read_generic, &spr_write_generic, |
| 1200 |
0x00000000);
|
| 1201 |
spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
|
| 1202 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1203 |
&spr_read_generic, &spr_write_generic, |
| 1204 |
0x00000000);
|
| 1205 |
spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
|
| 1206 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1207 |
&spr_read_generic, &spr_write_generic, |
| 1208 |
0x00000000);
|
| 1209 |
spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
|
| 1210 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1211 |
&spr_read_generic, &spr_write_generic, |
| 1212 |
0x00000000);
|
| 1213 |
spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
|
| 1214 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1215 |
&spr_read_generic, &spr_write_generic, |
| 1216 |
0x00000000);
|
| 1217 |
spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
|
| 1218 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1219 |
&spr_read_generic, &spr_write_generic, |
| 1220 |
0x00000000);
|
| 1221 |
spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
|
| 1222 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1223 |
&spr_read_generic, &spr_write_generic, |
| 1224 |
0x00000000);
|
| 1225 |
spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
|
| 1226 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1227 |
&spr_read_generic, &spr_write_generic, |
| 1228 |
0x00000000);
|
| 1229 |
spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
|
| 1230 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1231 |
&spr_read_generic, &spr_write_generic, |
| 1232 |
0x00000000);
|
| 1233 |
spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
|
| 1234 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1235 |
&spr_read_generic, &spr_write_generic, |
| 1236 |
0x00000000);
|
| 1237 |
spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
|
| 1238 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1239 |
&spr_read_generic, &spr_write_generic, |
| 1240 |
0x00000000);
|
| 1241 |
spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
|
| 1242 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1243 |
&spr_read_generic, &spr_write_generic, |
| 1244 |
0x00000000);
|
| 1245 |
spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
|
| 1246 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1247 |
&spr_read_generic, &spr_write_generic, |
| 1248 |
0x00000000);
|
| 1249 |
spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
|
| 1250 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1251 |
&spr_read_generic, &spr_write_generic, |
| 1252 |
0x00000000);
|
| 1253 |
spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
|
| 1254 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1255 |
&spr_read_generic, &spr_write_generic, |
| 1256 |
0x00000000);
|
| 1257 |
spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
|
| 1258 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1259 |
&spr_read_generic, &spr_write_generic, |
| 1260 |
0x00000000);
|
| 1261 |
spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
|
| 1262 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1263 |
&spr_read_generic, &spr_write_generic, |
| 1264 |
0x00000000);
|
| 1265 |
spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
|
| 1266 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1267 |
&spr_read_generic, &spr_write_generic, |
| 1268 |
0x00000000);
|
| 1269 |
spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
|
| 1270 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1271 |
&spr_read_generic, &spr_write_generic, |
| 1272 |
0x00000000);
|
| 1273 |
spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
|
| 1274 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1275 |
&spr_read_generic, &spr_write_generic, |
| 1276 |
0x00000000);
|
| 1277 |
spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
|
| 1278 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1279 |
&spr_read_generic, &spr_write_generic, |
| 1280 |
0x00000000);
|
| 1281 |
spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
|
| 1282 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1283 |
&spr_read_generic, &spr_write_generic, |
| 1284 |
0x00000000);
|
| 1285 |
spr_register(env, SPR_BOOKE_PID, "PID",
|
| 1286 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1287 |
&spr_read_generic, &spr_write_generic, |
| 1288 |
0x00000000);
|
| 1289 |
spr_register(env, SPR_BOOKE_TCR, "TCR",
|
| 1290 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1291 |
&spr_read_generic, &spr_write_booke_tcr, |
| 1292 |
0x00000000);
|
| 1293 |
spr_register(env, SPR_BOOKE_TSR, "TSR",
|
| 1294 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1295 |
&spr_read_generic, &spr_write_booke_tsr, |
| 1296 |
0x00000000);
|
| 1297 |
/* Timer */
|
| 1298 |
spr_register(env, SPR_DECR, "DECR",
|
| 1299 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1300 |
&spr_read_decr, &spr_write_decr, |
| 1301 |
0x00000000);
|
| 1302 |
spr_register(env, SPR_BOOKE_DECAR, "DECAR",
|
| 1303 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1304 |
SPR_NOACCESS, &spr_write_generic, |
| 1305 |
0x00000000);
|
| 1306 |
/* SPRGs */
|
| 1307 |
spr_register(env, SPR_USPRG0, "USPRG0",
|
| 1308 |
&spr_read_generic, &spr_write_generic, |
| 1309 |
&spr_read_generic, &spr_write_generic, |
| 1310 |
0x00000000);
|
| 1311 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
| 1312 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1313 |
&spr_read_generic, &spr_write_generic, |
| 1314 |
0x00000000);
|
| 1315 |
spr_register(env, SPR_USPRG4, "USPRG4",
|
| 1316 |
&spr_read_ureg, SPR_NOACCESS, |
| 1317 |
&spr_read_ureg, SPR_NOACCESS, |
| 1318 |
0x00000000);
|
| 1319 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
| 1320 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1321 |
&spr_read_generic, &spr_write_generic, |
| 1322 |
0x00000000);
|
| 1323 |
spr_register(env, SPR_USPRG5, "USPRG5",
|
| 1324 |
&spr_read_ureg, SPR_NOACCESS, |
| 1325 |
&spr_read_ureg, SPR_NOACCESS, |
| 1326 |
0x00000000);
|
| 1327 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
| 1328 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1329 |
&spr_read_generic, &spr_write_generic, |
| 1330 |
0x00000000);
|
| 1331 |
spr_register(env, SPR_USPRG6, "USPRG6",
|
| 1332 |
&spr_read_ureg, SPR_NOACCESS, |
| 1333 |
&spr_read_ureg, SPR_NOACCESS, |
| 1334 |
0x00000000);
|
| 1335 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
| 1336 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1337 |
&spr_read_generic, &spr_write_generic, |
| 1338 |
0x00000000);
|
| 1339 |
spr_register(env, SPR_USPRG7, "USPRG7",
|
| 1340 |
&spr_read_ureg, SPR_NOACCESS, |
| 1341 |
&spr_read_ureg, SPR_NOACCESS, |
| 1342 |
0x00000000);
|
| 1343 |
} |
| 1344 |
|
| 1345 |
/* FSL storage control registers */
|
| 1346 |
static void gen_spr_BookE_FSL (CPUPPCState *env) |
| 1347 |
{
|
| 1348 |
/* TLB assist registers */
|
| 1349 |
spr_register(env, SPR_BOOKE_MAS0, "MAS0",
|
| 1350 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1351 |
&spr_read_generic, &spr_write_generic, |
| 1352 |
0x00000000);
|
| 1353 |
spr_register(env, SPR_BOOKE_MAS1, "MAS2",
|
| 1354 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1355 |
&spr_read_generic, &spr_write_generic, |
| 1356 |
0x00000000);
|
| 1357 |
spr_register(env, SPR_BOOKE_MAS2, "MAS3",
|
| 1358 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1359 |
&spr_read_generic, &spr_write_generic, |
| 1360 |
0x00000000);
|
| 1361 |
spr_register(env, SPR_BOOKE_MAS3, "MAS4",
|
| 1362 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1363 |
&spr_read_generic, &spr_write_generic, |
| 1364 |
0x00000000);
|
| 1365 |
spr_register(env, SPR_BOOKE_MAS4, "MAS5",
|
| 1366 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1367 |
&spr_read_generic, &spr_write_generic, |
| 1368 |
0x00000000);
|
| 1369 |
spr_register(env, SPR_BOOKE_MAS6, "MAS6",
|
| 1370 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1371 |
&spr_read_generic, &spr_write_generic, |
| 1372 |
0x00000000);
|
| 1373 |
spr_register(env, SPR_BOOKE_MAS7, "MAS7",
|
| 1374 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1375 |
&spr_read_generic, &spr_write_generic, |
| 1376 |
0x00000000);
|
| 1377 |
if (env->nb_pids > 1) { |
| 1378 |
spr_register(env, SPR_BOOKE_PID1, "PID1",
|
| 1379 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1380 |
&spr_read_generic, &spr_write_generic, |
| 1381 |
0x00000000);
|
| 1382 |
} |
| 1383 |
if (env->nb_pids > 2) { |
| 1384 |
spr_register(env, SPR_BOOKE_PID2, "PID2",
|
| 1385 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1386 |
&spr_read_generic, &spr_write_generic, |
| 1387 |
0x00000000);
|
| 1388 |
} |
| 1389 |
spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
|
| 1390 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1391 |
&spr_read_generic, SPR_NOACCESS, |
| 1392 |
0x00000000); /* TOFIX */ |
| 1393 |
spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
|
| 1394 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1395 |
&spr_read_generic, &spr_write_generic, |
| 1396 |
0x00000000); /* TOFIX */ |
| 1397 |
switch (env->nb_ways) {
|
| 1398 |
case 4: |
| 1399 |
spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
|
| 1400 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1401 |
&spr_read_generic, SPR_NOACCESS, |
| 1402 |
0x00000000); /* TOFIX */ |
| 1403 |
/* Fallthru */
|
| 1404 |
case 3: |
| 1405 |
spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
|
| 1406 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1407 |
&spr_read_generic, SPR_NOACCESS, |
| 1408 |
0x00000000); /* TOFIX */ |
| 1409 |
/* Fallthru */
|
| 1410 |
case 2: |
| 1411 |
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
|
| 1412 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1413 |
&spr_read_generic, SPR_NOACCESS, |
| 1414 |
0x00000000); /* TOFIX */ |
| 1415 |
/* Fallthru */
|
| 1416 |
case 1: |
| 1417 |
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
|
| 1418 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1419 |
&spr_read_generic, SPR_NOACCESS, |
| 1420 |
0x00000000); /* TOFIX */ |
| 1421 |
/* Fallthru */
|
| 1422 |
case 0: |
| 1423 |
default:
|
| 1424 |
break;
|
| 1425 |
} |
| 1426 |
} |
| 1427 |
|
| 1428 |
/* SPR specific to PowerPC 440 implementation */
|
| 1429 |
static void gen_spr_440 (CPUPPCState *env) |
| 1430 |
{
|
| 1431 |
/* Cache control */
|
| 1432 |
/* XXX : not implemented */
|
| 1433 |
spr_register(env, SPR_440_DNV0, "DNV0",
|
| 1434 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1435 |
&spr_read_generic, &spr_write_generic, |
| 1436 |
0x00000000);
|
| 1437 |
/* XXX : not implemented */
|
| 1438 |
spr_register(env, SPR_440_DNV1, "DNV1",
|
| 1439 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1440 |
&spr_read_generic, &spr_write_generic, |
| 1441 |
0x00000000);
|
| 1442 |
/* XXX : not implemented */
|
| 1443 |
spr_register(env, SPR_440_DNV2, "DNV2",
|
| 1444 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1445 |
&spr_read_generic, &spr_write_generic, |
| 1446 |
0x00000000);
|
| 1447 |
/* XXX : not implemented */
|
| 1448 |
spr_register(env, SPR_440_DNV3, "DNV3",
|
| 1449 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1450 |
&spr_read_generic, &spr_write_generic, |
| 1451 |
0x00000000);
|
| 1452 |
/* XXX : not implemented */
|
| 1453 |
spr_register(env, SPR_440_DVT0, "DVT0",
|
| 1454 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1455 |
&spr_read_generic, &spr_write_generic, |
| 1456 |
0x00000000);
|
| 1457 |
/* XXX : not implemented */
|
| 1458 |
spr_register(env, SPR_440_DVT1, "DVT1",
|
| 1459 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1460 |
&spr_read_generic, &spr_write_generic, |
| 1461 |
0x00000000);
|
| 1462 |
/* XXX : not implemented */
|
| 1463 |
spr_register(env, SPR_440_DVT2, "DVT2",
|
| 1464 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1465 |
&spr_read_generic, &spr_write_generic, |
| 1466 |
0x00000000);
|
| 1467 |
/* XXX : not implemented */
|
| 1468 |
spr_register(env, SPR_440_DVT3, "DVT3",
|
| 1469 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1470 |
&spr_read_generic, &spr_write_generic, |
| 1471 |
0x00000000);
|
| 1472 |
/* XXX : not implemented */
|
| 1473 |
spr_register(env, SPR_440_DVLIM, "DVLIM",
|
| 1474 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1475 |
&spr_read_generic, &spr_write_generic, |
| 1476 |
0x00000000);
|
| 1477 |
/* XXX : not implemented */
|
| 1478 |
spr_register(env, SPR_440_INV0, "INV0",
|
| 1479 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1480 |
&spr_read_generic, &spr_write_generic, |
| 1481 |
0x00000000);
|
| 1482 |
/* XXX : not implemented */
|
| 1483 |
spr_register(env, SPR_440_INV1, "INV1",
|
| 1484 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1485 |
&spr_read_generic, &spr_write_generic, |
| 1486 |
0x00000000);
|
| 1487 |
/* XXX : not implemented */
|
| 1488 |
spr_register(env, SPR_440_INV2, "INV2",
|
| 1489 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1490 |
&spr_read_generic, &spr_write_generic, |
| 1491 |
0x00000000);
|
| 1492 |
/* XXX : not implemented */
|
| 1493 |
spr_register(env, SPR_440_INV3, "INV3",
|
| 1494 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1495 |
&spr_read_generic, &spr_write_generic, |
| 1496 |
0x00000000);
|
| 1497 |
/* XXX : not implemented */
|
| 1498 |
spr_register(env, SPR_440_IVT0, "IVT0",
|
| 1499 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1500 |
&spr_read_generic, &spr_write_generic, |
| 1501 |
0x00000000);
|
| 1502 |
/* XXX : not implemented */
|
| 1503 |
spr_register(env, SPR_440_IVT1, "IVT1",
|
| 1504 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1505 |
&spr_read_generic, &spr_write_generic, |
| 1506 |
0x00000000);
|
| 1507 |
/* XXX : not implemented */
|
| 1508 |
spr_register(env, SPR_440_IVT2, "IVT2",
|
| 1509 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1510 |
&spr_read_generic, &spr_write_generic, |
| 1511 |
0x00000000);
|
| 1512 |
/* XXX : not implemented */
|
| 1513 |
spr_register(env, SPR_440_IVT3, "IVT3",
|
| 1514 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1515 |
&spr_read_generic, &spr_write_generic, |
| 1516 |
0x00000000);
|
| 1517 |
/* XXX : not implemented */
|
| 1518 |
spr_register(env, SPR_440_IVLIM, "IVLIM",
|
| 1519 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1520 |
&spr_read_generic, &spr_write_generic, |
| 1521 |
0x00000000);
|
| 1522 |
/* Cache debug */
|
| 1523 |
/* XXX : not implemented */
|
| 1524 |
spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH",
|
| 1525 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1526 |
&spr_read_generic, SPR_NOACCESS, |
| 1527 |
0x00000000);
|
| 1528 |
/* XXX : not implemented */
|
| 1529 |
spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL",
|
| 1530 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1531 |
&spr_read_generic, SPR_NOACCESS, |
| 1532 |
0x00000000);
|
| 1533 |
/* XXX : not implemented */
|
| 1534 |
spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
|
| 1535 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1536 |
&spr_read_generic, SPR_NOACCESS, |
| 1537 |
0x00000000);
|
| 1538 |
/* XXX : not implemented */
|
| 1539 |
spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH",
|
| 1540 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1541 |
&spr_read_generic, SPR_NOACCESS, |
| 1542 |
0x00000000);
|
| 1543 |
/* XXX : not implemented */
|
| 1544 |
spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL",
|
| 1545 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1546 |
&spr_read_generic, SPR_NOACCESS, |
| 1547 |
0x00000000);
|
| 1548 |
/* XXX : not implemented */
|
| 1549 |
spr_register(env, SPR_440_DBDR, "DBDR",
|
| 1550 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1551 |
&spr_read_generic, &spr_write_generic, |
| 1552 |
0x00000000);
|
| 1553 |
/* Processor control */
|
| 1554 |
spr_register(env, SPR_4xx_CCR0, "CCR0",
|
| 1555 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1556 |
&spr_read_generic, &spr_write_generic, |
| 1557 |
0x00000000);
|
| 1558 |
spr_register(env, SPR_440_RSTCFG, "RSTCFG",
|
| 1559 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1560 |
&spr_read_generic, SPR_NOACCESS, |
| 1561 |
0x00000000);
|
| 1562 |
/* Storage control */
|
| 1563 |
spr_register(env, SPR_440_MMUCR, "MMUCR",
|
| 1564 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1565 |
&spr_read_generic, &spr_write_generic, |
| 1566 |
0x00000000);
|
| 1567 |
} |
| 1568 |
|
| 1569 |
/* SPR shared between PowerPC 40x implementations */
|
| 1570 |
static void gen_spr_40x (CPUPPCState *env) |
| 1571 |
{
|
| 1572 |
/* Cache */
|
| 1573 |
/* XXX : not implemented */
|
| 1574 |
spr_register(env, SPR_40x_DCCR, "DCCR",
|
| 1575 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1576 |
&spr_read_generic, &spr_write_generic, |
| 1577 |
0x00000000);
|
| 1578 |
/* XXX : not implemented */
|
| 1579 |
spr_register(env, SPR_40x_DCWR, "DCWR",
|
| 1580 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1581 |
&spr_read_generic, &spr_write_generic, |
| 1582 |
0x00000000);
|
| 1583 |
/* XXX : not implemented */
|
| 1584 |
spr_register(env, SPR_40x_ICCR, "ICCR",
|
| 1585 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1586 |
&spr_read_generic, &spr_write_generic, |
| 1587 |
0x00000000);
|
| 1588 |
/* XXX : not implemented */
|
| 1589 |
spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
|
| 1590 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1591 |
&spr_read_generic, SPR_NOACCESS, |
| 1592 |
0x00000000);
|
| 1593 |
/* Bus access control */
|
| 1594 |
spr_register(env, SPR_40x_SGR, "SGR",
|
| 1595 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1596 |
&spr_read_generic, &spr_write_generic, |
| 1597 |
0xFFFFFFFF);
|
| 1598 |
spr_register(env, SPR_40x_ZPR, "ZPR",
|
| 1599 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1600 |
&spr_read_generic, &spr_write_generic, |
| 1601 |
0x00000000);
|
| 1602 |
/* MMU */
|
| 1603 |
spr_register(env, SPR_40x_PID, "PID",
|
| 1604 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1605 |
&spr_read_generic, &spr_write_generic, |
| 1606 |
0x00000000);
|
| 1607 |
/* Exception */
|
| 1608 |
spr_register(env, SPR_40x_DEAR, "DEAR",
|
| 1609 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1610 |
&spr_read_generic, &spr_write_generic, |
| 1611 |
0x00000000);
|
| 1612 |
spr_register(env, SPR_40x_ESR, "ESR",
|
| 1613 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1614 |
&spr_read_generic, &spr_write_generic, |
| 1615 |
0x00000000);
|
| 1616 |
spr_register(env, SPR_40x_EVPR, "EVPR",
|
| 1617 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1618 |
&spr_read_generic, &spr_write_generic, |
| 1619 |
0x00000000);
|
| 1620 |
spr_register(env, SPR_40x_SRR2, "SRR2",
|
| 1621 |
&spr_read_generic, &spr_write_generic, |
| 1622 |
&spr_read_generic, &spr_write_generic, |
| 1623 |
0x00000000);
|
| 1624 |
spr_register(env, SPR_40x_SRR3, "SRR3",
|
| 1625 |
&spr_read_generic, &spr_write_generic, |
| 1626 |
&spr_read_generic, &spr_write_generic, |
| 1627 |
0x00000000);
|
| 1628 |
/* Timers */
|
| 1629 |
spr_register(env, SPR_40x_PIT, "PIT",
|
| 1630 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1631 |
&spr_read_40x_pit, &spr_write_40x_pit, |
| 1632 |
0x00000000);
|
| 1633 |
spr_register(env, SPR_40x_TCR, "TCR",
|
| 1634 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1635 |
&spr_read_generic, &spr_write_booke_tcr, |
| 1636 |
0x00000000);
|
| 1637 |
spr_register(env, SPR_40x_TSR, "TSR",
|
| 1638 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1639 |
&spr_read_generic, &spr_write_booke_tsr, |
| 1640 |
0x00000000);
|
| 1641 |
/* Debug interface */
|
| 1642 |
/* XXX : not implemented */
|
| 1643 |
spr_register(env, SPR_40x_DAC1, "DAC1",
|
| 1644 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1645 |
&spr_read_generic, &spr_write_generic, |
| 1646 |
0x00000000);
|
| 1647 |
spr_register(env, SPR_40x_DAC2, "DAC2",
|
| 1648 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1649 |
&spr_read_generic, &spr_write_generic, |
| 1650 |
0x00000000);
|
| 1651 |
/* XXX : not implemented */
|
| 1652 |
spr_register(env, SPR_40x_DBCR0, "DBCR0",
|
| 1653 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1654 |
&spr_read_generic, &spr_write_generic, |
| 1655 |
0x00000000);
|
| 1656 |
/* XXX : not implemented */
|
| 1657 |
spr_register(env, SPR_40x_DBSR, "DBSR",
|
| 1658 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1659 |
&spr_read_generic, &spr_write_generic, |
| 1660 |
/* Last reset was system reset (system boot */
|
| 1661 |
0x00000300);
|
| 1662 |
/* XXX : not implemented */
|
| 1663 |
spr_register(env, SPR_40x_IAC1, "IAC1",
|
| 1664 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1665 |
&spr_read_generic, &spr_write_generic, |
| 1666 |
0x00000000);
|
| 1667 |
spr_register(env, SPR_40x_IAC2, "IAC2",
|
| 1668 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1669 |
&spr_read_generic, &spr_write_generic, |
| 1670 |
0x00000000);
|
| 1671 |
} |
| 1672 |
|
| 1673 |
/* SPR specific to PowerPC 405 implementation */
|
| 1674 |
static void gen_spr_405 (CPUPPCState *env) |
| 1675 |
{
|
| 1676 |
spr_register(env, SPR_4xx_CCR0, "CCR0",
|
| 1677 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1678 |
&spr_read_generic, &spr_write_generic, |
| 1679 |
0x00700000);
|
| 1680 |
/* Debug */
|
| 1681 |
/* XXX : not implemented */
|
| 1682 |
spr_register(env, SPR_405_DBCR1, "DBCR1",
|
| 1683 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1684 |
&spr_read_generic, &spr_write_generic, |
| 1685 |
0x00000000);
|
| 1686 |
/* XXX : not implemented */
|
| 1687 |
spr_register(env, SPR_405_DVC1, "DVC1",
|
| 1688 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1689 |
&spr_read_generic, &spr_write_generic, |
| 1690 |
0x00000000);
|
| 1691 |
/* XXX : not implemented */
|
| 1692 |
spr_register(env, SPR_405_DVC2, "DVC2",
|
| 1693 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1694 |
&spr_read_generic, &spr_write_generic, |
| 1695 |
0x00000000);
|
| 1696 |
/* XXX : not implemented */
|
| 1697 |
spr_register(env, SPR_405_IAC3, "IAC3",
|
| 1698 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1699 |
&spr_read_generic, &spr_write_generic, |
| 1700 |
0x00000000);
|
| 1701 |
/* XXX : not implemented */
|
| 1702 |
spr_register(env, SPR_405_IAC4, "IAC4",
|
| 1703 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1704 |
&spr_read_generic, &spr_write_generic, |
| 1705 |
0x00000000);
|
| 1706 |
/* Storage control */
|
| 1707 |
/* XXX : not implemented */
|
| 1708 |
spr_register(env, SPR_405_SLER, "SLER",
|
| 1709 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1710 |
&spr_read_generic, &spr_write_generic, |
| 1711 |
0x00000000);
|
| 1712 |
/* XXX : not implemented */
|
| 1713 |
spr_register(env, SPR_405_SU0R, "SU0R",
|
| 1714 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1715 |
&spr_read_generic, &spr_write_generic, |
| 1716 |
0x00000000);
|
| 1717 |
/* SPRG */
|
| 1718 |
spr_register(env, SPR_USPRG0, "USPRG0",
|
| 1719 |
&spr_read_ureg, SPR_NOACCESS, |
| 1720 |
&spr_read_ureg, SPR_NOACCESS, |
| 1721 |
0x00000000);
|
| 1722 |
spr_register(env, SPR_SPRG4, "SPRG4",
|
| 1723 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1724 |
SPR_NOACCESS, &spr_write_generic, |
| 1725 |
0x00000000);
|
| 1726 |
spr_register(env, SPR_USPRG4, "USPRG4",
|
| 1727 |
&spr_read_ureg, SPR_NOACCESS, |
| 1728 |
&spr_read_ureg, SPR_NOACCESS, |
| 1729 |
0x00000000);
|
| 1730 |
spr_register(env, SPR_SPRG5, "SPRG5",
|
| 1731 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1732 |
SPR_NOACCESS, &spr_write_generic, |
| 1733 |
0x00000000);
|
| 1734 |
spr_register(env, SPR_USPRG5, "USPRG5",
|
| 1735 |
&spr_read_ureg, SPR_NOACCESS, |
| 1736 |
&spr_read_ureg, SPR_NOACCESS, |
| 1737 |
0x00000000);
|
| 1738 |
spr_register(env, SPR_SPRG6, "SPRG6",
|
| 1739 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1740 |
SPR_NOACCESS, &spr_write_generic, |
| 1741 |
0x00000000);
|
| 1742 |
spr_register(env, SPR_USPRG6, "USPRG6",
|
| 1743 |
&spr_read_ureg, SPR_NOACCESS, |
| 1744 |
&spr_read_ureg, SPR_NOACCESS, |
| 1745 |
0x00000000);
|
| 1746 |
spr_register(env, SPR_SPRG7, "SPRG7",
|
| 1747 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1748 |
SPR_NOACCESS, &spr_write_generic, |
| 1749 |
0x00000000);
|
| 1750 |
spr_register(env, SPR_USPRG7, "USPRG7",
|
| 1751 |
&spr_read_ureg, SPR_NOACCESS, |
| 1752 |
&spr_read_ureg, SPR_NOACCESS, |
| 1753 |
0x00000000);
|
| 1754 |
/* Debug */
|
| 1755 |
/* XXX : not implemented */
|
| 1756 |
spr_register(env, SPR_40x_DAC2, "DAC2",
|
| 1757 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1758 |
&spr_read_generic, &spr_write_generic, |
| 1759 |
0x00000000);
|
| 1760 |
/* XXX : not implemented */
|
| 1761 |
spr_register(env, SPR_40x_IAC2, "IAC2",
|
| 1762 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1763 |
&spr_read_generic, &spr_write_generic, |
| 1764 |
0x00000000);
|
| 1765 |
} |
| 1766 |
|
| 1767 |
/* SPR shared between PowerPC 401 & 403 implementations */
|
| 1768 |
static void gen_spr_401_403 (CPUPPCState *env) |
| 1769 |
{
|
| 1770 |
/* Time base */
|
| 1771 |
spr_register(env, SPR_403_VTBL, "TBL",
|
| 1772 |
&spr_read_tbl, SPR_NOACCESS, |
| 1773 |
&spr_read_tbl, SPR_NOACCESS, |
| 1774 |
0x00000000);
|
| 1775 |
spr_register(env, SPR_403_TBL, "TBL",
|
| 1776 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1777 |
SPR_NOACCESS, &spr_write_tbl, |
| 1778 |
0x00000000);
|
| 1779 |
spr_register(env, SPR_403_VTBU, "TBU",
|
| 1780 |
&spr_read_tbu, SPR_NOACCESS, |
| 1781 |
&spr_read_tbu, SPR_NOACCESS, |
| 1782 |
0x00000000);
|
| 1783 |
spr_register(env, SPR_403_TBU, "TBU",
|
| 1784 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1785 |
SPR_NOACCESS, &spr_write_tbu, |
| 1786 |
0x00000000);
|
| 1787 |
/* Debug */
|
| 1788 |
/* XXX: not implemented */
|
| 1789 |
spr_register(env, SPR_403_CDBCR, "CDBCR",
|
| 1790 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1791 |
&spr_read_generic, &spr_write_generic, |
| 1792 |
0x00000000);
|
| 1793 |
} |
| 1794 |
|
| 1795 |
/* SPR specific to PowerPC 403 implementation */
|
| 1796 |
static void gen_spr_403 (CPUPPCState *env) |
| 1797 |
{
|
| 1798 |
/* MMU */
|
| 1799 |
spr_register(env, SPR_403_PBL1, "PBL1",
|
| 1800 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1801 |
&spr_read_403_pbr, &spr_write_403_pbr, |
| 1802 |
0x00000000);
|
| 1803 |
spr_register(env, SPR_403_PBU1, "PBU1",
|
| 1804 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1805 |
&spr_read_403_pbr, &spr_write_403_pbr, |
| 1806 |
0x00000000);
|
| 1807 |
spr_register(env, SPR_403_PBL2, "PBL2",
|
| 1808 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1809 |
&spr_read_403_pbr, &spr_write_403_pbr, |
| 1810 |
0x00000000);
|
| 1811 |
spr_register(env, SPR_403_PBU2, "PBU2",
|
| 1812 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1813 |
&spr_read_403_pbr, &spr_write_403_pbr, |
| 1814 |
0x00000000);
|
| 1815 |
/* Debug */
|
| 1816 |
/* XXX : not implemented */
|
| 1817 |
spr_register(env, SPR_40x_DAC2, "DAC2",
|
| 1818 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1819 |
&spr_read_generic, &spr_write_generic, |
| 1820 |
0x00000000);
|
| 1821 |
/* XXX : not implemented */
|
| 1822 |
spr_register(env, SPR_40x_IAC2, "IAC2",
|
| 1823 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1824 |
&spr_read_generic, &spr_write_generic, |
| 1825 |
0x00000000);
|
| 1826 |
} |
| 1827 |
|
| 1828 |
/* SPR specific to PowerPC compression coprocessor extension */
|
| 1829 |
#if defined (TODO)
|
| 1830 |
static void gen_spr_compress (CPUPPCState *env) |
| 1831 |
{
|
| 1832 |
spr_register(env, SPR_401_SKR, "SKR",
|
| 1833 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1834 |
&spr_read_generic, &spr_write_generic, |
| 1835 |
0x00000000);
|
| 1836 |
} |
| 1837 |
#endif
|
| 1838 |
|
| 1839 |
// XXX: TODO (64 bits PowerPC SPRs)
|
| 1840 |
/*
|
| 1841 |
* ASR => SPR 280 (64 bits)
|
| 1842 |
* FPECR => SPR 1022 (?)
|
| 1843 |
* VRSAVE => SPR 256 (Altivec)
|
| 1844 |
* SCOMC => SPR 276 (64 bits ?)
|
| 1845 |
* SCOMD => SPR 277 (64 bits ?)
|
| 1846 |
* HSPRG0 => SPR 304 (hypervisor)
|
| 1847 |
* HSPRG1 => SPR 305 (hypervisor)
|
| 1848 |
* HDEC => SPR 310 (hypervisor)
|
| 1849 |
* HIOR => SPR 311 (hypervisor)
|
| 1850 |
* RMOR => SPR 312 (970)
|
| 1851 |
* HRMOR => SPR 313 (hypervisor)
|
| 1852 |
* HSRR0 => SPR 314 (hypervisor)
|
| 1853 |
* HSRR1 => SPR 315 (hypervisor)
|
| 1854 |
* LPCR => SPR 316 (970)
|
| 1855 |
* LPIDR => SPR 317 (970)
|
| 1856 |
* ... and more (thermal management, performance counters, ...)
|
| 1857 |
*/
|
| 1858 |
|
| 1859 |
static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def) |
| 1860 |
{
|
| 1861 |
env->reserve = -1;
|
| 1862 |
/* Default MMU definitions */
|
| 1863 |
env->nb_BATs = -1;
|
| 1864 |
env->nb_tlb = 0;
|
| 1865 |
env->nb_ways = 0;
|
| 1866 |
/* XXX: missing:
|
| 1867 |
* 32 bits PowerPC:
|
| 1868 |
* - MPC5xx(x)
|
| 1869 |
* - MPC8xx(x)
|
| 1870 |
* - RCPU (same as MPC5xx ?)
|
| 1871 |
*/
|
| 1872 |
spr_register(env, SPR_PVR, "PVR",
|
| 1873 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1874 |
&spr_read_generic, SPR_NOACCESS, |
| 1875 |
def->pvr); |
| 1876 |
printf("%s: PVR %08x mask %08x => %08x\n", __func__,
|
| 1877 |
def->pvr, def->pvr_mask, def->pvr & def->pvr_mask); |
| 1878 |
switch (def->pvr & def->pvr_mask) {
|
| 1879 |
/* Embedded PowerPC from IBM */
|
| 1880 |
case CPU_PPC_401A1: /* 401 A1 family */ |
| 1881 |
case CPU_PPC_401B2: /* 401 B2 family */ |
| 1882 |
case CPU_PPC_401C2: /* 401 C2 family */ |
| 1883 |
case CPU_PPC_401D2: /* 401 D2 family */ |
| 1884 |
case CPU_PPC_401E2: /* 401 E2 family */ |
| 1885 |
case CPU_PPC_401F2: /* 401 F2 family */ |
| 1886 |
case CPU_PPC_401G2: /* 401 G2 family */ |
| 1887 |
case CPU_PPC_IOP480: /* IOP 480 family */ |
| 1888 |
case CPU_PPC_COBRA: /* IBM Processor for Network Resources */ |
| 1889 |
gen_spr_generic(env); |
| 1890 |
gen_spr_40x(env); |
| 1891 |
gen_spr_401_403(env); |
| 1892 |
#if defined (TODO)
|
| 1893 |
/* XXX: optional ? */
|
| 1894 |
gen_spr_compress(env); |
| 1895 |
#endif
|
| 1896 |
env->nb_BATs = 0;
|
| 1897 |
env->nb_tlb = 64;
|
| 1898 |
env->nb_ways = 1;
|
| 1899 |
env->id_tlbs = 0;
|
| 1900 |
/* XXX: TODO: allocate internal IRQ controller */
|
| 1901 |
break;
|
| 1902 |
|
| 1903 |
case CPU_PPC_403GA: /* 403 GA family */ |
| 1904 |
case CPU_PPC_403GB: /* 403 GB family */ |
| 1905 |
case CPU_PPC_403GC: /* 403 GC family */ |
| 1906 |
case CPU_PPC_403GCX: /* 403 GCX family */ |
| 1907 |
gen_spr_generic(env); |
| 1908 |
gen_spr_40x(env); |
| 1909 |
gen_spr_401_403(env); |
| 1910 |
gen_spr_403(env); |
| 1911 |
env->nb_BATs = 0;
|
| 1912 |
env->nb_tlb = 64;
|
| 1913 |
env->nb_ways = 1;
|
| 1914 |
env->id_tlbs = 0;
|
| 1915 |
/* XXX: TODO: allocate internal IRQ controller */
|
| 1916 |
break;
|
| 1917 |
|
| 1918 |
case CPU_PPC_405CR: /* 405 GP/CR family */ |
| 1919 |
case CPU_PPC_405EP: /* 405 EP family */ |
| 1920 |
case CPU_PPC_405GPR: /* 405 GPR family */ |
| 1921 |
case CPU_PPC_405D2: /* 405 D2 family */ |
| 1922 |
case CPU_PPC_405D4: /* 405 D4 family */ |
| 1923 |
gen_spr_generic(env); |
| 1924 |
/* Time base */
|
| 1925 |
gen_tbl(env); |
| 1926 |
gen_spr_40x(env); |
| 1927 |
gen_spr_405(env); |
| 1928 |
env->nb_BATs = 0;
|
| 1929 |
env->nb_tlb = 64;
|
| 1930 |
env->nb_ways = 1;
|
| 1931 |
env->id_tlbs = 0;
|
| 1932 |
/* Allocate hardware IRQ controller */
|
| 1933 |
ppc405_irq_init(env); |
| 1934 |
break;
|
| 1935 |
|
| 1936 |
case CPU_PPC_NPE405H: /* NPe405 H family */ |
| 1937 |
case CPU_PPC_NPE405H2:
|
| 1938 |
case CPU_PPC_NPE405L: /* Npe405 L family */ |
| 1939 |
gen_spr_generic(env); |
| 1940 |
/* Time base */
|
| 1941 |
gen_tbl(env); |
| 1942 |
gen_spr_40x(env); |
| 1943 |
gen_spr_405(env); |
| 1944 |
env->nb_BATs = 0;
|
| 1945 |
env->nb_tlb = 64;
|
| 1946 |
env->nb_ways = 1;
|
| 1947 |
env->id_tlbs = 0;
|
| 1948 |
/* Allocate hardware IRQ controller */
|
| 1949 |
ppc405_irq_init(env); |
| 1950 |
break;
|
| 1951 |
|
| 1952 |
#if defined (TODO)
|
| 1953 |
case CPU_PPC_STB01000:
|
| 1954 |
#endif
|
| 1955 |
#if defined (TODO)
|
| 1956 |
case CPU_PPC_STB01010:
|
| 1957 |
#endif
|
| 1958 |
#if defined (TODO)
|
| 1959 |
case CPU_PPC_STB0210:
|
| 1960 |
#endif
|
| 1961 |
case CPU_PPC_STB03: /* STB03 family */ |
| 1962 |
#if defined (TODO)
|
| 1963 |
case CPU_PPC_STB043: /* STB043 family */ |
| 1964 |
#endif
|
| 1965 |
#if defined (TODO)
|
| 1966 |
case CPU_PPC_STB045: /* STB045 family */ |
| 1967 |
#endif
|
| 1968 |
case CPU_PPC_STB25: /* STB25 family */ |
| 1969 |
#if defined (TODO)
|
| 1970 |
case CPU_PPC_STB130: /* STB130 family */ |
| 1971 |
#endif
|
| 1972 |
gen_spr_generic(env); |
| 1973 |
/* Time base */
|
| 1974 |
gen_tbl(env); |
| 1975 |
gen_spr_40x(env); |
| 1976 |
gen_spr_405(env); |
| 1977 |
env->nb_BATs = 0;
|
| 1978 |
env->nb_tlb = 64;
|
| 1979 |
env->nb_ways = 1;
|
| 1980 |
env->id_tlbs = 0;
|
| 1981 |
/* Allocate hardware IRQ controller */
|
| 1982 |
ppc405_irq_init(env); |
| 1983 |
break;
|
| 1984 |
|
| 1985 |
case CPU_PPC_440EP: /* 440 EP family */ |
| 1986 |
case CPU_PPC_440GP: /* 440 GP family */ |
| 1987 |
case CPU_PPC_440GX: /* 440 GX family */ |
| 1988 |
case CPU_PPC_440GXc: /* 440 GXc family */ |
| 1989 |
case CPU_PPC_440GXf: /* 440 GXf family */ |
| 1990 |
case CPU_PPC_440SP: /* 440 SP family */ |
| 1991 |
case CPU_PPC_440SP2:
|
| 1992 |
case CPU_PPC_440SPE: /* 440 SPE family */ |
| 1993 |
gen_spr_generic(env); |
| 1994 |
/* Time base */
|
| 1995 |
gen_tbl(env); |
| 1996 |
gen_spr_BookE(env); |
| 1997 |
gen_spr_440(env); |
| 1998 |
env->nb_BATs = 0;
|
| 1999 |
env->nb_tlb = 64;
|
| 2000 |
env->nb_ways = 1;
|
| 2001 |
env->id_tlbs = 0;
|
| 2002 |
/* XXX: TODO: allocate internal IRQ controller */
|
| 2003 |
break;
|
| 2004 |
|
| 2005 |
/* Embedded PowerPC from Freescale */
|
| 2006 |
#if defined (TODO)
|
| 2007 |
case CPU_PPC_5xx:
|
| 2008 |
break;
|
| 2009 |
#endif
|
| 2010 |
#if defined (TODO)
|
| 2011 |
case CPU_PPC_8xx: /* MPC821 / 823 / 850 / 860 */ |
| 2012 |
break;
|
| 2013 |
#endif
|
| 2014 |
#if defined (TODO)
|
| 2015 |
case CPU_PPC_82xx_HIP3: /* MPC8240 / 8260 */ |
| 2016 |
case CPU_PPC_82xx_HIP4: /* MPC8240 / 8260 */ |
| 2017 |
break;
|
| 2018 |
#endif
|
| 2019 |
#if defined (TODO)
|
| 2020 |
case CPU_PPC_827x: /* MPC 827x / 828x */ |
| 2021 |
break;
|
| 2022 |
#endif
|
| 2023 |
|
| 2024 |
/* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */
|
| 2025 |
case CPU_PPC_e500v110:
|
| 2026 |
case CPU_PPC_e500v120:
|
| 2027 |
case CPU_PPC_e500v210:
|
| 2028 |
case CPU_PPC_e500v220:
|
| 2029 |
gen_spr_generic(env); |
| 2030 |
/* Time base */
|
| 2031 |
gen_tbl(env); |
| 2032 |
gen_spr_BookE(env); |
| 2033 |
gen_spr_BookE_FSL(env); |
| 2034 |
env->nb_BATs = 0;
|
| 2035 |
env->nb_tlb = 64;
|
| 2036 |
env->nb_ways = 1;
|
| 2037 |
env->id_tlbs = 0;
|
| 2038 |
/* XXX: TODO: allocate internal IRQ controller */
|
| 2039 |
break;
|
| 2040 |
|
| 2041 |
#if defined (TODO)
|
| 2042 |
case CPU_PPC_e600:
|
| 2043 |
break;
|
| 2044 |
#endif
|
| 2045 |
|
| 2046 |
/* 32 bits PowerPC */
|
| 2047 |
case CPU_PPC_601: /* PowerPC 601 */ |
| 2048 |
gen_spr_generic(env); |
| 2049 |
gen_spr_ne_601(env); |
| 2050 |
gen_spr_601(env); |
| 2051 |
/* Hardware implementation registers */
|
| 2052 |
/* XXX : not implemented */
|
| 2053 |
spr_register(env, SPR_HID0, "HID0",
|
| 2054 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2055 |
&spr_read_generic, &spr_write_generic, |
| 2056 |
0x00000000);
|
| 2057 |
/* XXX : not implemented */
|
| 2058 |
spr_register(env, SPR_HID1, "HID1",
|
| 2059 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2060 |
&spr_read_generic, &spr_write_generic, |
| 2061 |
0x00000000);
|
| 2062 |
/* XXX : not implemented */
|
| 2063 |
spr_register(env, SPR_601_HID2, "HID2",
|
| 2064 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2065 |
&spr_read_generic, &spr_write_generic, |
| 2066 |
0x00000000);
|
| 2067 |
/* XXX : not implemented */
|
| 2068 |
spr_register(env, SPR_601_HID5, "HID5",
|
| 2069 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2070 |
&spr_read_generic, &spr_write_generic, |
| 2071 |
0x00000000);
|
| 2072 |
/* XXX : not implemented */
|
| 2073 |
#if 0 /* ? */
|
| 2074 |
spr_register(env, SPR_601_HID15, "HID15",
|
| 2075 |
SPR_NOACCESS, SPR_NOACCESS,
|
| 2076 |
&spr_read_generic, &spr_write_generic,
|
| 2077 |
0x00000000);
|
| 2078 |
#endif
|
| 2079 |
env->nb_tlb = 64;
|
| 2080 |
env->nb_ways = 2;
|
| 2081 |
env->id_tlbs = 0;
|
| 2082 |
env->id_tlbs = 0;
|
| 2083 |
/* XXX: TODO: allocate internal IRQ controller */
|
| 2084 |
break;
|
| 2085 |
|
| 2086 |
case CPU_PPC_602: /* PowerPC 602 */ |
| 2087 |
gen_spr_generic(env); |
| 2088 |
gen_spr_ne_601(env); |
| 2089 |
/* Memory management */
|
| 2090 |
gen_low_BATs(env); |
| 2091 |
/* Time base */
|
| 2092 |
gen_tbl(env); |
| 2093 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
| 2094 |
gen_spr_602(env); |
| 2095 |
/* hardware implementation registers */
|
| 2096 |
/* XXX : not implemented */
|
| 2097 |
spr_register(env, SPR_HID0, "HID0",
|
| 2098 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2099 |
&spr_read_generic, &spr_write_generic, |
| 2100 |
0x00000000);
|
| 2101 |
/* XXX : not implemented */
|
| 2102 |
spr_register(env, SPR_HID1, "HID1",
|
| 2103 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2104 |
&spr_read_generic, &spr_write_generic, |
| 2105 |
0x00000000);
|
| 2106 |
/* Allocate hardware IRQ controller */
|
| 2107 |
ppc6xx_irq_init(env); |
| 2108 |
break;
|
| 2109 |
|
| 2110 |
case CPU_PPC_603: /* PowerPC 603 */ |
| 2111 |
case CPU_PPC_603E: /* PowerPC 603e */ |
| 2112 |
case CPU_PPC_603E7v:
|
| 2113 |
case CPU_PPC_603E7v2:
|
| 2114 |
case CPU_PPC_603P: /* PowerPC 603p */ |
| 2115 |
case CPU_PPC_603R: /* PowerPC 603r */ |
| 2116 |
gen_spr_generic(env); |
| 2117 |
gen_spr_ne_601(env); |
| 2118 |
/* Memory management */
|
| 2119 |
gen_low_BATs(env); |
| 2120 |
/* Time base */
|
| 2121 |
gen_tbl(env); |
| 2122 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
| 2123 |
gen_spr_603(env); |
| 2124 |
/* hardware implementation registers */
|
| 2125 |
/* XXX : not implemented */
|
| 2126 |
spr_register(env, SPR_HID0, "HID0",
|
| 2127 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2128 |
&spr_read_generic, &spr_write_generic, |
| 2129 |
0x00000000);
|
| 2130 |
/* XXX : not implemented */
|
| 2131 |
spr_register(env, SPR_HID1, "HID1",
|
| 2132 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2133 |
&spr_read_generic, &spr_write_generic, |
| 2134 |
0x00000000);
|
| 2135 |
/* Allocate hardware IRQ controller */
|
| 2136 |
ppc6xx_irq_init(env); |
| 2137 |
break;
|
| 2138 |
|
| 2139 |
case CPU_PPC_G2: /* PowerPC G2 family */ |
| 2140 |
case CPU_PPC_G2H4:
|
| 2141 |
case CPU_PPC_G2gp:
|
| 2142 |
case CPU_PPC_G2ls:
|
| 2143 |
case CPU_PPC_G2LE: /* PowerPC G2LE family */ |
| 2144 |
case CPU_PPC_G2LEgp:
|
| 2145 |
case CPU_PPC_G2LEls:
|
| 2146 |
gen_spr_generic(env); |
| 2147 |
gen_spr_ne_601(env); |
| 2148 |
/* Memory management */
|
| 2149 |
gen_low_BATs(env); |
| 2150 |
/* Time base */
|
| 2151 |
gen_tbl(env); |
| 2152 |
/* Memory management */
|
| 2153 |
gen_high_BATs(env); |
| 2154 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
| 2155 |
gen_spr_G2_755(env); |
| 2156 |
gen_spr_G2(env); |
| 2157 |
/* Hardware implementation register */
|
| 2158 |
/* XXX : not implemented */
|
| 2159 |
spr_register(env, SPR_HID0, "HID0",
|
| 2160 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2161 |
&spr_read_generic, &spr_write_generic, |
| 2162 |
0x00000000);
|
| 2163 |
/* XXX : not implemented */
|
| 2164 |
spr_register(env, SPR_HID1, "HID1",
|
| 2165 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2166 |
&spr_read_generic, &spr_write_generic, |
| 2167 |
0x00000000);
|
| 2168 |
/* XXX : not implemented */
|
| 2169 |
spr_register(env, SPR_HID2, "HID2",
|
| 2170 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2171 |
&spr_read_generic, &spr_write_generic, |
| 2172 |
0x00000000);
|
| 2173 |
/* Allocate hardware IRQ controller */
|
| 2174 |
ppc6xx_irq_init(env); |
| 2175 |
break;
|
| 2176 |
|
| 2177 |
case CPU_PPC_604: /* PowerPC 604 */ |
| 2178 |
case CPU_PPC_604E: /* PowerPC 604e */ |
| 2179 |
case CPU_PPC_604R: /* PowerPC 604r */ |
| 2180 |
gen_spr_generic(env); |
| 2181 |
gen_spr_ne_601(env); |
| 2182 |
/* Memory management */
|
| 2183 |
gen_low_BATs(env); |
| 2184 |
/* Time base */
|
| 2185 |
gen_tbl(env); |
| 2186 |
gen_spr_604(env); |
| 2187 |
/* Hardware implementation registers */
|
| 2188 |
/* XXX : not implemented */
|
| 2189 |
spr_register(env, SPR_HID0, "HID0",
|
| 2190 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2191 |
&spr_read_generic, &spr_write_generic, |
| 2192 |
0x00000000);
|
| 2193 |
/* XXX : not implemented */
|
| 2194 |
spr_register(env, SPR_HID1, "HID1",
|
| 2195 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2196 |
&spr_read_generic, &spr_write_generic, |
| 2197 |
0x00000000);
|
| 2198 |
/* Allocate hardware IRQ controller */
|
| 2199 |
ppc6xx_irq_init(env); |
| 2200 |
break;
|
| 2201 |
|
| 2202 |
case CPU_PPC_74x: /* PowerPC 740 / 750 */ |
| 2203 |
case CPU_PPC_740E:
|
| 2204 |
case CPU_PPC_750E:
|
| 2205 |
case CPU_PPC_74xP: /* PowerPC 740P / 750P */ |
| 2206 |
case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe */ |
| 2207 |
case CPU_PPC_750CXE22:
|
| 2208 |
case CPU_PPC_750CXE23:
|
| 2209 |
case CPU_PPC_750CXE24:
|
| 2210 |
case CPU_PPC_750CXE24b:
|
| 2211 |
case CPU_PPC_750CXE31:
|
| 2212 |
case CPU_PPC_750CXE31b:
|
| 2213 |
case CPU_PPC_750CXR:
|
| 2214 |
gen_spr_generic(env); |
| 2215 |
gen_spr_ne_601(env); |
| 2216 |
/* Memory management */
|
| 2217 |
gen_low_BATs(env); |
| 2218 |
/* Time base */
|
| 2219 |
gen_tbl(env); |
| 2220 |
gen_spr_7xx(env); |
| 2221 |
/* Hardware implementation registers */
|
| 2222 |
/* XXX : not implemented */
|
| 2223 |
spr_register(env, SPR_HID0, "HID0",
|
| 2224 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2225 |
&spr_read_generic, &spr_write_generic, |
| 2226 |
0x00000000);
|
| 2227 |
/* XXX : not implemented */
|
| 2228 |
spr_register(env, SPR_HID1, "HID1",
|
| 2229 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2230 |
&spr_read_generic, &spr_write_generic, |
| 2231 |
0x00000000);
|
| 2232 |
/* Allocate hardware IRQ controller */
|
| 2233 |
ppc6xx_irq_init(env); |
| 2234 |
break;
|
| 2235 |
|
| 2236 |
case CPU_PPC_750FX10: /* IBM PowerPC 750 FX */ |
| 2237 |
case CPU_PPC_750FX20:
|
| 2238 |
case CPU_PPC_750FX21:
|
| 2239 |
case CPU_PPC_750FX22:
|
| 2240 |
case CPU_PPC_750FX23:
|
| 2241 |
case CPU_PPC_750GX10: /* IBM PowerPC 750 GX */ |
| 2242 |
case CPU_PPC_750GX11:
|
| 2243 |
case CPU_PPC_750GX12:
|
| 2244 |
gen_spr_generic(env); |
| 2245 |
gen_spr_ne_601(env); |
| 2246 |
/* Memory management */
|
| 2247 |
gen_low_BATs(env); |
| 2248 |
/* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
|
| 2249 |
gen_high_BATs(env); |
| 2250 |
/* Time base */
|
| 2251 |
gen_tbl(env); |
| 2252 |
gen_spr_7xx(env); |
| 2253 |
/* Hardware implementation registers */
|
| 2254 |
/* XXX : not implemented */
|
| 2255 |
spr_register(env, SPR_HID0, "HID0",
|
| 2256 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2257 |
&spr_read_generic, &spr_write_generic, |
| 2258 |
0x00000000);
|
| 2259 |
/* XXX : not implemented */
|
| 2260 |
spr_register(env, SPR_HID1, "HID1",
|
| 2261 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2262 |
&spr_read_generic, &spr_write_generic, |
| 2263 |
0x00000000);
|
| 2264 |
/* XXX : not implemented */
|
| 2265 |
spr_register(env, SPR_750_HID2, "HID2",
|
| 2266 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2267 |
&spr_read_generic, &spr_write_generic, |
| 2268 |
0x00000000);
|
| 2269 |
/* Allocate hardware IRQ controller */
|
| 2270 |
ppc6xx_irq_init(env); |
| 2271 |
break;
|
| 2272 |
|
| 2273 |
case CPU_PPC_755_10: /* PowerPC 755 */ |
| 2274 |
case CPU_PPC_755_11:
|
| 2275 |
case CPU_PPC_755_20:
|
| 2276 |
case CPU_PPC_755D:
|
| 2277 |
case CPU_PPC_755E:
|
| 2278 |
gen_spr_generic(env); |
| 2279 |
gen_spr_ne_601(env); |
| 2280 |
/* Memory management */
|
| 2281 |
gen_low_BATs(env); |
| 2282 |
/* Time base */
|
| 2283 |
gen_tbl(env); |
| 2284 |
/* Memory management */
|
| 2285 |
gen_high_BATs(env); |
| 2286 |
gen_6xx_7xx_soft_tlb(env, 64, 2); |
| 2287 |
gen_spr_G2_755(env); |
| 2288 |
/* L2 cache control */
|
| 2289 |
/* XXX : not implemented */
|
| 2290 |
spr_register(env, SPR_ICTC, "ICTC",
|
| 2291 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2292 |
&spr_read_generic, &spr_write_generic, |
| 2293 |
0x00000000);
|
| 2294 |
/* XXX : not implemented */
|
| 2295 |
spr_register(env, SPR_L2PM, "L2PM",
|
| 2296 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2297 |
&spr_read_generic, &spr_write_generic, |
| 2298 |
0x00000000);
|
| 2299 |
/* Hardware implementation registers */
|
| 2300 |
/* XXX : not implemented */
|
| 2301 |
spr_register(env, SPR_HID0, "HID0",
|
| 2302 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2303 |
&spr_read_generic, &spr_write_generic, |
| 2304 |
0x00000000);
|
| 2305 |
/* XXX : not implemented */
|
| 2306 |
spr_register(env, SPR_HID1, "HID1",
|
| 2307 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2308 |
&spr_read_generic, &spr_write_generic, |
| 2309 |
0x00000000);
|
| 2310 |
/* XXX : not implemented */
|
| 2311 |
spr_register(env, SPR_HID2, "HID2",
|
| 2312 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2313 |
&spr_read_generic, &spr_write_generic, |
| 2314 |
0x00000000);
|
| 2315 |
/* Allocate hardware IRQ controller */
|
| 2316 |
ppc6xx_irq_init(env); |
| 2317 |
break;
|
| 2318 |
|
| 2319 |
#if defined (TODO)
|
| 2320 |
/* G4 family */
|
| 2321 |
case CPU_PPC_7400: /* PowerPC 7400 */ |
| 2322 |
case CPU_PPC_7410C: /* PowerPC 7410 */ |
| 2323 |
case CPU_PPC_7410D:
|
| 2324 |
case CPU_PPC_7410E:
|
| 2325 |
case CPU_PPC_7441: /* PowerPC 7441 */ |
| 2326 |
case CPU_PPC_7445: /* PowerPC 7445 */ |
| 2327 |
case CPU_PPC_7447: /* PowerPC 7447 */ |
| 2328 |
case CPU_PPC_7447A: /* PowerPC 7447A */ |
| 2329 |
case CPU_PPC_7448: /* PowerPC 7448 */ |
| 2330 |
case CPU_PPC_7450: /* PowerPC 7450 */ |
| 2331 |
case CPU_PPC_7450b:
|
| 2332 |
case CPU_PPC_7451: /* PowerPC 7451 */ |
| 2333 |
case CPU_PPC_7451G:
|
| 2334 |
case CPU_PPC_7455: /* PowerPC 7455 */ |
| 2335 |
case CPU_PPC_7455F:
|
| 2336 |
case CPU_PPC_7455G:
|
| 2337 |
case CPU_PPC_7457: /* PowerPC 7457 */ |
| 2338 |
case CPU_PPC_7457C:
|
| 2339 |
case CPU_PPC_7457A: /* PowerPC 7457A */ |
| 2340 |
break;
|
| 2341 |
#endif
|
| 2342 |
|
| 2343 |
/* 64 bits PowerPC */
|
| 2344 |
#if defined (TARGET_PPC64)
|
| 2345 |
#if defined (TODO)
|
| 2346 |
case CPU_PPC_620: /* PowerPC 620 */ |
| 2347 |
case CPU_PPC_630: /* PowerPC 630 (Power 3) */ |
| 2348 |
case CPU_PPC_631: /* PowerPC 631 (Power 3+) */ |
| 2349 |
case CPU_PPC_POWER4: /* Power 4 */ |
| 2350 |
case CPU_PPC_POWER4P: /* Power 4+ */ |
| 2351 |
case CPU_PPC_POWER5: /* Power 5 */ |
| 2352 |
case CPU_PPC_POWER5P: /* Power 5+ */ |
| 2353 |
#endif
|
| 2354 |
break;
|
| 2355 |
|
| 2356 |
case CPU_PPC_970: /* PowerPC 970 */ |
| 2357 |
case CPU_PPC_970FX10: /* PowerPC 970 FX */ |
| 2358 |
case CPU_PPC_970FX20:
|
| 2359 |
case CPU_PPC_970FX21:
|
| 2360 |
case CPU_PPC_970FX30:
|
| 2361 |
case CPU_PPC_970FX31:
|
| 2362 |
case CPU_PPC_970MP10: /* PowerPC 970 MP */ |
| 2363 |
case CPU_PPC_970MP11:
|
| 2364 |
gen_spr_generic(env); |
| 2365 |
gen_spr_ne_601(env); |
| 2366 |
/* XXX: not correct */
|
| 2367 |
gen_low_BATs(env); |
| 2368 |
/* Time base */
|
| 2369 |
gen_tbl(env); |
| 2370 |
gen_spr_7xx(env); |
| 2371 |
/* Hardware implementation registers */
|
| 2372 |
/* XXX : not implemented */
|
| 2373 |
spr_register(env, SPR_HID0, "HID0",
|
| 2374 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2375 |
&spr_read_generic, &spr_write_generic, |
| 2376 |
0x00000000);
|
| 2377 |
/* XXX : not implemented */
|
| 2378 |
spr_register(env, SPR_HID1, "HID1",
|
| 2379 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2380 |
&spr_read_generic, &spr_write_generic, |
| 2381 |
0x00000000);
|
| 2382 |
/* XXX : not implemented */
|
| 2383 |
spr_register(env, SPR_750_HID2, "HID2",
|
| 2384 |
SPR_NOACCESS, SPR_NOACCESS, |
| 2385 |
&spr_read_generic, &spr_write_generic, |
| 2386 |
0x00000000);
|
| 2387 |
/* Allocate hardware IRQ controller */
|
| 2388 |
ppc970_irq_init(env); |
| 2389 |
break;
|
| 2390 |
|
| 2391 |
#if defined (TODO)
|
| 2392 |
case CPU_PPC_CELL10: /* Cell family */ |
| 2393 |
case CPU_PPC_CELL20:
|
| 2394 |
case CPU_PPC_CELL30:
|
| 2395 |
case CPU_PPC_CELL31:
|
| 2396 |
#endif
|
| 2397 |
break;
|
| 2398 |
|
| 2399 |
#if defined (TODO)
|
| 2400 |
case CPU_PPC_RS64: /* Apache (RS64/A35) */ |
| 2401 |
case CPU_PPC_RS64II: /* NorthStar (RS64-II/A50) */ |
| 2402 |
case CPU_PPC_RS64III: /* Pulsar (RS64-III) */ |
| 2403 |
case CPU_PPC_RS64IV: /* IceStar/IStar/SStar (RS64-IV) */ |
| 2404 |
#endif
|
| 2405 |
break;
|
| 2406 |
#endif /* defined (TARGET_PPC64) */ |
| 2407 |
|
| 2408 |
#if defined (TODO)
|
| 2409 |
/* POWER */
|
| 2410 |
case CPU_POWER: /* POWER */ |
| 2411 |
case CPU_POWER2: /* POWER2 */ |
| 2412 |
break;
|
| 2413 |
#endif
|
| 2414 |
|
| 2415 |
default:
|
| 2416 |
gen_spr_generic(env); |
| 2417 |
/* XXX: TODO: allocate internal IRQ controller */
|
| 2418 |
break;
|
| 2419 |
} |
| 2420 |
if (env->nb_BATs == -1) |
| 2421 |
env->nb_BATs = 4;
|
| 2422 |
/* Allocate TLBs buffer when needed */
|
| 2423 |
if (env->nb_tlb != 0) { |
| 2424 |
int nb_tlb = env->nb_tlb;
|
| 2425 |
if (env->id_tlbs != 0) |
| 2426 |
nb_tlb *= 2;
|
| 2427 |
env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
|
| 2428 |
/* Pre-compute some useful values */
|
| 2429 |
env->tlb_per_way = env->nb_tlb / env->nb_ways; |
| 2430 |
} |
| 2431 |
} |
| 2432 |
|
| 2433 |
#if defined(PPC_DUMP_CPU)
|
| 2434 |
static void dump_sprs (CPUPPCState *env) |
| 2435 |
{
|
| 2436 |
ppc_spr_t *spr; |
| 2437 |
uint32_t pvr = env->spr[SPR_PVR]; |
| 2438 |
uint32_t sr, sw, ur, uw; |
| 2439 |
int i, j, n;
|
| 2440 |
|
| 2441 |
printf("* SPRs for PVR=%08x\n", pvr);
|
| 2442 |
for (i = 0; i < 32; i++) { |
| 2443 |
for (j = 0; j < 32; j++) { |
| 2444 |
n = (i << 5) | j;
|
| 2445 |
spr = &env->spr_cb[n]; |
| 2446 |
#if !defined(CONFIG_USER_ONLY)
|
| 2447 |
sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
|
| 2448 |
sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
|
| 2449 |
#else
|
| 2450 |
sw = 0;
|
| 2451 |
sr = 0;
|
| 2452 |
#endif
|
| 2453 |
uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
|
| 2454 |
ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
|
| 2455 |
if (sw || sr || uw || ur) {
|
| 2456 |
printf("%4d (%03x) %8s s%c%c u%c%c\n",
|
| 2457 |
(i << 5) | j, (i << 5) | j, spr->name, |
| 2458 |
sw ? 'w' : '-', sr ? 'r' : '-', |
| 2459 |
uw ? 'w' : '-', ur ? 'r' : '-'); |
| 2460 |
} |
| 2461 |
} |
| 2462 |
} |
| 2463 |
fflush(stdout); |
| 2464 |
fflush(stderr); |
| 2465 |
} |
| 2466 |
#endif
|
| 2467 |
|
| 2468 |
/*****************************************************************************/
|
| 2469 |
#include <stdlib.h> |
| 2470 |
#include <string.h> |
| 2471 |
|
| 2472 |
int fflush (FILE *stream);
|
| 2473 |
|
| 2474 |
/* Opcode types */
|
| 2475 |
enum {
|
| 2476 |
PPC_DIRECT = 0, /* Opcode routine */ |
| 2477 |
PPC_INDIRECT = 1, /* Indirect opcode table */ |
| 2478 |
}; |
| 2479 |
|
| 2480 |
static inline int is_indirect_opcode (void *handler) |
| 2481 |
{
|
| 2482 |
return ((unsigned long)handler & 0x03) == PPC_INDIRECT; |
| 2483 |
} |
| 2484 |
|
| 2485 |
static inline opc_handler_t **ind_table(void *handler) |
| 2486 |
{
|
| 2487 |
return (opc_handler_t **)((unsigned long)handler & ~3); |
| 2488 |
} |
| 2489 |
|
| 2490 |
/* Instruction table creation */
|
| 2491 |
/* Opcodes tables creation */
|
| 2492 |
static void fill_new_table (opc_handler_t **table, int len) |
| 2493 |
{
|
| 2494 |
int i;
|
| 2495 |
|
| 2496 |
for (i = 0; i < len; i++) |
| 2497 |
table[i] = &invalid_handler; |
| 2498 |
} |
| 2499 |
|
| 2500 |
static int create_new_table (opc_handler_t **table, unsigned char idx) |
| 2501 |
{
|
| 2502 |
opc_handler_t **tmp; |
| 2503 |
|
| 2504 |
tmp = malloc(0x20 * sizeof(opc_handler_t)); |
| 2505 |
if (tmp == NULL) |
| 2506 |
return -1; |
| 2507 |
fill_new_table(tmp, 0x20);
|
| 2508 |
table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT); |
| 2509 |
|
| 2510 |
return 0; |
| 2511 |
} |
| 2512 |
|
| 2513 |
static int insert_in_table (opc_handler_t **table, unsigned char idx, |
| 2514 |
opc_handler_t *handler) |
| 2515 |
{
|
| 2516 |
if (table[idx] != &invalid_handler)
|
| 2517 |
return -1; |
| 2518 |
table[idx] = handler; |
| 2519 |
|
| 2520 |
return 0; |
| 2521 |
} |
| 2522 |
|
| 2523 |
static int register_direct_insn (opc_handler_t **ppc_opcodes, |
| 2524 |
unsigned char idx, opc_handler_t *handler) |
| 2525 |
{
|
| 2526 |
if (insert_in_table(ppc_opcodes, idx, handler) < 0) { |
| 2527 |
printf("*** ERROR: opcode %02x already assigned in main "
|
| 2528 |
"opcode table\n", idx);
|
| 2529 |
return -1; |
| 2530 |
} |
| 2531 |
|
| 2532 |
return 0; |
| 2533 |
} |
| 2534 |
|
| 2535 |
static int register_ind_in_table (opc_handler_t **table, |
| 2536 |
unsigned char idx1, unsigned char idx2, |
| 2537 |
opc_handler_t *handler) |
| 2538 |
{
|
| 2539 |
if (table[idx1] == &invalid_handler) {
|
| 2540 |
if (create_new_table(table, idx1) < 0) { |
| 2541 |
printf("*** ERROR: unable to create indirect table "
|
| 2542 |
"idx=%02x\n", idx1);
|
| 2543 |
return -1; |
| 2544 |
} |
| 2545 |
} else {
|
| 2546 |
if (!is_indirect_opcode(table[idx1])) {
|
| 2547 |
printf("*** ERROR: idx %02x already assigned to a direct "
|
| 2548 |
"opcode\n", idx1);
|
| 2549 |
return -1; |
| 2550 |
} |
| 2551 |
} |
| 2552 |
if (handler != NULL && |
| 2553 |
insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
|
| 2554 |
printf("*** ERROR: opcode %02x already assigned in "
|
| 2555 |
"opcode table %02x\n", idx2, idx1);
|
| 2556 |
return -1; |
| 2557 |
} |
| 2558 |
|
| 2559 |
return 0; |
| 2560 |
} |
| 2561 |
|
| 2562 |
static int register_ind_insn (opc_handler_t **ppc_opcodes, |
| 2563 |
unsigned char idx1, unsigned char idx2, |
| 2564 |
opc_handler_t *handler) |
| 2565 |
{
|
| 2566 |
int ret;
|
| 2567 |
|
| 2568 |
ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler); |
| 2569 |
|
| 2570 |
return ret;
|
| 2571 |
} |
| 2572 |
|
| 2573 |
static int register_dblind_insn (opc_handler_t **ppc_opcodes, |
| 2574 |
unsigned char idx1, unsigned char idx2, |
| 2575 |
unsigned char idx3, opc_handler_t *handler) |
| 2576 |
{
|
| 2577 |
if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { |
| 2578 |
printf("*** ERROR: unable to join indirect table idx "
|
| 2579 |
"[%02x-%02x]\n", idx1, idx2);
|
| 2580 |
return -1; |
| 2581 |
} |
| 2582 |
if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
|
| 2583 |
handler) < 0) {
|
| 2584 |
printf("*** ERROR: unable to insert opcode "
|
| 2585 |
"[%02x-%02x-%02x]\n", idx1, idx2, idx3);
|
| 2586 |
return -1; |
| 2587 |
} |
| 2588 |
|
| 2589 |
return 0; |
| 2590 |
} |
| 2591 |
|
| 2592 |
static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn) |
| 2593 |
{
|
| 2594 |
if (insn->opc2 != 0xFF) { |
| 2595 |
if (insn->opc3 != 0xFF) { |
| 2596 |
if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
|
| 2597 |
insn->opc3, &insn->handler) < 0)
|
| 2598 |
return -1; |
| 2599 |
} else {
|
| 2600 |
if (register_ind_insn(ppc_opcodes, insn->opc1,
|
| 2601 |
insn->opc2, &insn->handler) < 0)
|
| 2602 |
return -1; |
| 2603 |
} |
| 2604 |
} else {
|
| 2605 |
if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) |
| 2606 |
return -1; |
| 2607 |
} |
| 2608 |
|
| 2609 |
return 0; |
| 2610 |
} |
| 2611 |
|
| 2612 |
static int test_opcode_table (opc_handler_t **table, int len) |
| 2613 |
{
|
| 2614 |
int i, count, tmp;
|
| 2615 |
|
| 2616 |
for (i = 0, count = 0; i < len; i++) { |
| 2617 |
/* Consistency fixup */
|
| 2618 |
if (table[i] == NULL) |
| 2619 |
table[i] = &invalid_handler; |
| 2620 |
if (table[i] != &invalid_handler) {
|
| 2621 |
if (is_indirect_opcode(table[i])) {
|
| 2622 |
tmp = test_opcode_table(ind_table(table[i]), 0x20);
|
| 2623 |
if (tmp == 0) { |
| 2624 |
free(table[i]); |
| 2625 |
table[i] = &invalid_handler; |
| 2626 |
} else {
|
| 2627 |
count++; |
| 2628 |
} |
| 2629 |
} else {
|
| 2630 |
count++; |
| 2631 |
} |
| 2632 |
} |
| 2633 |
} |
| 2634 |
|
| 2635 |
return count;
|
| 2636 |
} |
| 2637 |
|
| 2638 |
static void fix_opcode_tables (opc_handler_t **ppc_opcodes) |
| 2639 |
{
|
| 2640 |
if (test_opcode_table(ppc_opcodes, 0x40) == 0) |
| 2641 |
printf("*** WARNING: no opcode defined !\n");
|
| 2642 |
} |
| 2643 |
|
| 2644 |
/*****************************************************************************/
|
| 2645 |
static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def) |
| 2646 |
{
|
| 2647 |
opcode_t *opc, *start, *end; |
| 2648 |
|
| 2649 |
fill_new_table(env->opcodes, 0x40);
|
| 2650 |
#if defined(PPC_DUMP_CPU)
|
| 2651 |
printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64
|
| 2652 |
" %08x\n",
|
| 2653 |
def->pvr, def->name, def->insns_flags, def->flags); |
| 2654 |
#endif
|
| 2655 |
if (&opc_start < &opc_end) {
|
| 2656 |
start = &opc_start; |
| 2657 |
end = &opc_end; |
| 2658 |
} else {
|
| 2659 |
start = &opc_end; |
| 2660 |
end = &opc_start; |
| 2661 |
} |
| 2662 |
for (opc = start + 1; opc != end; opc++) { |
| 2663 |
if ((opc->handler.type & def->insns_flags) != 0) { |
| 2664 |
if (register_insn(env->opcodes, opc) < 0) { |
| 2665 |
printf("*** ERROR initializing PowerPC instruction "
|
| 2666 |
"0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
|
| 2667 |
opc->opc3); |
| 2668 |
return -1; |
| 2669 |
} |
| 2670 |
#if defined(PPC_DUMP_CPU)
|
| 2671 |
if (opc1 != 0x00) { |
| 2672 |
if (opc->opc3 == 0xFF) { |
| 2673 |
if (opc->opc2 == 0xFF) { |
| 2674 |
printf(" %02x -- -- (%2d ----) : %s\n",
|
| 2675 |
opc->opc1, opc->opc1, opc->oname); |
| 2676 |
} else {
|
| 2677 |
printf(" %02x %02x -- (%2d %4d) : %s\n",
|
| 2678 |
opc->opc1, opc->opc2, opc->opc1, opc->opc2, |
| 2679 |
opc->oname); |
| 2680 |
} |
| 2681 |
} else {
|
| 2682 |
printf(" %02x %02x %02x (%2d %4d) : %s\n",
|
| 2683 |
opc->opc1, opc->opc2, opc->opc3, |
| 2684 |
opc->opc1, (opc->opc3 << 5) | opc->opc2,
|
| 2685 |
opc->oname); |
| 2686 |
} |
| 2687 |
} |
| 2688 |
#endif
|
| 2689 |
} |
| 2690 |
} |
| 2691 |
fix_opcode_tables(env->opcodes); |
| 2692 |
fflush(stdout); |
| 2693 |
fflush(stderr); |
| 2694 |
|
| 2695 |
return 0; |
| 2696 |
} |
| 2697 |
|
| 2698 |
int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
|
| 2699 |
{
|
| 2700 |
env->msr_mask = def->msr_mask; |
| 2701 |
env->flags = def->flags; |
| 2702 |
if (create_ppc_opcodes(env, def) < 0) |
| 2703 |
return -1; |
| 2704 |
init_ppc_proc(env, def); |
| 2705 |
#if defined(PPC_DUMP_CPU)
|
| 2706 |
dump_sprs(env); |
| 2707 |
if (env->tlb != NULL) { |
| 2708 |
printf("%d %s TLB in %d ways\n", env->nb_tlb,
|
| 2709 |
env->id_tlbs ? "splitted" : "merged", env->nb_ways); |
| 2710 |
} |
| 2711 |
#endif
|
| 2712 |
|
| 2713 |
return 0; |
| 2714 |
} |
| 2715 |
|
| 2716 |
void do_compute_hflags (CPUPPCState *env);
|
| 2717 |
CPUPPCState *cpu_ppc_init (void)
|
| 2718 |
{
|
| 2719 |
CPUPPCState *env; |
| 2720 |
|
| 2721 |
env = qemu_mallocz(sizeof(CPUPPCState));
|
| 2722 |
if (!env)
|
| 2723 |
return NULL; |
| 2724 |
cpu_exec_init(env); |
| 2725 |
tlb_flush(env, 1);
|
| 2726 |
#if defined (DO_SINGLE_STEP) && 0 |
| 2727 |
/* Single step trace mode */
|
| 2728 |
msr_se = 1;
|
| 2729 |
msr_be = 1;
|
| 2730 |
#endif
|
| 2731 |
msr_fp = 1; /* Allow floating point exceptions */ |
| 2732 |
msr_me = 1; /* Allow machine check exceptions */ |
| 2733 |
#if defined(CONFIG_USER_ONLY)
|
| 2734 |
msr_pr = 1;
|
| 2735 |
#else
|
| 2736 |
env->nip = 0xFFFFFFFC;
|
| 2737 |
#endif
|
| 2738 |
do_compute_hflags(env); |
| 2739 |
env->reserve = -1;
|
| 2740 |
return env;
|
| 2741 |
} |
| 2742 |
|
| 2743 |
void cpu_ppc_close(CPUPPCState *env)
|
| 2744 |
{
|
| 2745 |
/* Should also remove all opcode tables... */
|
| 2746 |
free(env); |
| 2747 |
} |
| 2748 |
|
| 2749 |
/*****************************************************************************/
|
| 2750 |
/* PowerPC CPU definitions */
|
| 2751 |
static ppc_def_t ppc_defs[] =
|
| 2752 |
{
|
| 2753 |
/* Embedded PowerPC */
|
| 2754 |
#if defined (TODO)
|
| 2755 |
/* PowerPC 401 */
|
| 2756 |
{
|
| 2757 |
.name = "401",
|
| 2758 |
.pvr = CPU_PPC_401, |
| 2759 |
.pvr_mask = 0xFFFF0000,
|
| 2760 |
.insns_flags = PPC_INSNS_401, |
| 2761 |
.flags = PPC_FLAGS_401, |
| 2762 |
.msr_mask = xxx, |
| 2763 |
}, |
| 2764 |
#endif
|
| 2765 |
#if defined (TODO)
|
| 2766 |
/* IOP480 (401 microcontroler) */
|
| 2767 |
{
|
| 2768 |
.name = "iop480",
|
| 2769 |
.pvr = CPU_PPC_IOP480, |
| 2770 |
.pvr_mask = 0xFFFF0000,
|
| 2771 |
.insns_flags = PPC_INSNS_401, |
| 2772 |
.flags = PPC_FLAGS_401, |
| 2773 |
.msr_mask = xxx, |
| 2774 |
}, |
| 2775 |
#endif
|
| 2776 |
#if defined (TODO)
|
| 2777 |
/* IBM Processor for Network Resources */
|
| 2778 |
{
|
| 2779 |
.name = "Cobra",
|
| 2780 |
.pvr = CPU_PPC_COBRA, |
| 2781 |
.pvr_mask = 0xFFFF0000,
|
| 2782 |
.insns_flags = PPC_INSNS_401, |
| 2783 |
.flags = PPC_FLAGS_401, |
| 2784 |
.msr_mask = xxx, |
| 2785 |
}, |
| 2786 |
#endif
|
| 2787 |
#if defined (TODO)
|
| 2788 |
/* Generic PowerPC 403 */
|
| 2789 |
{
|
| 2790 |
.name = "403",
|
| 2791 |
.pvr = CPU_PPC_403, |
| 2792 |
.pvr_mask = 0xFFFFFF00,
|
| 2793 |
.insns_flags = PPC_INSNS_403, |
| 2794 |
.flags = PPC_FLAGS_403, |
| 2795 |
.msr_mask = 0x000000000007D23D,
|
| 2796 |
}, |
| 2797 |
#endif
|
| 2798 |
#if defined (TODO)
|
| 2799 |
/* PowerPC 403 GA */
|
| 2800 |
{
|
| 2801 |
.name = "403ga",
|
| 2802 |
.pvr = CPU_PPC_403GA, |
| 2803 |
.pvr_mask = 0xFFFFFF00,
|
| 2804 |
.insns_flags = PPC_INSNS_403, |
| 2805 |
.flags = PPC_FLAGS_403, |
| 2806 |
.msr_mask = 0x000000000007D23D,
|
| 2807 |
}, |
| 2808 |
#endif
|
| 2809 |
#if defined (TODO)
|
| 2810 |
/* PowerPC 403 GB */
|
| 2811 |
{
|
| 2812 |
.name = "403gb",
|
| 2813 |
.pvr = CPU_PPC_403GB, |
| 2814 |
.pvr_mask = 0xFFFFFF00,
|
| 2815 |
.insns_flags = PPC_INSNS_403, |
| 2816 |
.flags = PPC_FLAGS_403, |
| 2817 |
.msr_mask = 0x000000000007D23D,
|
| 2818 |
}, |
| 2819 |
#endif
|
| 2820 |
#if defined (TODO)
|
| 2821 |
/* PowerPC 403 GC */
|
| 2822 |
{
|
| 2823 |
.name = "403gc",
|
| 2824 |
.pvr = CPU_PPC_403GC, |
| 2825 |
.pvr_mask = 0xFFFFFF00,
|
| 2826 |
.insns_flags = PPC_INSNS_403, |
| 2827 |
.flags = PPC_FLAGS_403, |
| 2828 |
.msr_mask = 0x000000000007D23D,
|
| 2829 |
}, |
| 2830 |
#endif
|
| 2831 |
#if defined (TODO)
|
| 2832 |
/* PowerPC 403 GCX */
|
| 2833 |
{
|
| 2834 |
.name = "403gcx",
|
| 2835 |
.pvr = CPU_PPC_403GCX, |
| 2836 |
.pvr_mask = 0xFFFFFF00,
|
| 2837 |
.insns_flags = PPC_INSNS_403, |
| 2838 |
.flags = PPC_FLAGS_403, |
| 2839 |
.msr_mask = 0x000000000007D23D,
|
| 2840 |
}, |
| 2841 |
#endif
|
| 2842 |
#if defined (TODO)
|
| 2843 |
/* Generic PowerPC 405 */
|
| 2844 |
{
|
| 2845 |
.name = "405",
|
| 2846 |
.pvr = CPU_PPC_405, |
| 2847 |
.pvr_mask = 0xFFFF0000,
|
| 2848 |
.insns_flags = PPC_INSNS_405, |
| 2849 |
.flags = PPC_FLAGS_405, |
| 2850 |
.msr_mask = 0x00000000020EFF30,
|
| 2851 |
}, |
| 2852 |
#endif
|
| 2853 |
#if defined (TODO)
|
| 2854 |
/* PowerPC 405 CR */
|
| 2855 |
{
|
| 2856 |
.name = "405cr",
|
| 2857 |
.pvr = CPU_PPC_405, |
| 2858 |
.pvr_mask = 0xFFFF0000,
|
| 2859 |
.insns_flags = PPC_INSNS_405, |
| 2860 |
.flags = PPC_FLAGS_405, |
| 2861 |
.msr_mask = 0x00000000020EFF30,
|
| 2862 |
}, |
| 2863 |
#endif
|
| 2864 |
#if defined (TODO)
|
| 2865 |
/* PowerPC 405 GP */
|
| 2866 |
{
|
| 2867 |
.name = "405gp",
|
| 2868 |
.pvr = CPU_PPC_405, |
| 2869 |
.pvr_mask = 0xFFFF0000,
|
| 2870 |
.insns_flags = PPC_INSNS_405, |
| 2871 |
.flags = PPC_FLAGS_405, |
| 2872 |
.msr_mask = 0x00000000020EFF30,
|
| 2873 |
}, |
| 2874 |
#endif
|
| 2875 |
#if defined (TODO)
|
| 2876 |
/* PowerPC 405 EP */
|
| 2877 |
{
|
| 2878 |
.name = "405ep",
|
| 2879 |
.pvr = CPU_PPC_405EP, |
| 2880 |
.pvr_mask = 0xFFFF0000,
|
| 2881 |
.insns_flags = PPC_INSNS_405, |
| 2882 |
.flags = PPC_FLAGS_405, |
| 2883 |
.msr_mask = 0x00000000020EFF30,
|
| 2884 |
}, |
| 2885 |
#endif
|
| 2886 |
#if defined (TODO)
|
| 2887 |
/* PowerPC 405 GPR */
|
| 2888 |
{
|
| 2889 |
.name = "405gpr",
|
| 2890 |
.pvr = CPU_PPC_405GPR, |
| 2891 |
.pvr_mask = 0xFFFF0000,
|
| 2892 |
.insns_flags = PPC_INSNS_405, |
| 2893 |
.flags = PPC_FLAGS_405, |
| 2894 |
.msr_mask = 0x00000000020EFF30,
|
| 2895 |
}, |
| 2896 |
#endif
|
| 2897 |
#if defined (TODO)
|
| 2898 |
/* PowerPC 405 D2 */
|
| 2899 |
{
|
| 2900 |
.name = "405d2",
|
| 2901 |
.pvr = CPU_PPC_405D2, |
| 2902 |
.pvr_mask = 0xFFFF0000,
|
| 2903 |
.insns_flags = PPC_INSNS_405, |
| 2904 |
.flags = PPC_FLAGS_405, |
| 2905 |
.msr_mask = 0x00000000020EFF30,
|
| 2906 |
}, |
| 2907 |
#endif
|
| 2908 |
#if defined (TODO)
|
| 2909 |
/* PowerPC 405 D4 */
|
| 2910 |
{
|
| 2911 |
.name = "405d4",
|
| 2912 |
.pvr = CPU_PPC_405D4, |
| 2913 |
.pvr_mask = 0xFFFF0000,
|
| 2914 |
.insns_flags = PPC_INSNS_405, |
| 2915 |
.flags = PPC_FLAGS_405, |
| 2916 |
.msr_mask = 0x00000000020EFF30,
|
| 2917 |
}, |
| 2918 |
#endif
|
| 2919 |
#if defined (TODO)
|
| 2920 |
/* Npe405 H */
|
| 2921 |
{
|
| 2922 |
.name = "Npe405H",
|
| 2923 |
.pvr = CPU_PPC_NPE405H, |
| 2924 |
.pvr_mask = 0xFFFF0000,
|
| 2925 |
.insns_flags = PPC_INSNS_405, |
| 2926 |
.flags = PPC_FLAGS_405, |
| 2927 |
.msr_mask = 0x00000000020EFF30,
|
| 2928 |
}, |
| 2929 |
#endif
|
| 2930 |
#if defined (TODO)
|
| 2931 |
/* Npe405 L */
|
| 2932 |
{
|
| 2933 |
.name = "Npe405L",
|
| 2934 |
.pvr = CPU_PPC_NPE405L, |
| 2935 |
.pvr_mask = 0xFFFF0000,
|
| 2936 |
.insns_flags = PPC_INSNS_405, |
| 2937 |
.flags = PPC_FLAGS_405, |
| 2938 |
.msr_mask = 0x00000000020EFF30,
|
| 2939 |
}, |
| 2940 |
#endif
|
| 2941 |
#if defined (TODO)
|
| 2942 |
/* STB010000 */
|
| 2943 |
{
|
| 2944 |
.name = "STB01000",
|
| 2945 |
.pvr = CPU_PPC_STB01000, |
| 2946 |
.pvr_mask = 0xFFFF0000,
|
| 2947 |
.insns_flags = PPC_INSNS_405, |
| 2948 |
.flags = PPC_FLAGS_405, |
| 2949 |
.msr_mask = 0x00000000020EFF30,
|
| 2950 |
}, |
| 2951 |
#endif
|
| 2952 |
#if defined (TODO)
|
| 2953 |
/* STB01010 */
|
| 2954 |
{
|
| 2955 |
.name = "STB01010",
|
| 2956 |
.pvr = CPU_PPC_STB01010, |
| 2957 |
.pvr_mask = 0xFFFF0000,
|
| 2958 |
.insns_flags = PPC_INSNS_405, |
| 2959 |
.flags = PPC_FLAGS_405, |
| 2960 |
.msr_mask = 0x00000000020EFF30,
|
| 2961 |
}, |
| 2962 |
#endif
|
| 2963 |
#if defined (TODO)
|
| 2964 |
/* STB0210 */
|
| 2965 |
{
|
| 2966 |
.name = "STB0210",
|
| 2967 |
.pvr = CPU_PPC_STB0210, |
| 2968 |
.pvr_mask = 0xFFFF0000,
|
| 2969 |
.insns_flags = PPC_INSNS_405, |
| 2970 |
.flags = PPC_FLAGS_405, |
| 2971 |
.msr_mask = 0x00000000020EFF30,
|
| 2972 |
}, |
| 2973 |
#endif
|
| 2974 |
#if defined (TODO)
|
| 2975 |
/* STB03xx */
|
| 2976 |
{
|
| 2977 |
.name = "STB03",
|
| 2978 |
.pvr = CPU_PPC_STB03, |
| 2979 |
.pvr_mask = 0xFFFF0000,
|
| 2980 |
.insns_flags = PPC_INSNS_405, |
| 2981 |
.flags = PPC_FLAGS_405, |
| 2982 |
.msr_mask = 0x00000000020EFF30,
|
| 2983 |
}, |
| 2984 |
#endif
|
| 2985 |
#if defined (TODO)
|
| 2986 |
/* STB043x */
|
| 2987 |
{
|
| 2988 |
.name = "STB043",
|
| 2989 |
.pvr = CPU_PPC_STB043, |
| 2990 |
.pvr_mask = 0xFFFF0000,
|
| 2991 |
.insns_flags = PPC_INSNS_405, |
| 2992 |
.flags = PPC_FLAGS_405, |
| 2993 |
.msr_mask = 0x00000000020EFF30,
|
| 2994 |
}, |
| 2995 |
#endif
|
| 2996 |
#if defined (TODO)
|
| 2997 |
/* STB045x */
|
| 2998 |
{
|
| 2999 |
.name = "STB045",
|
| 3000 |
.pvr = CPU_PPC_STB045, |
| 3001 |
.pvr_mask = 0xFFFF0000,
|
| 3002 |
.insns_flags = PPC_INSNS_405, |
| 3003 |
.flags = PPC_FLAGS_405, |
| 3004 |
.msr_mask = 0x00000000020EFF30,
|
| 3005 |
}, |
| 3006 |
#endif
|
| 3007 |
#if defined (TODO)
|
| 3008 |
/* STB25xx */
|
| 3009 |
{
|
| 3010 |
.name = "STB25",
|
| 3011 |
.pvr = CPU_PPC_STB25, |
| 3012 |
.pvr_mask = 0xFFFF0000,
|
| 3013 |
.insns_flags = PPC_INSNS_405, |
| 3014 |
.flags = PPC_FLAGS_405, |
| 3015 |
.msr_mask = 0x00000000020EFF30,
|
| 3016 |
}, |
| 3017 |
#endif
|
| 3018 |
#if defined (TODO)
|
| 3019 |
/* STB130 */
|
| 3020 |
{
|
| 3021 |
.name = "STB130",
|
| 3022 |
.pvr = CPU_PPC_STB130, |
| 3023 |
.pvr_mask = 0xFFFF0000,
|
| 3024 |
.insns_flags = PPC_INSNS_405, |
| 3025 |
.flags = PPC_FLAGS_405, |
| 3026 |
.msr_mask = 0x00000000020EFF30,
|
| 3027 |
}, |
| 3028 |
#endif
|
| 3029 |
/* Xilinx PowerPC 405 cores */
|
| 3030 |
#if defined (TODO)
|
| 3031 |
{
|
| 3032 |
.name = "x2vp4",
|
| 3033 |
.pvr = CPU_PPC_X2VP4, |
| 3034 |
.pvr_mask = 0xFFFF0000,
|
| 3035 |
.insns_flags = PPC_INSNS_405, |
| 3036 |
.flags = PPC_FLAGS_405, |
| 3037 |
.msr_mask = 0x00000000020EFF30,
|
| 3038 |
}, |
| 3039 |
{
|
| 3040 |
.name = "x2vp7",
|
| 3041 |
.pvr = CPU_PPC_X2VP7, |
| 3042 |
.pvr_mask = 0xFFFF0000,
|
| 3043 |
.insns_flags = PPC_INSNS_405, |
| 3044 |
.flags = PPC_FLAGS_405, |
| 3045 |
.msr_mask = 0x00000000020EFF30,
|
| 3046 |
}, |
| 3047 |
{
|
| 3048 |
.name = "x2vp20",
|
| 3049 |
.pvr = CPU_PPC_X2VP20, |
| 3050 |
.pvr_mask = 0xFFFF0000,
|
| 3051 |
.insns_flags = PPC_INSNS_405, |
| 3052 |
.flags = PPC_FLAGS_405, |
| 3053 |
.msr_mask = 0x00000000020EFF30,
|
| 3054 |
}, |
| 3055 |
{
|
| 3056 |
.name = "x2vp50",
|
| 3057 |
.pvr = CPU_PPC_X2VP50, |
| 3058 |
.pvr_mask = 0xFFFF0000,
|
| 3059 |
.insns_flags = PPC_INSNS_405, |
| 3060 |
.flags = PPC_FLAGS_405, |
| 3061 |
.msr_mask = 0x00000000020EFF30,
|
| 3062 |
}, |
| 3063 |
#endif
|
| 3064 |
#if defined (TODO)
|
| 3065 |
/* PowerPC 440 EP */
|
| 3066 |
{
|
| 3067 |
.name = "440ep",
|
| 3068 |
.pvr = CPU_PPC_440EP, |
| 3069 |
.pvr_mask = 0xFFFF0000,
|
| 3070 |
.insns_flags = PPC_INSNS_440, |
| 3071 |
.flags = PPC_FLAGS_440, |
| 3072 |
.msr_mask = 0x000000000006D630,
|
| 3073 |
}, |
| 3074 |
#endif
|
| 3075 |
#if defined (TODO)
|
| 3076 |
/* PowerPC 440 GR */
|
| 3077 |
{
|
| 3078 |
.name = "440gr",
|
| 3079 |
.pvr = CPU_PPC_440GR, |
| 3080 |
.pvr_mask = 0xFFFF0000,
|
| 3081 |
.insns_flags = PPC_INSNS_440, |
| 3082 |
.flags = PPC_FLAGS_440, |
| 3083 |
.msr_mask = 0x000000000006D630,
|
| 3084 |
}, |
| 3085 |
#endif
|
| 3086 |
#if defined (TODO)
|
| 3087 |
/* PowerPC 440 GP */
|
| 3088 |
{
|
| 3089 |
.name = "440gp",
|
| 3090 |
.pvr = CPU_PPC_440GP, |
| 3091 |
.pvr_mask = 0xFFFFFF00,
|
| 3092 |
.insns_flags = PPC_INSNS_440, |
| 3093 |
.flags = PPC_FLAGS_440, |
| 3094 |
.msr_mask = 0x000000000006D630,
|
| 3095 |
}, |
| 3096 |
#endif
|
| 3097 |
#if defined (TODO)
|
| 3098 |
/* PowerPC 440 GX */
|
| 3099 |
{
|
| 3100 |
.name = "440gx",
|
| 3101 |
.pvr = CPU_PPC_440GX, |
| 3102 |
.pvr_mask = 0xFFFF0000,
|
| 3103 |
.insns_flags = PPC_INSNS_405, |
| 3104 |
.flags = PPC_FLAGS_440, |
| 3105 |
.msr_mask = 0x000000000006D630,
|
| 3106 |
}, |
| 3107 |
#endif
|
| 3108 |
#if defined (TODO)
|
| 3109 |
/* PowerPC 440 GXc */
|
| 3110 |
{
|
| 3111 |
.name = "440gxc",
|
| 3112 |
.pvr = CPU_PPC_440GXC, |
| 3113 |
.pvr_mask = 0xFFFF0000,
|
| 3114 |
.insns_flags = PPC_INSNS_405, |
| 3115 |
.flags = PPC_FLAGS_440, |
| 3116 |
.msr_mask = 0x000000000006D630,
|
| 3117 |
}, |
| 3118 |
#endif
|
| 3119 |
#if defined (TODO)
|
| 3120 |
/* PowerPC 440 GXf */
|
| 3121 |
{
|
| 3122 |
.name = "440gxf",
|
| 3123 |
.pvr = CPU_PPC_440GXF, |
| 3124 |
.pvr_mask = 0xFFFF0000,
|
| 3125 |
.insns_flags = PPC_INSNS_405, |
| 3126 |
.flags = PPC_FLAGS_440, |
| 3127 |
.msr_mask = 0x000000000006D630,
|
| 3128 |
}, |
| 3129 |
#endif
|
| 3130 |
#if defined (TODO)
|
| 3131 |
/* PowerPC 440 SP */
|
| 3132 |
{
|
| 3133 |
.name = "440sp",
|
| 3134 |
.pvr = CPU_PPC_440SP, |
| 3135 |
.pvr_mask = 0xFFFF0000,
|
| 3136 |
.insns_flags = PPC_INSNS_405, |
| 3137 |
.flags = PPC_FLAGS_440, |
| 3138 |
.msr_mask = 0x000000000006D630,
|
| 3139 |
}, |
| 3140 |
#endif
|
| 3141 |
#if defined (TODO)
|
| 3142 |
/* PowerPC 440 SP2 */
|
| 3143 |
{
|
| 3144 |
.name = "440sp2",
|
| 3145 |
.pvr = CPU_PPC_440SP2, |
| 3146 |
.pvr_mask = 0xFFFF0000,
|
| 3147 |
.insns_flags = PPC_INSNS_405, |
| 3148 |
.flags = PPC_FLAGS_440, |
| 3149 |
.msr_mask = 0x000000000006D630,
|
| 3150 |
}, |
| 3151 |
#endif
|
| 3152 |
#if defined (TODO)
|
| 3153 |
/* PowerPC 440 SPE */
|
| 3154 |
{
|
| 3155 |
.name = "440spe",
|
| 3156 |
.pvr = CPU_PPC_440SPE, |
| 3157 |
.pvr_mask = 0xFFFF0000,
|
| 3158 |
.insns_flags = PPC_INSNS_405, |
| 3159 |
.flags = PPC_FLAGS_440, |
| 3160 |
.msr_mask = 0x000000000006D630,
|
| 3161 |
}, |
| 3162 |
#endif
|
| 3163 |
/* Fake generic BookE PowerPC */
|
| 3164 |
{
|
| 3165 |
.name = "BookE",
|
| 3166 |
.pvr = CPU_PPC_e500, |
| 3167 |
.pvr_mask = 0xFFFFFFFF,
|
| 3168 |
.insns_flags = PPC_INSNS_BOOKE, |
| 3169 |
.flags = PPC_FLAGS_BOOKE, |
| 3170 |
.msr_mask = 0x000000000006D630,
|
| 3171 |
}, |
| 3172 |
/* PowerPC 460 cores - TODO */
|
| 3173 |
/* PowerPC MPC 5xx cores - TODO */
|
| 3174 |
/* PowerPC MPC 8xx cores - TODO */
|
| 3175 |
/* PowerPC MPC 8xxx cores - TODO */
|
| 3176 |
/* e200 cores - TODO */
|
| 3177 |
/* e500 cores - TODO */
|
| 3178 |
/* e600 cores - TODO */
|
| 3179 |
|
| 3180 |
/* 32 bits "classic" PowerPC */
|
| 3181 |
#if defined (TODO)
|
| 3182 |
/* PowerPC 601 */
|
| 3183 |
{
|
| 3184 |
.name = "601",
|
| 3185 |
.pvr = CPU_PPC_601, |
| 3186 |
.pvr_mask = 0xFFFF0000,
|
| 3187 |
.insns_flags = PPC_INSNS_601, |
| 3188 |
.flags = PPC_FLAGS_601, |
| 3189 |
.msr_mask = 0x000000000000FD70,
|
| 3190 |
}, |
| 3191 |
#endif
|
| 3192 |
#if defined (TODO)
|
| 3193 |
/* PowerPC 602 */
|
| 3194 |
{
|
| 3195 |
.name = "602",
|
| 3196 |
.pvr = CPU_PPC_602, |
| 3197 |
.pvr_mask = 0xFFFF0000,
|
| 3198 |
.insns_flags = PPC_INSNS_602, |
| 3199 |
.flags = PPC_FLAGS_602, |
| 3200 |
.msr_mask = 0x0000000000C7FF73,
|
| 3201 |
}, |
| 3202 |
#endif
|
| 3203 |
/* PowerPC 603 */
|
| 3204 |
{
|
| 3205 |
.name = "603",
|
| 3206 |
.pvr = CPU_PPC_603, |
| 3207 |
.pvr_mask = 0xFFFFFFFF,
|
| 3208 |
.insns_flags = PPC_INSNS_603, |
| 3209 |
.flags = PPC_FLAGS_603, |
| 3210 |
.msr_mask = 0x000000000007FF73,
|
| 3211 |
}, |
| 3212 |
/* PowerPC 603e */
|
| 3213 |
{
|
| 3214 |
.name = "603e",
|
| 3215 |
.pvr = CPU_PPC_603E, |
| 3216 |
.pvr_mask = 0xFFFFFFFF,
|
| 3217 |
.insns_flags = PPC_INSNS_603, |
| 3218 |
.flags = PPC_FLAGS_603, |
| 3219 |
.msr_mask = 0x000000000007FF73,
|
| 3220 |
}, |
| 3221 |
{
|
| 3222 |
.name = "Stretch",
|
| 3223 |
.pvr = CPU_PPC_603E, |
| 3224 |
.pvr_mask = 0xFFFFFFFF,
|
| 3225 |
.insns_flags = PPC_INSNS_603, |
| 3226 |
.flags = PPC_FLAGS_603, |
| 3227 |
.msr_mask = 0x000000000007FF73,
|
| 3228 |
}, |
| 3229 |
/* PowerPC 603p */
|
| 3230 |
{
|
| 3231 |
.name = "603p",
|
| 3232 |
.pvr = CPU_PPC_603P, |
| 3233 |
.pvr_mask = 0xFFFFFFFF,
|
| 3234 |
.insns_flags = PPC_INSNS_603, |
| 3235 |
.flags = PPC_FLAGS_603, |
| 3236 |
.msr_mask = 0x000000000007FF73,
|
| 3237 |
}, |
| 3238 |
/* PowerPC 603e7 */
|
| 3239 |
{
|
| 3240 |
.name = "603e7",
|
| 3241 |
.pvr = CPU_PPC_603E7, |
| 3242 |
.pvr_mask = 0xFFFFFFFF,
|
| 3243 |
.insns_flags = PPC_INSNS_603, |
| 3244 |
.flags = PPC_FLAGS_603, |
| 3245 |
.msr_mask = 0x000000000007FF73,
|
| 3246 |
}, |
| 3247 |
/* PowerPC 603e7v */
|
| 3248 |
{
|
| 3249 |
.name = "603e7v",
|
| 3250 |
.pvr = CPU_PPC_603E7v, |
| 3251 |
.pvr_mask = 0xFFFFFFFF,
|
| 3252 |
.insns_flags = PPC_INSNS_603, |
| 3253 |
.flags = PPC_FLAGS_603, |
| 3254 |
.msr_mask = 0x000000000007FF73,
|
| 3255 |
}, |
| 3256 |
/* PowerPC 603e7v2 */
|
| 3257 |
{
|
| 3258 |
.name = "603e7v2",
|
| 3259 |
.pvr = CPU_PPC_603E7v2, |
| 3260 |
.pvr_mask = 0xFFFFFFFF,
|
| 3261 |
.insns_flags = PPC_INSNS_603, |
| 3262 |
.flags = PPC_FLAGS_603, |
| 3263 |
.msr_mask = 0x000000000007FF73,
|
| 3264 |
}, |
| 3265 |
/* PowerPC 603r */
|
| 3266 |
{
|
| 3267 |
.name = "603r",
|
| 3268 |
.pvr = CPU_PPC_603R, |
| 3269 |
.pvr_mask = 0xFFFFFFFF,
|
| 3270 |
.insns_flags = PPC_INSNS_603, |
| 3271 |
.flags = PPC_FLAGS_603, |
| 3272 |
.msr_mask = 0x000000000007FF73,
|
| 3273 |
}, |
| 3274 |
{
|
| 3275 |
.name = "Goldeneye",
|
| 3276 |
.pvr = CPU_PPC_603R, |
| 3277 |
.pvr_mask = 0xFFFFFFFF,
|
| 3278 |
.insns_flags = PPC_INSNS_603, |
| 3279 |
.flags = PPC_FLAGS_603, |
| 3280 |
.msr_mask = 0x000000000007FF73,
|
| 3281 |
}, |
| 3282 |
#if defined (TODO)
|
| 3283 |
/* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
|
| 3284 |
{
|
| 3285 |
.name = "G2",
|
| 3286 |
.pvr = CPU_PPC_G2, |
| 3287 |
.pvr_mask = 0xFFFF0000,
|
| 3288 |
.insns_flags = PPC_INSNS_G2, |
| 3289 |
.flags = PPC_FLAGS_G2, |
| 3290 |
.msr_mask = 0x000000000006FFF2,
|
| 3291 |
}, |
| 3292 |
{
|
| 3293 |
.name = "G2h4",
|
| 3294 |
.pvr = CPU_PPC_G2H4, |
| 3295 |
.pvr_mask = 0xFFFF0000,
|
| 3296 |
.insns_flags = PPC_INSNS_G2, |
| 3297 |
.flags = PPC_FLAGS_G2, |
| 3298 |
.msr_mask = 0x000000000006FFF2,
|
| 3299 |
}, |
| 3300 |
{
|
| 3301 |
.name = "G2gp",
|
| 3302 |
.pvr = CPU_PPC_G2gp, |
| 3303 |
.pvr_mask = 0xFFFF0000,
|
| 3304 |
.insns_flags = PPC_INSNS_G2, |
| 3305 |
.flags = PPC_FLAGS_G2, |
| 3306 |
.msr_mask = 0x000000000006FFF2,
|
| 3307 |
}, |
| 3308 |
{
|
| 3309 |
.name = "G2ls",
|
| 3310 |
.pvr = CPU_PPC_G2ls, |
| 3311 |
.pvr_mask = 0xFFFF0000,
|
| 3312 |
.insns_flags = PPC_INSNS_G2, |
| 3313 |
.flags = PPC_FLAGS_G2, |
| 3314 |
.msr_mask = 0x000000000006FFF2,
|
| 3315 |
}, |
| 3316 |
{ /* Same as G2, with LE mode support */
|
| 3317 |
.name = "G2le",
|
| 3318 |
.pvr = CPU_PPC_G2LE, |
| 3319 |
.pvr_mask = 0xFFFF0000,
|
| 3320 |
.insns_flags = PPC_INSNS_G2, |
| 3321 |
.flags = PPC_FLAGS_G2, |
| 3322 |
.msr_mask = 0x000000000007FFF3,
|
| 3323 |
}, |
| 3324 |
{
|
| 3325 |
.name = "G2legp",
|
| 3326 |
.pvr = CPU_PPC_G2LEgp, |
| 3327 |
.pvr_mask = 0xFFFF0000,
|
| 3328 |
.insns_flags = PPC_INSNS_G2, |
| 3329 |
.flags = PPC_FLAGS_G2, |
| 3330 |
.msr_mask = 0x000000000007FFF3,
|
| 3331 |
}, |
| 3332 |
{
|
| 3333 |
.name = "G2lels",
|
| 3334 |
.pvr = CPU_PPC_G2LEls, |
| 3335 |
.pvr_mask = 0xFFFF0000,
|
| 3336 |
.insns_flags = PPC_INSNS_G2, |
| 3337 |
.flags = PPC_FLAGS_G2, |
| 3338 |
.msr_mask = 0x000000000007FFF3,
|
| 3339 |
}, |
| 3340 |
#endif
|
| 3341 |
/* PowerPC 604 */
|
| 3342 |
{
|
| 3343 |
.name = "604",
|
| 3344 |
.pvr = CPU_PPC_604, |
| 3345 |
.pvr_mask = 0xFFFFFFFF,
|
| 3346 |
.insns_flags = PPC_INSNS_604, |
| 3347 |
.flags = PPC_FLAGS_604, |
| 3348 |
.msr_mask = 0x000000000005FF77,
|
| 3349 |
}, |
| 3350 |
/* PowerPC 604e */
|
| 3351 |
{
|
| 3352 |
.name = "604e",
|
| 3353 |
.pvr = CPU_PPC_604E, |
| 3354 |
.pvr_mask = 0xFFFFFFFF,
|
| 3355 |
.insns_flags = PPC_INSNS_604, |
| 3356 |
.flags = PPC_FLAGS_604, |
| 3357 |
.msr_mask = 0x000000000005FF77,
|
| 3358 |
}, |
| 3359 |
/* PowerPC 604r */
|
| 3360 |
{
|
| 3361 |
.name = "604r",
|
| 3362 |
.pvr = CPU_PPC_604R, |
| 3363 |
.pvr_mask = 0xFFFFFFFF,
|
| 3364 |
.insns_flags = PPC_INSNS_604, |
| 3365 |
.flags = PPC_FLAGS_604, |
| 3366 |
.msr_mask = 0x000000000005FF77,
|
| 3367 |
}, |
| 3368 |
/* generic G3 */
|
| 3369 |
{
|
| 3370 |
.name = "G3",
|
| 3371 |
.pvr = CPU_PPC_74x, |
| 3372 |
.pvr_mask = 0xFFFFFFFF,
|
| 3373 |
.insns_flags = PPC_INSNS_7x0, |
| 3374 |
.flags = PPC_FLAGS_7x0, |
| 3375 |
.msr_mask = 0x000000000007FF77,
|
| 3376 |
}, |
| 3377 |
/* MPC740 (G3) */
|
| 3378 |
{
|
| 3379 |
.name = "740",
|
| 3380 |
.pvr = CPU_PPC_74x, |
| 3381 |
.pvr_mask = 0xFFFFFFFF,
|
| 3382 |
.insns_flags = PPC_INSNS_7x0, |
| 3383 |
.flags = PPC_FLAGS_7x0, |
| 3384 |
.msr_mask = 0x000000000007FF77,
|
| 3385 |
}, |
| 3386 |
{
|
| 3387 |
.name = "Arthur",
|
| 3388 |
.pvr = CPU_PPC_74x, |
| 3389 |
.pvr_mask = 0xFFFFFFFF,
|
| 3390 |
.insns_flags = PPC_INSNS_7x0, |
| 3391 |
.flags = PPC_FLAGS_7x0, |
| 3392 |
.msr_mask = 0x000000000007FF77,
|
| 3393 |
}, |
| 3394 |
#if defined (TODO)
|
| 3395 |
/* MPC745 (G3) */
|
| 3396 |
{
|
| 3397 |
.name = "745",
|
| 3398 |
.pvr = CPU_PPC_74x, |
| 3399 |
.pvr_mask = 0xFFFFF000,
|
| 3400 |
.insns_flags = PPC_INSNS_7x5, |
| 3401 |
.flags = PPC_FLAGS_7x5, |
| 3402 |
.msr_mask = 0x000000000007FF77,
|
| 3403 |
}, |
| 3404 |
{
|
| 3405 |
.name = "Goldfinger",
|
| 3406 |
.pvr = CPU_PPC_74x, |
| 3407 |
.pvr_mask = 0xFFFFF000,
|
| 3408 |
.insns_flags = PPC_INSNS_7x5, |
| 3409 |
.flags = PPC_FLAGS_7x5, |
| 3410 |
.msr_mask = 0x000000000007FF77,
|
| 3411 |
}, |
| 3412 |
#endif
|
| 3413 |
/* MPC750 (G3) */
|
| 3414 |
{
|
| 3415 |
.name = "750",
|
| 3416 |
.pvr = CPU_PPC_74x, |
| 3417 |
.pvr_mask = 0xFFFFFFFF,
|
| 3418 |
.insns_flags = PPC_INSNS_7x0, |
| 3419 |
.flags = PPC_FLAGS_7x0, |
| 3420 |
.msr_mask = 0x000000000007FF77,
|
| 3421 |
}, |
| 3422 |
#if defined (TODO)
|
| 3423 |
/* MPC755 (G3) */
|
| 3424 |
{
|
| 3425 |
.name = "755",
|
| 3426 |
.pvr = CPU_PPC_755, |
| 3427 |
.pvr_mask = 0xFFFFF000,
|
| 3428 |
.insns_flags = PPC_INSNS_7x5, |
| 3429 |
.flags = PPC_FLAGS_7x5, |
| 3430 |
.msr_mask = 0x000000000007FF77,
|
| 3431 |
}, |
| 3432 |
#endif
|
| 3433 |
/* MPC740P (G3) */
|
| 3434 |
{
|
| 3435 |
.name = "740p",
|
| 3436 |
.pvr = CPU_PPC_74xP, |
| 3437 |
.pvr_mask = 0xFFFFFFFF,
|
| 3438 |
.insns_flags = PPC_INSNS_7x0, |
| 3439 |
.flags = PPC_FLAGS_7x0, |
| 3440 |
.msr_mask = 0x000000000007FF77,
|
| 3441 |
}, |
| 3442 |
{
|
| 3443 |
.name = "Conan/Doyle",
|
| 3444 |
.pvr = CPU_PPC_74xP, |
| 3445 |
.pvr_mask = 0xFFFFFFFF,
|
| 3446 |
.insns_flags = PPC_INSNS_7x0, |
| 3447 |
.flags = PPC_FLAGS_7x0, |
| 3448 |
.msr_mask = 0x000000000007FF77,
|
| 3449 |
}, |
| 3450 |
#if defined (TODO)
|
| 3451 |
/* MPC745P (G3) */
|
| 3452 |
{
|
| 3453 |
.name = "745p",
|
| 3454 |
.pvr = CPU_PPC_74xP, |
| 3455 |
.pvr_mask = 0xFFFFF000,
|
| 3456 |
.insns_flags = PPC_INSNS_7x5, |
| 3457 |
.flags = PPC_FLAGS_7x5, |
| 3458 |
.msr_mask = 0x000000000007FF77,
|
| 3459 |
}, |
| 3460 |
#endif
|
| 3461 |
/* MPC750P (G3) */
|
| 3462 |
{
|
| 3463 |
.name = "750p",
|
| 3464 |
.pvr = CPU_PPC_74xP, |
| 3465 |
.pvr_mask = 0xFFFFFFFF,
|
| 3466 |
.insns_flags = PPC_INSNS_7x0, |
| 3467 |
.flags = PPC_FLAGS_7x0, |
| 3468 |
.msr_mask = 0x000000000007FF77,
|
| 3469 |
}, |
| 3470 |
#if defined (TODO)
|
| 3471 |
/* MPC755P (G3) */
|
| 3472 |
{
|
| 3473 |
.name = "755p",
|
| 3474 |
.pvr = CPU_PPC_74xP, |
| 3475 |
.pvr_mask = 0xFFFFF000,
|
| 3476 |
.insns_flags = PPC_INSNS_7x5, |
| 3477 |
.flags = PPC_FLAGS_7x5, |
| 3478 |
.msr_mask = 0x000000000007FF77,
|
| 3479 |
}, |
| 3480 |
#endif
|
| 3481 |
/* IBM 750CXe (G3 embedded) */
|
| 3482 |
{
|
| 3483 |
.name = "750cxe",
|
| 3484 |
.pvr = CPU_PPC_750CXE, |
| 3485 |
.pvr_mask = 0xFFFFFFFF,
|
| 3486 |
.insns_flags = PPC_INSNS_7x0, |
| 3487 |
.flags = PPC_FLAGS_7x0, |
| 3488 |
.msr_mask = 0x000000000007FF77,
|
| 3489 |
}, |
| 3490 |
/* IBM 750FX (G3 embedded) */
|
| 3491 |
{
|
| 3492 |
.name = "750fx",
|
| 3493 |
.pvr = CPU_PPC_750FX, |
| 3494 |
.pvr_mask = 0xFFFFFFFF,
|
| 3495 |
.insns_flags = PPC_INSNS_7x0, |
| 3496 |
.flags = PPC_FLAGS_7x0, |
| 3497 |
.msr_mask = 0x000000000007FF77,
|
| 3498 |
}, |
| 3499 |
/* IBM 750GX (G3 embedded) */
|
| 3500 |
{
|
| 3501 |
.name = "750gx",
|
| 3502 |
.pvr = CPU_PPC_750GX, |
| 3503 |
.pvr_mask = 0xFFFFFFFF,
|
| 3504 |
.insns_flags = PPC_INSNS_7x0, |
| 3505 |
.flags = PPC_FLAGS_7x0, |
| 3506 |
.msr_mask = 0x000000000007FF77,
|
| 3507 |
}, |
| 3508 |
#if defined (TODO)
|
| 3509 |
/* generic G4 */
|
| 3510 |
{
|
| 3511 |
.name = "G4",
|
| 3512 |
.pvr = CPU_PPC_7400, |
| 3513 |
.pvr_mask = 0xFFFF0000,
|
| 3514 |
.insns_flags = PPC_INSNS_74xx, |
| 3515 |
.flags = PPC_FLAGS_74xx, |
| 3516 |
.msr_mask = 0x000000000205FF77,
|
| 3517 |
}, |
| 3518 |
#endif
|
| 3519 |
#if defined (TODO)
|
| 3520 |
/* PowerPC 7400 (G4) */
|
| 3521 |
{
|
| 3522 |
.name = "7400",
|
| 3523 |
.pvr = CPU_PPC_7400, |
| 3524 |
.pvr_mask = 0xFFFF0000,
|
| 3525 |
.insns_flags = PPC_INSNS_74xx, |
| 3526 |
.flags = PPC_FLAGS_74xx, |
| 3527 |
.msr_mask = 0x000000000205FF77,
|
| 3528 |
}, |
| 3529 |
{
|
| 3530 |
.name = "Max",
|
| 3531 |
.pvr = CPU_PPC_7400, |
| 3532 |
.pvr_mask = 0xFFFF0000,
|
| 3533 |
.insns_flags = PPC_INSNS_74xx, |
| 3534 |
.flags = PPC_FLAGS_74xx, |
| 3535 |
.msr_mask = 0x000000000205FF77,
|
| 3536 |
}, |
| 3537 |
#endif
|
| 3538 |
#if defined (TODO)
|
| 3539 |
/* PowerPC 7410 (G4) */
|
| 3540 |
{
|
| 3541 |
.name = "7410",
|
| 3542 |
.pvr = CPU_PPC_7410, |
| 3543 |
.pvr_mask = 0xFFFF0000,
|
| 3544 |
.insns_flags = PPC_INSNS_74xx, |
| 3545 |
.flags = PPC_FLAGS_74xx, |
| 3546 |
.msr_mask = 0x000000000205FF77,
|
| 3547 |
}, |
| 3548 |
{
|
| 3549 |
.name = "Nitro",
|
| 3550 |
.pvr = CPU_PPC_7410, |
| 3551 |
.pvr_mask = 0xFFFF0000,
|
| 3552 |
.insns_flags = PPC_INSNS_74xx, |
| 3553 |
.flags = PPC_FLAGS_74xx, |
| 3554 |
.msr_mask = 0x000000000205FF77,
|
| 3555 |
}, |
| 3556 |
#endif
|
| 3557 |
/* XXX: 7441 */
|
| 3558 |
/* XXX: 7445 */
|
| 3559 |
/* XXX: 7447 */
|
| 3560 |
/* XXX: 7447A */
|
| 3561 |
#if defined (TODO)
|
| 3562 |
/* PowerPC 7450 (G4) */
|
| 3563 |
{
|
| 3564 |
.name = "7450",
|
| 3565 |
.pvr = CPU_PPC_7450, |
| 3566 |
.pvr_mask = 0xFFFF0000,
|
| 3567 |
.insns_flags = PPC_INSNS_74xx, |
| 3568 |
.flags = PPC_FLAGS_74xx, |
| 3569 |
.msr_mask = 0x000000000205FF77,
|
| 3570 |
}, |
| 3571 |
{
|
| 3572 |
.name = "Vger",
|
| 3573 |
.pvr = CPU_PPC_7450, |
| 3574 |
.pvr_mask = 0xFFFF0000,
|
| 3575 |
.insns_flags = PPC_INSNS_74xx, |
| 3576 |
.flags = PPC_FLAGS_74xx, |
| 3577 |
.msr_mask = 0x000000000205FF77,
|
| 3578 |
}, |
| 3579 |
#endif
|
| 3580 |
/* XXX: 7451 */
|
| 3581 |
#if defined (TODO)
|
| 3582 |
/* PowerPC 7455 (G4) */
|
| 3583 |
{
|
| 3584 |
.name = "7455",
|
| 3585 |
.pvr = CPU_PPC_7455, |
| 3586 |
.pvr_mask = 0xFFFF0000,
|
| 3587 |
.insns_flags = PPC_INSNS_74xx, |
| 3588 |
.flags = PPC_FLAGS_74xx, |
| 3589 |
.msr_mask = 0x000000000205FF77,
|
| 3590 |
}, |
| 3591 |
{
|
| 3592 |
.name = "Apollo 6",
|
| 3593 |
.pvr = CPU_PPC_7455, |
| 3594 |
.pvr_mask = 0xFFFF0000,
|
| 3595 |
.insns_flags = PPC_INSNS_74xx, |
| 3596 |
.flags = PPC_FLAGS_74xx, |
| 3597 |
.msr_mask = 0x000000000205FF77,
|
| 3598 |
}, |
| 3599 |
#endif
|
| 3600 |
#if defined (TODO)
|
| 3601 |
/* PowerPC 7457 (G4) */
|
| 3602 |
{
|
| 3603 |
.name = "7457",
|
| 3604 |
.pvr = CPU_PPC_7457, |
| 3605 |
.pvr_mask = 0xFFFF0000,
|
| 3606 |
.insns_flags = PPC_INSNS_74xx, |
| 3607 |
.flags = PPC_FLAGS_74xx, |
| 3608 |
.msr_mask = 0x000000000205FF77,
|
| 3609 |
}, |
| 3610 |
{
|
| 3611 |
.name = "Apollo 7",
|
| 3612 |
.pvr = CPU_PPC_7457, |
| 3613 |
.pvr_mask = 0xFFFF0000,
|
| 3614 |
.insns_flags = PPC_INSNS_74xx, |
| 3615 |
.flags = PPC_FLAGS_74xx, |
| 3616 |
.msr_mask = 0x000000000205FF77,
|
| 3617 |
}, |
| 3618 |
#endif
|
| 3619 |
#if defined (TODO)
|
| 3620 |
/* PowerPC 7457A (G4) */
|
| 3621 |
{
|
| 3622 |
.name = "7457A",
|
| 3623 |
.pvr = CPU_PPC_7457A, |
| 3624 |
.pvr_mask = 0xFFFF0000,
|
| 3625 |
.insns_flags = PPC_INSNS_74xx, |
| 3626 |
.flags = PPC_FLAGS_74xx, |
| 3627 |
.msr_mask = 0x000000000205FF77,
|
| 3628 |
}, |
| 3629 |
{
|
| 3630 |
.name = "Apollo 7 PM",
|
| 3631 |
.pvr = CPU_PPC_7457A, |
| 3632 |
.pvr_mask = 0xFFFF0000,
|
| 3633 |
.insns_flags = PPC_INSNS_74xx, |
| 3634 |
.flags = PPC_FLAGS_74xx, |
| 3635 |
.msr_mask = 0x000000000205FF77,
|
| 3636 |
}, |
| 3637 |
#endif
|
| 3638 |
/* 64 bits PowerPC */
|
| 3639 |
#if defined (TARGET_PPC64)
|
| 3640 |
#if defined (TODO)
|
| 3641 |
/* PowerPC 620 */
|
| 3642 |
{
|
| 3643 |
.name = "620",
|
| 3644 |
.pvr = CPU_PPC_620, |
| 3645 |
.pvr_mask = 0xFFFF0000,
|
| 3646 |
.insns_flags = PPC_INSNS_620, |
| 3647 |
.flags = PPC_FLAGS_620, |
| 3648 |
.msr_mask = 0x800000000005FF73,
|
| 3649 |
}, |
| 3650 |
#endif
|
| 3651 |
#if defined (TODO)
|
| 3652 |
/* PowerPC 630 (POWER3) */
|
| 3653 |
{
|
| 3654 |
.name = "630",
|
| 3655 |
.pvr = CPU_PPC_630, |
| 3656 |
.pvr_mask = 0xFFFF0000,
|
| 3657 |
.insns_flags = PPC_INSNS_630, |
| 3658 |
.flags = PPC_FLAGS_630, |
| 3659 |
.msr_mask = xxx, |
| 3660 |
} |
| 3661 |
{
|
| 3662 |
.name = "POWER3",
|
| 3663 |
.pvr = CPU_PPC_630, |
| 3664 |
.pvr_mask = 0xFFFF0000,
|
| 3665 |
.insns_flags = PPC_INSNS_630, |
| 3666 |
.flags = PPC_FLAGS_630, |
| 3667 |
.msr_mask = xxx, |
| 3668 |
} |
| 3669 |
#endif
|
| 3670 |
#if defined (TODO)
|
| 3671 |
/* PowerPC 631 (Power 3+)*/
|
| 3672 |
{
|
| 3673 |
.name = "631",
|
| 3674 |
.pvr = CPU_PPC_631, |
| 3675 |
.pvr_mask = 0xFFFF0000,
|
| 3676 |
.insns_flags = PPC_INSNS_631, |
| 3677 |
.flags = PPC_FLAGS_631, |
| 3678 |
.msr_mask = xxx, |
| 3679 |
}, |
| 3680 |
{
|
| 3681 |
.name = "POWER3+",
|
| 3682 |
.pvr = CPU_PPC_631, |
| 3683 |
.pvr_mask = 0xFFFF0000,
|
| 3684 |
.insns_flags = PPC_INSNS_631, |
| 3685 |
.flags = PPC_FLAGS_631, |
| 3686 |
.msr_mask = xxx, |
| 3687 |
}, |
| 3688 |
#endif
|
| 3689 |
#if defined (TODO)
|
| 3690 |
/* POWER4 */
|
| 3691 |
{
|
| 3692 |
.name = "POWER4",
|
| 3693 |
.pvr = CPU_PPC_POWER4, |
| 3694 |
.pvr_mask = 0xFFFF0000,
|
| 3695 |
.insns_flags = PPC_INSNS_POWER4, |
| 3696 |
.flags = PPC_FLAGS_POWER4, |
| 3697 |
.msr_mask = xxx, |
| 3698 |
}, |
| 3699 |
#endif
|
| 3700 |
#if defined (TODO)
|
| 3701 |
/* POWER4p */
|
| 3702 |
{
|
| 3703 |
.name = "POWER4+",
|
| 3704 |
.pvr = CPU_PPC_POWER4P, |
| 3705 |
.pvr_mask = 0xFFFF0000,
|
| 3706 |
.insns_flags = PPC_INSNS_POWER4, |
| 3707 |
.flags = PPC_FLAGS_POWER4, |
| 3708 |
.msr_mask = xxx, |
| 3709 |
}, |
| 3710 |
#endif
|
| 3711 |
#if defined (TODO)
|
| 3712 |
/* POWER5 */
|
| 3713 |
{
|
| 3714 |
.name = "POWER5",
|
| 3715 |
.pvr = CPU_PPC_POWER5, |
| 3716 |
.pvr_mask = 0xFFFF0000,
|
| 3717 |
.insns_flags = PPC_INSNS_POWER5, |
| 3718 |
.flags = PPC_FLAGS_POWER5, |
| 3719 |
.msr_mask = xxx, |
| 3720 |
}, |
| 3721 |
#endif
|
| 3722 |
#if defined (TODO)
|
| 3723 |
/* POWER5+ */
|
| 3724 |
{
|
| 3725 |
.name = "POWER5+",
|
| 3726 |
.pvr = CPU_PPC_POWER5P, |
| 3727 |
.pvr_mask = 0xFFFF0000,
|
| 3728 |
.insns_flags = PPC_INSNS_POWER5, |
| 3729 |
.flags = PPC_FLAGS_POWER5, |
| 3730 |
.msr_mask = xxx, |
| 3731 |
}, |
| 3732 |
#endif
|
| 3733 |
#if defined (TODO)
|
| 3734 |
/* PowerPC 970 */
|
| 3735 |
{
|
| 3736 |
.name = "970",
|
| 3737 |
.pvr = CPU_PPC_970, |
| 3738 |
.pvr_mask = 0xFFFF0000,
|
| 3739 |
.insns_flags = PPC_INSNS_970, |
| 3740 |
.flags = PPC_FLAGS_970, |
| 3741 |
.msr_mask = 0x900000000204FF36,
|
| 3742 |
}, |
| 3743 |
#endif
|
| 3744 |
#if defined (TODO)
|
| 3745 |
/* PowerPC 970FX (G5) */
|
| 3746 |
{
|
| 3747 |
.name = "970fx",
|
| 3748 |
.pvr = CPU_PPC_970FX, |
| 3749 |
.pvr_mask = 0xFFFF0000,
|
| 3750 |
.insns_flags = PPC_INSNS_970FX, |
| 3751 |
.flags = PPC_FLAGS_970FX, |
| 3752 |
.msr_mask = 0x800000000204FF36,
|
| 3753 |
}, |
| 3754 |
#endif
|
| 3755 |
#if defined (TODO)
|
| 3756 |
/* RS64 (Apache/A35) */
|
| 3757 |
/* This one seems to support the whole POWER2 instruction set
|
| 3758 |
* and the PowerPC 64 one.
|
| 3759 |
*/
|
| 3760 |
{
|
| 3761 |
.name = "RS64",
|
| 3762 |
.pvr = CPU_PPC_RS64, |
| 3763 |
.pvr_mask = 0xFFFF0000,
|
| 3764 |
.insns_flags = PPC_INSNS_RS64, |
| 3765 |
.flags = PPC_FLAGS_RS64, |
| 3766 |
.msr_mask = xxx, |
| 3767 |
}, |
| 3768 |
{
|
| 3769 |
.name = "Apache",
|
| 3770 |
.pvr = CPU_PPC_RS64, |
| 3771 |
.pvr_mask = 0xFFFF0000,
|
| 3772 |
.insns_flags = PPC_INSNS_RS64, |
| 3773 |
.flags = PPC_FLAGS_RS64, |
| 3774 |
.msr_mask = xxx, |
| 3775 |
}, |
| 3776 |
{
|
| 3777 |
.name = "A35",
|
| 3778 |
.pvr = CPU_PPC_RS64, |
| 3779 |
.pvr_mask = 0xFFFF0000,
|
| 3780 |
.insns_flags = PPC_INSNS_RS64, |
| 3781 |
.flags = PPC_FLAGS_RS64, |
| 3782 |
.msr_mask = xxx, |
| 3783 |
}, |
| 3784 |
#endif
|
| 3785 |
#if defined (TODO)
|
| 3786 |
/* RS64-II (NorthStar/A50) */
|
| 3787 |
{
|
| 3788 |
.name = "RS64-II",
|
| 3789 |
.pvr = CPU_PPC_RS64II, |
| 3790 |
.pvr_mask = 0xFFFF0000,
|
| 3791 |
.insns_flags = PPC_INSNS_RS64, |
| 3792 |
.flags = PPC_FLAGS_RS64, |
| 3793 |
.msr_mask = xxx, |
| 3794 |
}, |
| 3795 |
{
|
| 3796 |
.name = "NortStar",
|
| 3797 |
.pvr = CPU_PPC_RS64II, |
| 3798 |
.pvr_mask = 0xFFFF0000,
|
| 3799 |
.insns_flags = PPC_INSNS_RS64, |
| 3800 |
.flags = PPC_FLAGS_RS64, |
| 3801 |
.msr_mask = xxx, |
| 3802 |
}, |
| 3803 |
{
|
| 3804 |
.name = "A50",
|
| 3805 |
.pvr = CPU_PPC_RS64II, |
| 3806 |
.pvr_mask = 0xFFFF0000,
|
| 3807 |
.insns_flags = PPC_INSNS_RS64, |
| 3808 |
.flags = PPC_FLAGS_RS64, |
| 3809 |
.msr_mask = xxx, |
| 3810 |
}, |
| 3811 |
#endif
|
| 3812 |
#if defined (TODO)
|
| 3813 |
/* RS64-III (Pulsar) */
|
| 3814 |
{
|
| 3815 |
.name = "RS64-III",
|
| 3816 |
.pvr = CPU_PPC_RS64III, |
| 3817 |
.pvr_mask = 0xFFFF0000,
|
| 3818 |
.insns_flags = PPC_INSNS_RS64, |
| 3819 |
.flags = PPC_FLAGS_RS64, |
| 3820 |
.msr_mask = xxx, |
| 3821 |
}, |
| 3822 |
{
|
| 3823 |
.name = "Pulsar",
|
| 3824 |
.pvr = CPU_PPC_RS64III, |
| 3825 |
.pvr_mask = 0xFFFF0000,
|
| 3826 |
.insns_flags = PPC_INSNS_RS64, |
| 3827 |
.flags = PPC_FLAGS_RS64, |
| 3828 |
.msr_mask = xxx, |
| 3829 |
}, |
| 3830 |
#endif
|
| 3831 |
#if defined (TODO)
|
| 3832 |
/* RS64-IV (IceStar/IStar/SStar) */
|
| 3833 |
{
|
| 3834 |
.name = "RS64-IV",
|
| 3835 |
.pvr = CPU_PPC_RS64IV, |
| 3836 |
.pvr_mask = 0xFFFF0000,
|
| 3837 |
.insns_flags = PPC_INSNS_RS64, |
| 3838 |
.flags = PPC_FLAGS_RS64, |
| 3839 |
.msr_mask = xxx, |
| 3840 |
}, |
| 3841 |
{
|
| 3842 |
.name = "IceStar",
|
| 3843 |
.pvr = CPU_PPC_RS64IV, |
| 3844 |
.pvr_mask = 0xFFFF0000,
|
| 3845 |
.insns_flags = PPC_INSNS_RS64, |
| 3846 |
.flags = PPC_FLAGS_RS64, |
| 3847 |
.msr_mask = xxx, |
| 3848 |
}, |
| 3849 |
{
|
| 3850 |
.name = "IStar",
|
| 3851 |
.pvr = CPU_PPC_RS64IV, |
| 3852 |
.pvr_mask = 0xFFFF0000,
|
| 3853 |
.insns_flags = PPC_INSNS_RS64, |
| 3854 |
.flags = PPC_FLAGS_RS64, |
| 3855 |
.msr_mask = xxx, |
| 3856 |
}, |
| 3857 |
{
|
| 3858 |
.name = "SStar",
|
| 3859 |
.pvr = CPU_PPC_RS64IV, |
| 3860 |
.pvr_mask = 0xFFFF0000,
|
| 3861 |
.insns_flags = PPC_INSNS_RS64, |
| 3862 |
.flags = PPC_FLAGS_RS64, |
| 3863 |
.msr_mask = xxx, |
| 3864 |
}, |
| 3865 |
#endif
|
| 3866 |
/* POWER */
|
| 3867 |
#if defined (TODO)
|
| 3868 |
/* Original POWER */
|
| 3869 |
{
|
| 3870 |
.name = "POWER",
|
| 3871 |
.pvr = CPU_POWER, |
| 3872 |
.pvr_mask = 0xFFFF0000,
|
| 3873 |
.insns_flags = PPC_INSNS_POWER, |
| 3874 |
.flags = PPC_FLAGS_POWER, |
| 3875 |
.msr_mask = xxx, |
| 3876 |
}, |
| 3877 |
#endif
|
| 3878 |
#endif /* defined (TARGET_PPC64) */ |
| 3879 |
#if defined (TODO)
|
| 3880 |
/* POWER2 */
|
| 3881 |
{
|
| 3882 |
.name = "POWER2",
|
| 3883 |
.pvr = CPU_POWER2, |
| 3884 |
.pvr_mask = 0xFFFF0000,
|
| 3885 |
.insns_flags = PPC_INSNS_POWER, |
| 3886 |
.flags = PPC_FLAGS_POWER, |
| 3887 |
.msr_mask = xxx, |
| 3888 |
}, |
| 3889 |
#endif
|
| 3890 |
/* Generic PowerPCs */
|
| 3891 |
#if defined (TODO)
|
| 3892 |
{
|
| 3893 |
.name = "ppc64",
|
| 3894 |
.pvr = CPU_PPC_970, |
| 3895 |
.pvr_mask = 0xFFFF0000,
|
| 3896 |
.insns_flags = PPC_INSNS_PPC64, |
| 3897 |
.flags = PPC_FLAGS_PPC64, |
| 3898 |
.msr_mask = 0xA00000000204FF36,
|
| 3899 |
}, |
| 3900 |
#endif
|
| 3901 |
{
|
| 3902 |
.name = "ppc32",
|
| 3903 |
.pvr = CPU_PPC_604, |
| 3904 |
.pvr_mask = 0xFFFFFFFF,
|
| 3905 |
.insns_flags = PPC_INSNS_PPC32, |
| 3906 |
.flags = PPC_FLAGS_PPC32, |
| 3907 |
.msr_mask = 0x000000000005FF77,
|
| 3908 |
}, |
| 3909 |
/* Fallback */
|
| 3910 |
{
|
| 3911 |
.name = "ppc",
|
| 3912 |
.pvr = CPU_PPC_604, |
| 3913 |
.pvr_mask = 0xFFFFFFFF,
|
| 3914 |
.insns_flags = PPC_INSNS_PPC32, |
| 3915 |
.flags = PPC_FLAGS_PPC32, |
| 3916 |
.msr_mask = 0x000000000005FF77,
|
| 3917 |
}, |
| 3918 |
}; |
| 3919 |
|
| 3920 |
int ppc_find_by_name (const unsigned char *name, ppc_def_t **def) |
| 3921 |
{
|
| 3922 |
int i, ret;
|
| 3923 |
|
| 3924 |
ret = -1;
|
| 3925 |
*def = NULL;
|
| 3926 |
for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) { |
| 3927 |
if (strcasecmp(name, ppc_defs[i].name) == 0) { |
| 3928 |
*def = &ppc_defs[i]; |
| 3929 |
ret = 0;
|
| 3930 |
break;
|
| 3931 |
} |
| 3932 |
} |
| 3933 |
|
| 3934 |
return ret;
|
| 3935 |
} |
| 3936 |
|
| 3937 |
int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
|
| 3938 |
{
|
| 3939 |
int i, ret;
|
| 3940 |
|
| 3941 |
ret = -1;
|
| 3942 |
*def = NULL;
|
| 3943 |
for (i = 0; ppc_defs[i].name != NULL; i++) { |
| 3944 |
if ((pvr & ppc_defs[i].pvr_mask) ==
|
| 3945 |
(ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
|
| 3946 |
*def = &ppc_defs[i]; |
| 3947 |
ret = 0;
|
| 3948 |
break;
|
| 3949 |
} |
| 3950 |
} |
| 3951 |
|
| 3952 |
return ret;
|
| 3953 |
} |
| 3954 |
|
| 3955 |
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
| 3956 |
{
|
| 3957 |
int i;
|
| 3958 |
|
| 3959 |
for (i = 0; ; i++) { |
| 3960 |
(*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n",
|
| 3961 |
ppc_defs[i].name, |
| 3962 |
ppc_defs[i].pvr, ppc_defs[i].pvr_mask); |
| 3963 |
if (strcmp(ppc_defs[i].name, "ppc") == 0) |
| 3964 |
break;
|
| 3965 |
} |
| 3966 |
} |