Revision d0f7453d

b/Makefile.target
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obj-mips-y += g364fb.o jazz_led.o
222 222
obj-mips-y += gt64xxx.o mc146818rtc.o
223 223
obj-mips-y += piix4.o cirrus_vga.o
224
obj-mips-$(CONFIG_FULONG) += bonito.o
224 225

  
225 226
obj-microblaze-y = petalogix_s3adsp1800_mmu.o
226 227

  
b/default-configs/mips64el-softmmu.mak
29 29
CONFIG_DS1225Y=y
30 30
CONFIG_MIPSNET=y
31 31
CONFIG_PFLASH_CFI01=y
32
CONFIG_FULONG=y
b/hw/bonito.c
1
/*
2
 * bonito north bridge support
3
 *
4
 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5
 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
6
 *
7
 * This code is licensed under the GNU GPL v2.
8
 */
9

  
10
/*
11
 * fulong 2e mini pc has a bonito north bridge.
12
 */
13

  
14
/* what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
15
 *
16
 * devfn   pci_slot<<3  + funno
17
 * one pci bus can have 32 devices and each device can have 8 functions.
18
 *
19
 * In bonito north bridge, pci slot = IDSEL bit - 12.
20
 * For example, PCI_IDSEL_VIA686B = 17,
21
 * pci slot = 17-12=5
22
 *
23
 * so
24
 * VT686B_FUN0's devfn = (5<<3)+0
25
 * VT686B_FUN1's devfn = (5<<3)+1
26
 *
27
 * qemu also uses pci address for north bridge to access pci config register.
28
 * bus_no   [23:16]
29
 * dev_no   [15:11]
30
 * fun_no   [10:8]
31
 * reg_no   [7:2]
32
 *
33
 * so function bonito_sbridge_pciaddr for the translation from
34
 * north bridge address to pci address.
35
 */
36

  
37
#include <assert.h>
38

  
39
#include "hw.h"
40
#include "pci.h"
41
#include "pc.h"
42
#include "mips.h"
43
#include "pci_host.h"
44
#include "sysemu.h"
45

  
46
//#define DEBUG_BONITO
47

  
48
#ifdef DEBUG_BONITO
49
#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
50
#else
51
#define DPRINTF(fmt, ...)
52
#endif
53

  
54
/* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
55
#define BONITO_BOOT_BASE        0x1fc00000
56
#define BONITO_BOOT_SIZE        0x00100000
57
#define BONITO_BOOT_TOP         (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
58
#define BONITO_FLASH_BASE       0x1c000000
59
#define BONITO_FLASH_SIZE       0x03000000
60
#define BONITO_FLASH_TOP        (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
61
#define BONITO_SOCKET_BASE      0x1f800000
62
#define BONITO_SOCKET_SIZE      0x00400000
63
#define BONITO_SOCKET_TOP       (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
64
#define BONITO_REG_BASE         0x1fe00000
65
#define BONITO_REG_SIZE         0x00040000
66
#define BONITO_REG_TOP          (BONITO_REG_BASE+BONITO_REG_SIZE-1)
67
#define BONITO_DEV_BASE         0x1ff00000
68
#define BONITO_DEV_SIZE         0x00100000
69
#define BONITO_DEV_TOP          (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
70
#define BONITO_PCILO_BASE       0x10000000
71
#define BONITO_PCILO_BASE_VA    0xb0000000
72
#define BONITO_PCILO_SIZE       0x0c000000
73
#define BONITO_PCILO_TOP        (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
74
#define BONITO_PCILO0_BASE      0x10000000
75
#define BONITO_PCILO1_BASE      0x14000000
76
#define BONITO_PCILO2_BASE      0x18000000
77
#define BONITO_PCIHI_BASE       0x20000000
78
#define BONITO_PCIHI_SIZE       0x20000000
79
#define BONITO_PCIHI_TOP        (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
80
#define BONITO_PCIIO_BASE       0x1fd00000
81
#define BONITO_PCIIO_BASE_VA    0xbfd00000
82
#define BONITO_PCIIO_SIZE       0x00010000
83
#define BONITO_PCIIO_TOP        (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
84
#define BONITO_PCICFG_BASE      0x1fe80000
85
#define BONITO_PCICFG_SIZE      0x00080000
86
#define BONITO_PCICFG_TOP       (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
87

  
88

  
89
#define BONITO_PCICONFIGBASE    0x00
90
#define BONITO_REGBASE          0x100
91

  
92
#define BONITO_PCICONFIG_BASE   (BONITO_PCICONFIGBASE+BONITO_REG_BASE)
93
#define BONITO_PCICONFIG_SIZE   (0x100)
94

  
95
#define BONITO_INTERNAL_REG_BASE  (BONITO_REGBASE+BONITO_REG_BASE)
96
#define BONITO_INTERNAL_REG_SIZE  (0x70)
97

  
98
#define BONITO_SPCICONFIG_BASE  (BONITO_PCICFG_BASE)
99
#define BONITO_SPCICONFIG_SIZE  (BONITO_PCICFG_SIZE)
100

  
101

  
102

  
103
/* 1. Bonito h/w Configuration */
104
/* Power on register */
105

  
106
#define BONITO_BONPONCFG        (0x00 >> 2)      /* 0x100 */
107
#define BONITO_BONGENCFG_OFFSET 0x4
108
#define BONITO_BONGENCFG        (BONITO_BONGENCFG_OFFSET>>2)   /*0x104 */
109

  
110
/* 2. IO & IDE configuration */
111
#define BONITO_IODEVCFG         (0x08 >> 2)      /* 0x108 */
112

  
113
/* 3. IO & IDE configuration */
114
#define BONITO_SDCFG            (0x0c >> 2)      /* 0x10c */
115

  
116
/* 4. PCI address map control */
117
#define BONITO_PCIMAP           (0x10 >> 2)      /* 0x110 */
118
#define BONITO_PCIMEMBASECFG    (0x14 >> 2)      /* 0x114 */
119
#define BONITO_PCIMAP_CFG       (0x18 >> 2)      /* 0x118 */
120

  
121
/* 5. ICU & GPIO regs */
122
/* GPIO Regs - r/w */
123
#define BONITO_GPIODATA_OFFSET  0x1c
124
#define BONITO_GPIODATA         (BONITO_GPIODATA_OFFSET >> 2)   /* 0x11c */
125
#define BONITO_GPIOIE           (0x20 >> 2)      /* 0x120 */
126

  
127
/* ICU Configuration Regs - r/w */
128
#define BONITO_INTEDGE          (0x24 >> 2)      /* 0x124 */
129
#define BONITO_INTSTEER         (0x28 >> 2)      /* 0x128 */
130
#define BONITO_INTPOL           (0x2c >> 2)      /* 0x12c */
131

  
132
/* ICU Enable Regs - IntEn & IntISR are r/o. */
133
#define BONITO_INTENSET         (0x30 >> 2)      /* 0x130 */
134
#define BONITO_INTENCLR         (0x34 >> 2)      /* 0x134 */
135
#define BONITO_INTEN            (0x38 >> 2)      /* 0x138 */
136
#define BONITO_INTISR           (0x3c >> 2)      /* 0x13c */
137

  
138
/* PCI mail boxes */
139
#define BONITO_PCIMAIL0_OFFSET    0x40
140
#define BONITO_PCIMAIL1_OFFSET    0x44
141
#define BONITO_PCIMAIL2_OFFSET    0x48
142
#define BONITO_PCIMAIL3_OFFSET    0x4c
143
#define BONITO_PCIMAIL0         (0x40 >> 2)      /* 0x140 */
144
#define BONITO_PCIMAIL1         (0x44 >> 2)      /* 0x144 */
145
#define BONITO_PCIMAIL2         (0x48 >> 2)      /* 0x148 */
146
#define BONITO_PCIMAIL3         (0x4c >> 2)      /* 0x14c */
147

  
148
/* 6. PCI cache */
149
#define BONITO_PCICACHECTRL     (0x50 >> 2)      /* 0x150 */
150
#define BONITO_PCICACHETAG      (0x54 >> 2)      /* 0x154 */
151
#define BONITO_PCIBADADDR       (0x58 >> 2)      /* 0x158 */
152
#define BONITO_PCIMSTAT         (0x5c >> 2)      /* 0x15c */
153

  
154
/* 7. other*/
155
#define BONITO_TIMECFG          (0x60 >> 2)      /* 0x160 */
156
#define BONITO_CPUCFG           (0x64 >> 2)      /* 0x164 */
157
#define BONITO_DQCFG            (0x68 >> 2)      /* 0x168 */
158
#define BONITO_MEMSIZE          (0x6C >> 2)      /* 0x16c */
159

  
160
#define BONITO_REGS             (0x70 >> 2)
161

  
162
/* PCI config for south bridge. type 0 */
163
#define BONITO_PCICONF_IDSEL_MASK      0xfffff800     /* [31:11] */
164
#define BONITO_PCICONF_IDSEL_OFFSET    11
165
#define BONITO_PCICONF_FUN_MASK        0x700    /* [10:8] */
166
#define BONITO_PCICONF_FUN_OFFSET      8
167
#define BONITO_PCICONF_REG_MASK        0xFC
168
#define BONITO_PCICONF_REG_OFFSET      0
169

  
170

  
171
/* idsel BIT = pci slot number +12 */
172
#define PCI_SLOT_BASE              12
173
#define PCI_IDSEL_VIA686B_BIT      (17)
174
#define PCI_IDSEL_VIA686B          (1<<PCI_IDSEL_VIA686B_BIT)
175

  
176
#define PCI_ADDR(busno,devno,funno,regno)  \
177
    ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno))
178

  
179
typedef PCIHostState BonitoState;
180

  
181
typedef struct PCIBonitoState
182
{
183
    PCIDevice dev;
184
    BonitoState *pcihost;
185
    uint32_t regs[BONITO_REGS];
186

  
187
    struct bonldma {
188
        uint32_t ldmactrl;
189
        uint32_t ldmastat;
190
        uint32_t ldmaaddr;
191
        uint32_t ldmago;
192
    } bonldma;
193

  
194
    /* Based at 1fe00300, bonito Copier */
195
    struct boncop {
196
        uint32_t copctrl;
197
        uint32_t copstat;
198
        uint32_t coppaddr;
199
        uint32_t copgo;
200
    } boncop;
201

  
202
    /* Bonito registers */
203
    target_phys_addr_t bonito_reg_start;
204
    target_phys_addr_t bonito_reg_length;
205
    int bonito_reg_handle;
206

  
207
    target_phys_addr_t bonito_pciconf_start;
208
    target_phys_addr_t bonito_pciconf_length;
209
    int bonito_pciconf_handle;
210

  
211
    target_phys_addr_t bonito_spciconf_start;
212
    target_phys_addr_t bonito_spciconf_length;
213
    int bonito_spciconf_handle;
214

  
215
    target_phys_addr_t bonito_pciio_start;
216
    target_phys_addr_t bonito_pciio_length;
217
    int bonito_pciio_handle;
218

  
219
    target_phys_addr_t bonito_localio_start;
220
    target_phys_addr_t bonito_localio_length;
221
    int bonito_localio_handle;
222

  
223
    target_phys_addr_t bonito_ldma_start;
224
    target_phys_addr_t bonito_ldma_length;
225
    int bonito_ldma_handle;
226

  
227
    target_phys_addr_t bonito_cop_start;
228
    target_phys_addr_t bonito_cop_length;
229
    int bonito_cop_handle;
230

  
231
} PCIBonitoState;
232

  
233
PCIBonitoState * bonito_state;
234

  
235
static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
236
{
237
    PCIBonitoState *s = opaque;
238
    uint32_t saddr;
239
    int reset = 0;
240

  
241
    saddr = (addr - BONITO_REGBASE) >> 2;
242

  
243
    DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x \n", addr, val, saddr);
244
    switch (saddr) {
245
    case BONITO_BONPONCFG:
246
    case BONITO_IODEVCFG:
247
    case BONITO_SDCFG:
248
    case BONITO_PCIMAP:
249
    case BONITO_PCIMEMBASECFG:
250
    case BONITO_PCIMAP_CFG:
251
    case BONITO_GPIODATA:
252
    case BONITO_GPIOIE:
253
    case BONITO_INTEDGE:
254
    case BONITO_INTSTEER:
255
    case BONITO_INTPOL:
256
    case BONITO_PCIMAIL0:
257
    case BONITO_PCIMAIL1:
258
    case BONITO_PCIMAIL2:
259
    case BONITO_PCIMAIL3:
260
    case BONITO_PCICACHECTRL:
261
    case BONITO_PCICACHETAG:
262
    case BONITO_PCIBADADDR:
263
    case BONITO_PCIMSTAT:
264
    case BONITO_TIMECFG:
265
    case BONITO_CPUCFG:
266
    case BONITO_DQCFG:
267
    case BONITO_MEMSIZE:
268
        s->regs[saddr] = val;
269
        break;
270
    case BONITO_BONGENCFG:
271
        if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
272
            reset = 1; /* bit 2 jump from 0 to 1 cause reset */
273
        }
274
        s->regs[saddr] = val;
275
        if (reset) {
276
            qemu_system_reset_request();
277
        }
278
        break;
279
    case BONITO_INTENSET:
280
        s->regs[BONITO_INTENSET] = val;
281
        s->regs[BONITO_INTEN] |= val;
282
        break;
283
    case BONITO_INTENCLR:
284
        s->regs[BONITO_INTENCLR] = val;
285
        s->regs[BONITO_INTEN] &= ~val;
286
        break;
287
    case BONITO_INTEN:
288
    case BONITO_INTISR:
289
        DPRINTF("write to readonly bonito register %x \n", saddr);
290
        break;
291
    default:
292
        DPRINTF("write to unknown bonito register %x \n", saddr);
293
        break;
294
    }
295
}
296

  
297
static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr)
298
{
299
    PCIBonitoState *s = opaque;
300
    uint32_t saddr;
301

  
302
    saddr = (addr - BONITO_REGBASE) >> 2;
303

  
304
    DPRINTF("bonito_readl "TARGET_FMT_plx"  \n", addr);
305
    switch (saddr) {
306
    case BONITO_INTISR:
307
        return s->regs[saddr];
308
    default:
309
        return s->regs[saddr];
310
    }
311
}
312

  
313
static CPUWriteMemoryFunc * const bonito_write[] = {
314
    NULL,
315
    NULL,
316
    bonito_writel,
317
};
318

  
319
static CPUReadMemoryFunc * const bonito_read[] = {
320
    NULL,
321
    NULL,
322
    bonito_readl,
323
};
324

  
325
static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
326
                                  uint32_t val)
327
{
328
    PCIBonitoState *s = opaque;
329

  
330
    DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x \n", addr, val);
331
    s->dev.config_write(&s->dev, addr, val, 4);
332
}
333

  
334
static uint32_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr)
335
{
336

  
337
    PCIBonitoState *s = opaque;
338

  
339
    DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr);
340
    return s->dev.config_read(&s->dev, addr, 4);
341
}
342

  
343
/* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
344
static CPUWriteMemoryFunc * const bonito_pciconf_write[] = {
345
    NULL,
346
    NULL,
347
    bonito_pciconf_writel,
348
};
349

  
350
static CPUReadMemoryFunc * const bonito_pciconf_read[] = {
351
    NULL,
352
    NULL,
353
    bonito_pciconf_readl,
354
};
355

  
356
static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr)
357
{
358
    uint32_t val;
359
    PCIBonitoState *s = opaque;
360

  
361
    val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)];
362

  
363
    return val;
364
}
365

  
366
static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
367
                               uint32_t val)
368
{
369
    PCIBonitoState *s = opaque;
370

  
371
    ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;
372
}
373

  
374
static CPUWriteMemoryFunc * const bonito_ldma_write[] = {
375
    NULL,
376
    NULL,
377
    bonito_ldma_writel,
378
};
379

  
380
static CPUReadMemoryFunc * const bonito_ldma_read[] = {
381
    NULL,
382
    NULL,
383
    bonito_ldma_readl,
384
};
385

  
386
static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr)
387
{
388
    uint32_t val;
389
    PCIBonitoState *s = opaque;
390

  
391
    val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)];
392

  
393
    return val;
394
}
395

  
396
static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
397
                              uint32_t val)
398
{
399
    PCIBonitoState *s = opaque;
400

  
401
    ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;
402
}
403

  
404
static CPUWriteMemoryFunc * const bonito_cop_write[] = {
405
    NULL,
406
    NULL,
407
    bonito_cop_writel,
408
};
409

  
410
static CPUReadMemoryFunc * const bonito_cop_read[] = {
411
    NULL,
412
    NULL,
413
    bonito_cop_readl,
414
};
415

  
416
static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
417
{
418
    PCIBonitoState *s = opaque;
419
    uint32_t cfgaddr;
420
    uint32_t idsel;
421
    uint32_t devno;
422
    uint32_t funno;
423
    uint32_t regno;
424
    uint32_t pciaddr;
425

  
426
    /* support type0 pci config */
427
    if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
428
        return 0xffffffff;
429
    }
430

  
431
    cfgaddr = addr & 0xffff;
432
    cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
433

  
434
    idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET;
435
    devno = ffs(idsel) - 1;
436
    funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
437
    regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET;
438

  
439
    if (idsel == 0) {
440
        fprintf(stderr, "error in bonito pci config address" TARGET_FMT_plx
441
            ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]);
442
        exit(1);
443
    }
444
    pciaddr = PCI_ADDR(pci_bus_num(s->pcihost->bus), devno, funno, regno);
445
    DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d \n",
446
        cfgaddr, pciaddr, pci_bus_num(s->pcihost->bus), devno, funno, regno);
447

  
448
    return pciaddr;
449
}
450

  
451
static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr,
452
                                   uint32_t val)
453
{
454
    PCIBonitoState *s = opaque;
455
    uint32_t pciaddr;
456
    uint16_t status;
457

  
458
    DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x \n", addr, val);
459
    pciaddr = bonito_sbridge_pciaddr(s, addr);
460

  
461
    if (pciaddr == 0xffffffff) {
462
        return;
463
    }
464

  
465
    /* set the pci address in s->config_reg */
466
    s->pcihost->config_reg = (pciaddr) | (1u << 31);
467
    pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val & 0xff, 1);
468

  
469
    /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
470
    status = pci_get_word(s->dev.config + PCI_STATUS);
471
    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
472
    pci_set_word(s->dev.config + PCI_STATUS, status);
473
}
474

  
475
static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr,
476
                                   uint32_t val)
477
{
478
    PCIBonitoState *s = opaque;
479
    uint32_t pciaddr;
480
    uint16_t status;
481

  
482
    DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x \n", addr, val);
483
    assert((addr&0x1)==0);
484

  
485
    pciaddr = bonito_sbridge_pciaddr(s, addr);
486

  
487
    if (pciaddr == 0xffffffff) {
488
        return;
489
    }
490

  
491
    /* set the pci address in s->config_reg */
492
    s->pcihost->config_reg = (pciaddr) | (1u << 31);
493
    pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 2);
494

  
495
    /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
496
    status = pci_get_word(s->dev.config + PCI_STATUS);
497
    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
498
    pci_set_word(s->dev.config + PCI_STATUS, status);
499
}
500

  
501
static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,
502
                                   uint32_t val)
503
{
504
    PCIBonitoState *s = opaque;
505
    uint32_t pciaddr;
506
    uint16_t status;
507

  
508
    DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x \n", addr, val);
509
    assert((addr&0x3)==0);
510

  
511
    pciaddr = bonito_sbridge_pciaddr(s, addr);
512

  
513
    if (pciaddr == 0xffffffff) {
514
        return;
515
    }
516

  
517
    /* set the pci address in s->config_reg */
518
    s->pcihost->config_reg = (pciaddr) | (1u << 31);
519
    pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 4);
520

  
521
    /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
522
    status = pci_get_word(s->dev.config + PCI_STATUS);
523
    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
524
    pci_set_word(s->dev.config + PCI_STATUS, status);
525
}
526

  
527
static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr)
528
{
529
    PCIBonitoState *s = opaque;
530
    uint32_t pciaddr;
531
    uint16_t status;
532

  
533
    DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"  \n", addr);
534
    pciaddr = bonito_sbridge_pciaddr(s, addr);
535

  
536
    if (pciaddr == 0xffffffff) {
537
        return 0xff;
538
    }
539

  
540
    /* set the pci address in s->config_reg */
541
    s->pcihost->config_reg = (pciaddr) | (1u << 31);
542

  
543
    /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
544
    status = pci_get_word(s->dev.config + PCI_STATUS);
545
    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
546
    pci_set_word(s->dev.config + PCI_STATUS, status);
547

  
548
    return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 1);
549
}
550

  
551
static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr)
552
{
553
    PCIBonitoState *s = opaque;
554
    uint32_t pciaddr;
555
    uint16_t status;
556

  
557
    DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"  \n", addr);
558
    assert((addr&0x1)==0);
559

  
560
    pciaddr = bonito_sbridge_pciaddr(s, addr);
561

  
562
    if (pciaddr == 0xffffffff) {
563
        return 0xffff;
564
    }
565

  
566
    /* set the pci address in s->config_reg */
567
    s->pcihost->config_reg = (pciaddr) | (1u << 31);
568

  
569
    /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
570
    status = pci_get_word(s->dev.config + PCI_STATUS);
571
    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
572
    pci_set_word(s->dev.config + PCI_STATUS, status);
573

  
574
    return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 2);
575
}
576

  
577
static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
578
{
579
    PCIBonitoState *s = opaque;
580
    uint32_t pciaddr;
581
    uint16_t status;
582

  
583
    DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"  \n", addr);
584
    assert((addr&0x3) == 0);
585

  
586
    pciaddr = bonito_sbridge_pciaddr(s, addr);
587

  
588
    if (pciaddr == 0xffffffff) {
589
        return 0xffffffff;
590
    }
591

  
592
    /* set the pci address in s->config_reg */
593
    s->pcihost->config_reg = (pciaddr) | (1u << 31);
594

  
595
    /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
596
    status = pci_get_word(s->dev.config + PCI_STATUS);
597
    status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
598
    pci_set_word(s->dev.config + PCI_STATUS, status);
599

  
600
    return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 4);
601
}
602

  
603
/* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
604
static CPUWriteMemoryFunc * const bonito_spciconf_write[] = {
605
    bonito_spciconf_writeb,
606
    bonito_spciconf_writew,
607
    bonito_spciconf_writel,
608
};
609

  
610
static CPUReadMemoryFunc * const bonito_spciconf_read[] = {
611
    bonito_spciconf_readb,
612
    bonito_spciconf_readw,
613
    bonito_spciconf_readl,
614
};
615

  
616
#define BONITO_IRQ_BASE 32
617

  
618
static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
619
{
620
    qemu_irq *pic = opaque;
621
    int internal_irq = irq_num - BONITO_IRQ_BASE;
622

  
623
    if (bonito_state->regs[BONITO_INTEDGE] & (1<<internal_irq)) {
624
        qemu_irq_pulse(*pic);
625
    } else {   /* level triggered */
626
        if (bonito_state->regs[BONITO_INTPOL] & (1<<internal_irq)) {
627
            qemu_irq_raise(*pic);
628
        } else {
629
            qemu_irq_lower(*pic);
630
        }
631
    }
632
}
633

  
634
/* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
635
static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num)
636
{
637
    int slot;
638

  
639
    slot = (pci_dev->devfn >> 3);
640

  
641
    switch (slot) {
642
    case 5:   /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
643
        return irq_num % 4 + BONITO_IRQ_BASE;
644
    case 6:   /* FULONG2E_ATI_SLOT, VGA */
645
        return 4 + BONITO_IRQ_BASE;
646
    case 7:   /* FULONG2E_RTL_SLOT, RTL8139 */
647
        return 5 + BONITO_IRQ_BASE;
648
    case 8 ... 12: /* PCI slot 1 to 4 */
649
        return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
650
    default:  /* Unknown device, don't do any translation */
651
        return irq_num;
652
    }
653
}
654

  
655
static void bonito_reset(void *opaque)
656
{
657
    PCIBonitoState *s = opaque;
658

  
659
    /* set the default value of north bridge registers */
660

  
661
    s->regs[BONITO_BONPONCFG] = 0xc40;
662
    s->regs[BONITO_BONGENCFG] = 0x1384;
663
    s->regs[BONITO_IODEVCFG] = 0x2bff8010;
664
    s->regs[BONITO_SDCFG] = 0x255e0091;
665

  
666
    s->regs[BONITO_GPIODATA] = 0x1ff;
667
    s->regs[BONITO_GPIOIE] = 0x1ff;
668
    s->regs[BONITO_DQCFG] = 0x8;
669
    s->regs[BONITO_MEMSIZE] = 0x10000000;
670
    s->regs[BONITO_PCIMAP] = 0x6140;
671
}
672

  
673
static const VMStateDescription vmstate_bonito = {
674
    .name = "Bonito",
675
    .version_id = 1,
676
    .minimum_version_id = 1,
677
    .minimum_version_id_old = 1,
678
    .fields      = (VMStateField []) {
679
        VMSTATE_PCI_DEVICE(dev, PCIBonitoState),
680
        VMSTATE_END_OF_LIST()
681
    }
682
};
683

  
684
static int bonito_pcihost_initfn(SysBusDevice *dev)
685
{
686
    return 0;
687
}
688

  
689
static int bonito_initfn(PCIDevice *dev)
690
{
691
    PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
692

  
693
    /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
694
    pci_config_set_vendor_id(dev->config, 0xdf53);
695
    pci_config_set_device_id(dev->config, 0x00d5);
696
    pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_HOST);
697
    pci_config_set_prog_interface(dev->config, 0x00);
698
    pci_config_set_revision(dev->config, 0x01);
699

  
700
    /* set the north bridge register mapping */
701
    s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s);
702
    s->bonito_reg_start = BONITO_INTERNAL_REG_BASE;
703
    s->bonito_reg_length = BONITO_INTERNAL_REG_SIZE;
704
    cpu_register_physical_memory(s->bonito_reg_start, s->bonito_reg_length,
705
                                 s->bonito_reg_handle);
706

  
707
    /* set the north bridge pci configure  mapping */
708
    s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read,
709
                                                      bonito_pciconf_write, s);
710
    s->bonito_pciconf_start = BONITO_PCICONFIG_BASE;
711
    s->bonito_pciconf_length = BONITO_PCICONFIG_SIZE;
712
    cpu_register_physical_memory(s->bonito_pciconf_start, s->bonito_pciconf_length,
713
                                 s->bonito_pciconf_handle);
714

  
715
    /* set the south bridge pci configure  mapping */
716
    s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read,
717
                                                       bonito_spciconf_write, s);
718
    s->bonito_spciconf_start = BONITO_SPCICONFIG_BASE;
719
    s->bonito_spciconf_length = BONITO_SPCICONFIG_SIZE;
720
    cpu_register_physical_memory(s->bonito_spciconf_start, s->bonito_spciconf_length,
721
                                 s->bonito_spciconf_handle);
722

  
723
    s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read,
724
                                                   bonito_ldma_write, s);
725
    s->bonito_ldma_start = 0xbfe00200;
726
    s->bonito_ldma_length = 0x100;
727
    cpu_register_physical_memory(s->bonito_ldma_start, s->bonito_ldma_length,
728
                                 s->bonito_ldma_handle);
729

  
730
    s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read,
731
                                                  bonito_cop_write, s);
732
    s->bonito_cop_start = 0xbfe00300;
733
    s->bonito_cop_length = 0x100;
734
    cpu_register_physical_memory(s->bonito_cop_start, s->bonito_cop_length,
735
                                 s->bonito_cop_handle);
736

  
737
    /* Map PCI IO Space  0x1fd0 0000 - 0x1fd1 0000 */
738
    s->bonito_pciio_start = BONITO_PCIIO_BASE;
739
    s->bonito_pciio_length = BONITO_PCIIO_SIZE;
740
    isa_mem_base = s->bonito_pciio_start;
741
    isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length, 0);
742

  
743
    /* add pci local io mapping */
744
    s->bonito_localio_start = BONITO_DEV_BASE;
745
    s->bonito_localio_length = BONITO_DEV_SIZE;
746
    isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length, 0);
747

  
748
    /* set the default value of north bridge pci config */
749
    pci_set_word(dev->config + PCI_COMMAND, 0x0000);
750
    pci_set_word(dev->config + PCI_STATUS, 0x0000);
751
    pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
752
    pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
753

  
754
    pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
755
    pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01);
756
    pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
757
    pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
758

  
759
    qemu_register_reset(bonito_reset, s);
760

  
761
    return 0;
762
}
763

  
764
PCIBus *bonito_init(qemu_irq *pic)
765
{
766
    DeviceState *dev;
767
    PCIBus *b;
768
    BonitoState *pcihost;
769
    PCIBonitoState *s;
770
    PCIDevice *d;
771

  
772
    dev = qdev_create(NULL, "Bonito-pcihost");
773
    pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev));
774
    b = pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_irq,
775
                         pci_bonito_map_irq, pic, 0x28, 32);
776
    pcihost->bus = b;
777
    qdev_init_nofail(dev);
778
    pci_bus_set_mem_base(pcihost->bus, 0x10000000);
779

  
780
    d = pci_create_simple(b, PCI_DEVFN(0, 0), "Bonito");
781
    s = DO_UPCAST(PCIBonitoState, dev, d);
782
    s->pcihost = pcihost;
783
    bonito_state = s;
784

  
785
    return b;
786
}
787

  
788
static PCIDeviceInfo bonito_info = {
789
    .qdev.name    = "Bonito",
790
    .qdev.desc    = "Host bridge",
791
    .qdev.size    = sizeof(PCIBonitoState),
792
    .qdev.vmsd    = &vmstate_bonito,
793
    .qdev.no_user = 1,
794
    .init         = bonito_initfn,
795
};
796

  
797
static SysBusDeviceInfo bonito_pcihost_info = {
798
    .init         = bonito_pcihost_initfn,
799
    .qdev.name    = "Bonito-pcihost",
800
    .qdev.size    = sizeof(BonitoState),
801
    .qdev.no_user = 1,
802
};
803

  
804
static void bonito_register(void)
805
{
806
    sysbus_register_withprop(&bonito_pcihost_info);
807
    pci_qdev_register(&bonito_info);
808
}
809
device_init(bonito_register);
b/hw/mips.h
5 5
/* gt64xxx.c */
6 6
PCIBus *pci_gt64120_init(qemu_irq *pic);
7 7

  
8
/* bonito.c */
9
PCIBus *bonito_init(qemu_irq *pic);
10

  
8 11
/* ds1225y.c */
9 12
void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
10 13
void ds1225y_set_protection(void *opaque, int protection);

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