Revision d12d51d5
| b/hw/ppc.c | ||
|---|---|---|
| 31 | 31 |
//#define PPC_DEBUG_IRQ |
| 32 | 32 |
//#define PPC_DEBUG_TB |
| 33 | 33 |
|
| 34 |
#ifdef PPC_DEBUG_IRQ |
|
| 35 |
# define LOG_IRQ(...) do { \
|
|
| 36 |
if (loglevel & CPU_LOG_INT) \ |
|
| 37 |
fprintf(logfile, ## __VA_ARGS__); \ |
|
| 38 |
} while (0) |
|
| 39 |
#else |
|
| 40 |
# define LOG_IRQ(...) do { } while (0)
|
|
| 41 |
#endif |
|
| 42 |
|
|
| 43 |
|
|
| 44 |
#ifdef PPC_DEBUG_TB |
|
| 45 |
# define LOG_TB(...) do { \
|
|
| 46 |
if (loglevel) \ |
|
| 47 |
fprintf(logfile, ## __VA_ARGS__); \ |
|
| 48 |
} while (0) |
|
| 49 |
#else |
|
| 50 |
# define LOG_TB(...) do { } while (0)
|
|
| 51 |
#endif |
|
| 52 |
|
|
| 34 | 53 |
static void cpu_ppc_tb_stop (CPUState *env); |
| 35 | 54 |
static void cpu_ppc_tb_start (CPUState *env); |
| 36 | 55 |
|
| ... | ... | |
| 44 | 63 |
if (env->pending_interrupts == 0) |
| 45 | 64 |
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
| 46 | 65 |
} |
| 47 |
#if defined(PPC_DEBUG_IRQ) |
|
| 48 |
if (loglevel & CPU_LOG_INT) {
|
|
| 49 |
fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08" PRIx32 |
|
| 66 |
LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
|
|
| 50 | 67 |
"req %08x\n", __func__, env, n_IRQ, level, |
| 51 | 68 |
env->pending_interrupts, env->interrupt_request); |
| 52 |
} |
|
| 53 |
#endif |
|
| 54 | 69 |
} |
| 55 | 70 |
|
| 56 | 71 |
/* PowerPC 6xx / 7xx internal IRQ controller */ |
| ... | ... | |
| 59 | 74 |
CPUState *env = opaque; |
| 60 | 75 |
int cur_level; |
| 61 | 76 |
|
| 62 |
#if defined(PPC_DEBUG_IRQ) |
|
| 63 |
if (loglevel & CPU_LOG_INT) {
|
|
| 64 |
fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, |
|
| 77 |
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
|
|
| 65 | 78 |
env, pin, level); |
| 66 |
} |
|
| 67 |
#endif |
|
| 68 | 79 |
cur_level = (env->irq_input_state >> pin) & 1; |
| 69 | 80 |
/* Don't generate spurious events */ |
| 70 | 81 |
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
|
| 71 | 82 |
switch (pin) {
|
| 72 | 83 |
case PPC6xx_INPUT_TBEN: |
| 73 | 84 |
/* Level sensitive - active high */ |
| 74 |
#if defined(PPC_DEBUG_IRQ) |
|
| 75 |
if (loglevel & CPU_LOG_INT) {
|
|
| 76 |
fprintf(logfile, "%s: %s the time base\n", |
|
| 85 |
LOG_IRQ("%s: %s the time base\n",
|
|
| 77 | 86 |
__func__, level ? "start" : "stop"); |
| 78 |
} |
|
| 79 |
#endif |
|
| 80 | 87 |
if (level) {
|
| 81 | 88 |
cpu_ppc_tb_start(env); |
| 82 | 89 |
} else {
|
| ... | ... | |
| 84 | 91 |
} |
| 85 | 92 |
case PPC6xx_INPUT_INT: |
| 86 | 93 |
/* Level sensitive - active high */ |
| 87 |
#if defined(PPC_DEBUG_IRQ) |
|
| 88 |
if (loglevel & CPU_LOG_INT) {
|
|
| 89 |
fprintf(logfile, "%s: set the external IRQ state to %d\n", |
|
| 94 |
LOG_IRQ("%s: set the external IRQ state to %d\n",
|
|
| 90 | 95 |
__func__, level); |
| 91 |
} |
|
| 92 |
#endif |
|
| 93 | 96 |
ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
| 94 | 97 |
break; |
| 95 | 98 |
case PPC6xx_INPUT_SMI: |
| 96 | 99 |
/* Level sensitive - active high */ |
| 97 |
#if defined(PPC_DEBUG_IRQ) |
|
| 98 |
if (loglevel & CPU_LOG_INT) {
|
|
| 99 |
fprintf(logfile, "%s: set the SMI IRQ state to %d\n", |
|
| 100 |
LOG_IRQ("%s: set the SMI IRQ state to %d\n",
|
|
| 100 | 101 |
__func__, level); |
| 101 |
} |
|
| 102 |
#endif |
|
| 103 | 102 |
ppc_set_irq(env, PPC_INTERRUPT_SMI, level); |
| 104 | 103 |
break; |
| 105 | 104 |
case PPC6xx_INPUT_MCP: |
| ... | ... | |
| 108 | 107 |
* 603/604/740/750: check HID0[EMCP] |
| 109 | 108 |
*/ |
| 110 | 109 |
if (cur_level == 1 && level == 0) {
|
| 111 |
#if defined(PPC_DEBUG_IRQ) |
|
| 112 |
if (loglevel & CPU_LOG_INT) {
|
|
| 113 |
fprintf(logfile, "%s: raise machine check state\n", |
|
| 110 |
LOG_IRQ("%s: raise machine check state\n",
|
|
| 114 | 111 |
__func__); |
| 115 |
} |
|
| 116 |
#endif |
|
| 117 | 112 |
ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); |
| 118 | 113 |
} |
| 119 | 114 |
break; |
| ... | ... | |
| 122 | 117 |
/* XXX: TODO: relay the signal to CKSTP_OUT pin */ |
| 123 | 118 |
/* XXX: Note that the only way to restart the CPU is to reset it */ |
| 124 | 119 |
if (level) {
|
| 125 |
#if defined(PPC_DEBUG_IRQ) |
|
| 126 |
if (loglevel & CPU_LOG_INT) {
|
|
| 127 |
fprintf(logfile, "%s: stop the CPU\n", __func__); |
|
| 128 |
} |
|
| 129 |
#endif |
|
| 120 |
LOG_IRQ("%s: stop the CPU\n", __func__);
|
|
| 130 | 121 |
env->halted = 1; |
| 131 | 122 |
} |
| 132 | 123 |
break; |
| 133 | 124 |
case PPC6xx_INPUT_HRESET: |
| 134 | 125 |
/* Level sensitive - active low */ |
| 135 | 126 |
if (level) {
|
| 136 |
#if defined(PPC_DEBUG_IRQ) |
|
| 137 |
if (loglevel & CPU_LOG_INT) {
|
|
| 138 |
fprintf(logfile, "%s: reset the CPU\n", __func__); |
|
| 139 |
} |
|
| 140 |
#endif |
|
| 127 |
LOG_IRQ("%s: reset the CPU\n", __func__);
|
|
| 141 | 128 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
| 142 | 129 |
/* XXX: TOFIX */ |
| 143 | 130 |
#if 0 |
| ... | ... | |
| 148 | 135 |
} |
| 149 | 136 |
break; |
| 150 | 137 |
case PPC6xx_INPUT_SRESET: |
| 151 |
#if defined(PPC_DEBUG_IRQ) |
|
| 152 |
if (loglevel & CPU_LOG_INT) {
|
|
| 153 |
fprintf(logfile, "%s: set the RESET IRQ state to %d\n", |
|
| 138 |
LOG_IRQ("%s: set the RESET IRQ state to %d\n",
|
|
| 154 | 139 |
__func__, level); |
| 155 |
} |
|
| 156 |
#endif |
|
| 157 | 140 |
ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
| 158 | 141 |
break; |
| 159 | 142 |
default: |
| 160 | 143 |
/* Unknown pin - do nothing */ |
| 161 |
#if defined(PPC_DEBUG_IRQ) |
|
| 162 |
if (loglevel & CPU_LOG_INT) {
|
|
| 163 |
fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); |
|
| 164 |
} |
|
| 165 |
#endif |
|
| 144 |
LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
|
|
| 166 | 145 |
return; |
| 167 | 146 |
} |
| 168 | 147 |
if (level) |
| ... | ... | |
| 185 | 164 |
CPUState *env = opaque; |
| 186 | 165 |
int cur_level; |
| 187 | 166 |
|
| 188 |
#if defined(PPC_DEBUG_IRQ) |
|
| 189 |
if (loglevel & CPU_LOG_INT) {
|
|
| 190 |
fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, |
|
| 167 |
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
|
|
| 191 | 168 |
env, pin, level); |
| 192 |
} |
|
| 193 |
#endif |
|
| 194 | 169 |
cur_level = (env->irq_input_state >> pin) & 1; |
| 195 | 170 |
/* Don't generate spurious events */ |
| 196 | 171 |
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
|
| 197 | 172 |
switch (pin) {
|
| 198 | 173 |
case PPC970_INPUT_INT: |
| 199 | 174 |
/* Level sensitive - active high */ |
| 200 |
#if defined(PPC_DEBUG_IRQ) |
|
| 201 |
if (loglevel & CPU_LOG_INT) {
|
|
| 202 |
fprintf(logfile, "%s: set the external IRQ state to %d\n", |
|
| 175 |
LOG_IRQ("%s: set the external IRQ state to %d\n",
|
|
| 203 | 176 |
__func__, level); |
| 204 |
} |
|
| 205 |
#endif |
|
| 206 | 177 |
ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
| 207 | 178 |
break; |
| 208 | 179 |
case PPC970_INPUT_THINT: |
| 209 | 180 |
/* Level sensitive - active high */ |
| 210 |
#if defined(PPC_DEBUG_IRQ) |
|
| 211 |
if (loglevel & CPU_LOG_INT) {
|
|
| 212 |
fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__, |
|
| 181 |
LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
|
|
| 213 | 182 |
level); |
| 214 |
} |
|
| 215 |
#endif |
|
| 216 | 183 |
ppc_set_irq(env, PPC_INTERRUPT_THERM, level); |
| 217 | 184 |
break; |
| 218 | 185 |
case PPC970_INPUT_MCP: |
| ... | ... | |
| 221 | 188 |
* 603/604/740/750: check HID0[EMCP] |
| 222 | 189 |
*/ |
| 223 | 190 |
if (cur_level == 1 && level == 0) {
|
| 224 |
#if defined(PPC_DEBUG_IRQ) |
|
| 225 |
if (loglevel & CPU_LOG_INT) {
|
|
| 226 |
fprintf(logfile, "%s: raise machine check state\n", |
|
| 191 |
LOG_IRQ("%s: raise machine check state\n",
|
|
| 227 | 192 |
__func__); |
| 228 |
} |
|
| 229 |
#endif |
|
| 230 | 193 |
ppc_set_irq(env, PPC_INTERRUPT_MCK, 1); |
| 231 | 194 |
} |
| 232 | 195 |
break; |
| ... | ... | |
| 234 | 197 |
/* Level sensitive - active low */ |
| 235 | 198 |
/* XXX: TODO: relay the signal to CKSTP_OUT pin */ |
| 236 | 199 |
if (level) {
|
| 237 |
#if defined(PPC_DEBUG_IRQ) |
|
| 238 |
if (loglevel & CPU_LOG_INT) {
|
|
| 239 |
fprintf(logfile, "%s: stop the CPU\n", __func__); |
|
| 240 |
} |
|
| 241 |
#endif |
|
| 200 |
LOG_IRQ("%s: stop the CPU\n", __func__);
|
|
| 242 | 201 |
env->halted = 1; |
| 243 | 202 |
} else {
|
| 244 |
#if defined(PPC_DEBUG_IRQ) |
|
| 245 |
if (loglevel & CPU_LOG_INT) {
|
|
| 246 |
fprintf(logfile, "%s: restart the CPU\n", __func__); |
|
| 247 |
} |
|
| 248 |
#endif |
|
| 203 |
LOG_IRQ("%s: restart the CPU\n", __func__);
|
|
| 249 | 204 |
env->halted = 0; |
| 250 | 205 |
} |
| 251 | 206 |
break; |
| ... | ... | |
| 253 | 208 |
/* Level sensitive - active low */ |
| 254 | 209 |
if (level) {
|
| 255 | 210 |
#if 0 // XXX: TOFIX |
| 256 |
#if defined(PPC_DEBUG_IRQ) |
|
| 257 |
if (loglevel & CPU_LOG_INT) {
|
|
| 258 |
fprintf(logfile, "%s: reset the CPU\n", __func__); |
|
| 259 |
} |
|
| 260 |
#endif |
|
| 211 |
LOG_IRQ("%s: reset the CPU\n", __func__);
|
|
| 261 | 212 |
cpu_reset(env); |
| 262 | 213 |
#endif |
| 263 | 214 |
} |
| 264 | 215 |
break; |
| 265 | 216 |
case PPC970_INPUT_SRESET: |
| 266 |
#if defined(PPC_DEBUG_IRQ) |
|
| 267 |
if (loglevel & CPU_LOG_INT) {
|
|
| 268 |
fprintf(logfile, "%s: set the RESET IRQ state to %d\n", |
|
| 217 |
LOG_IRQ("%s: set the RESET IRQ state to %d\n",
|
|
| 269 | 218 |
__func__, level); |
| 270 |
} |
|
| 271 |
#endif |
|
| 272 | 219 |
ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
| 273 | 220 |
break; |
| 274 | 221 |
case PPC970_INPUT_TBEN: |
| 275 |
#if defined(PPC_DEBUG_IRQ) |
|
| 276 |
if (loglevel & CPU_LOG_INT) {
|
|
| 277 |
fprintf(logfile, "%s: set the TBEN state to %d\n", __func__, |
|
| 222 |
LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
|
|
| 278 | 223 |
level); |
| 279 |
} |
|
| 280 |
#endif |
|
| 281 | 224 |
/* XXX: TODO */ |
| 282 | 225 |
break; |
| 283 | 226 |
default: |
| 284 | 227 |
/* Unknown pin - do nothing */ |
| 285 |
#if defined(PPC_DEBUG_IRQ) |
|
| 286 |
if (loglevel & CPU_LOG_INT) {
|
|
| 287 |
fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); |
|
| 288 |
} |
|
| 289 |
#endif |
|
| 228 |
LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
|
|
| 290 | 229 |
return; |
| 291 | 230 |
} |
| 292 | 231 |
if (level) |
| ... | ... | |
| 309 | 248 |
CPUState *env = opaque; |
| 310 | 249 |
int cur_level; |
| 311 | 250 |
|
| 312 |
#if defined(PPC_DEBUG_IRQ) |
|
| 313 |
if (loglevel & CPU_LOG_INT) {
|
|
| 314 |
fprintf(logfile, "%s: env %p pin %d level %d\n", __func__, |
|
| 251 |
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
|
|
| 315 | 252 |
env, pin, level); |
| 316 |
} |
|
| 317 |
#endif |
|
| 318 | 253 |
cur_level = (env->irq_input_state >> pin) & 1; |
| 319 | 254 |
/* Don't generate spurious events */ |
| 320 | 255 |
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
|
| 321 | 256 |
switch (pin) {
|
| 322 | 257 |
case PPC40x_INPUT_RESET_SYS: |
| 323 | 258 |
if (level) {
|
| 324 |
#if defined(PPC_DEBUG_IRQ) |
|
| 325 |
if (loglevel & CPU_LOG_INT) {
|
|
| 326 |
fprintf(logfile, "%s: reset the PowerPC system\n", |
|
| 259 |
LOG_IRQ("%s: reset the PowerPC system\n",
|
|
| 327 | 260 |
__func__); |
| 328 |
} |
|
| 329 |
#endif |
|
| 330 | 261 |
ppc40x_system_reset(env); |
| 331 | 262 |
} |
| 332 | 263 |
break; |
| 333 | 264 |
case PPC40x_INPUT_RESET_CHIP: |
| 334 | 265 |
if (level) {
|
| 335 |
#if defined(PPC_DEBUG_IRQ) |
|
| 336 |
if (loglevel & CPU_LOG_INT) {
|
|
| 337 |
fprintf(logfile, "%s: reset the PowerPC chip\n", __func__); |
|
| 338 |
} |
|
| 339 |
#endif |
|
| 266 |
LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
|
|
| 340 | 267 |
ppc40x_chip_reset(env); |
| 341 | 268 |
} |
| 342 | 269 |
break; |
| 343 | 270 |
case PPC40x_INPUT_RESET_CORE: |
| 344 | 271 |
/* XXX: TODO: update DBSR[MRR] */ |
| 345 | 272 |
if (level) {
|
| 346 |
#if defined(PPC_DEBUG_IRQ) |
|
| 347 |
if (loglevel & CPU_LOG_INT) {
|
|
| 348 |
fprintf(logfile, "%s: reset the PowerPC core\n", __func__); |
|
| 349 |
} |
|
| 350 |
#endif |
|
| 273 |
LOG_IRQ("%s: reset the PowerPC core\n", __func__);
|
|
| 351 | 274 |
ppc40x_core_reset(env); |
| 352 | 275 |
} |
| 353 | 276 |
break; |
| 354 | 277 |
case PPC40x_INPUT_CINT: |
| 355 | 278 |
/* Level sensitive - active high */ |
| 356 |
#if defined(PPC_DEBUG_IRQ) |
|
| 357 |
if (loglevel & CPU_LOG_INT) {
|
|
| 358 |
fprintf(logfile, "%s: set the critical IRQ state to %d\n", |
|
| 279 |
LOG_IRQ("%s: set the critical IRQ state to %d\n",
|
|
| 359 | 280 |
__func__, level); |
| 360 |
} |
|
| 361 |
#endif |
|
| 362 | 281 |
ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
| 363 | 282 |
break; |
| 364 | 283 |
case PPC40x_INPUT_INT: |
| 365 | 284 |
/* Level sensitive - active high */ |
| 366 |
#if defined(PPC_DEBUG_IRQ) |
|
| 367 |
if (loglevel & CPU_LOG_INT) {
|
|
| 368 |
fprintf(logfile, "%s: set the external IRQ state to %d\n", |
|
| 285 |
LOG_IRQ("%s: set the external IRQ state to %d\n",
|
|
| 369 | 286 |
__func__, level); |
| 370 |
} |
|
| 371 |
#endif |
|
| 372 | 287 |
ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
| 373 | 288 |
break; |
| 374 | 289 |
case PPC40x_INPUT_HALT: |
| 375 | 290 |
/* Level sensitive - active low */ |
| 376 | 291 |
if (level) {
|
| 377 |
#if defined(PPC_DEBUG_IRQ) |
|
| 378 |
if (loglevel & CPU_LOG_INT) {
|
|
| 379 |
fprintf(logfile, "%s: stop the CPU\n", __func__); |
|
| 380 |
} |
|
| 381 |
#endif |
|
| 292 |
LOG_IRQ("%s: stop the CPU\n", __func__);
|
|
| 382 | 293 |
env->halted = 1; |
| 383 | 294 |
} else {
|
| 384 |
#if defined(PPC_DEBUG_IRQ) |
|
| 385 |
if (loglevel & CPU_LOG_INT) {
|
|
| 386 |
fprintf(logfile, "%s: restart the CPU\n", __func__); |
|
| 387 |
} |
|
| 388 |
#endif |
|
| 295 |
LOG_IRQ("%s: restart the CPU\n", __func__);
|
|
| 389 | 296 |
env->halted = 0; |
| 390 | 297 |
} |
| 391 | 298 |
break; |
| 392 | 299 |
case PPC40x_INPUT_DEBUG: |
| 393 | 300 |
/* Level sensitive - active high */ |
| 394 |
#if defined(PPC_DEBUG_IRQ) |
|
| 395 |
if (loglevel & CPU_LOG_INT) {
|
|
| 396 |
fprintf(logfile, "%s: set the debug pin state to %d\n", |
|
| 301 |
LOG_IRQ("%s: set the debug pin state to %d\n",
|
|
| 397 | 302 |
__func__, level); |
| 398 |
} |
|
| 399 |
#endif |
|
| 400 | 303 |
ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
| 401 | 304 |
break; |
| 402 | 305 |
default: |
| 403 | 306 |
/* Unknown pin - do nothing */ |
| 404 |
#if defined(PPC_DEBUG_IRQ) |
|
| 405 |
if (loglevel & CPU_LOG_INT) {
|
|
| 406 |
fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin); |
|
| 407 |
} |
|
| 408 |
#endif |
|
| 307 |
LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
|
|
| 409 | 308 |
return; |
| 410 | 309 |
} |
| 411 | 310 |
if (level) |
| ... | ... | |
| 453 | 352 |
uint64_t tb; |
| 454 | 353 |
|
| 455 | 354 |
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
| 456 |
#if defined(PPC_DEBUG_TB) |
|
| 457 |
if (loglevel != 0) {
|
|
| 458 |
fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb); |
|
| 459 |
} |
|
| 460 |
#endif |
|
| 355 |
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
|
|
| 461 | 356 |
|
| 462 | 357 |
return tb & 0xFFFFFFFF; |
| 463 | 358 |
} |
| ... | ... | |
| 468 | 363 |
uint64_t tb; |
| 469 | 364 |
|
| 470 | 365 |
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
| 471 |
#if defined(PPC_DEBUG_TB) |
|
| 472 |
if (loglevel != 0) {
|
|
| 473 |
fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb); |
|
| 474 |
} |
|
| 475 |
#endif |
|
| 366 |
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
|
|
| 476 | 367 |
|
| 477 | 368 |
return tb >> 32; |
| 478 | 369 |
} |
| ... | ... | |
| 487 | 378 |
uint64_t value) |
| 488 | 379 |
{
|
| 489 | 380 |
*tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec); |
| 490 |
#ifdef PPC_DEBUG_TB |
|
| 491 |
if (loglevel != 0) {
|
|
| 492 |
fprintf(logfile, "%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", |
|
| 381 |
LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
|
|
| 493 | 382 |
__func__, value, *tb_offsetp); |
| 494 |
} |
|
| 495 |
#endif |
|
| 496 | 383 |
} |
| 497 | 384 |
|
| 498 | 385 |
void cpu_ppc_store_tbl (CPUState *env, uint32_t value) |
| ... | ... | |
| 528 | 415 |
uint64_t tb; |
| 529 | 416 |
|
| 530 | 417 |
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
| 531 |
#if defined(PPC_DEBUG_TB) |
|
| 532 |
if (loglevel != 0) {
|
|
| 533 |
fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb); |
|
| 534 |
} |
|
| 535 |
#endif |
|
| 418 |
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
|
|
| 536 | 419 |
|
| 537 | 420 |
return tb & 0xFFFFFFFF; |
| 538 | 421 |
} |
| ... | ... | |
| 543 | 426 |
uint64_t tb; |
| 544 | 427 |
|
| 545 | 428 |
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
| 546 |
#if defined(PPC_DEBUG_TB) |
|
| 547 |
if (loglevel != 0) {
|
|
| 548 |
fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb); |
|
| 549 |
} |
|
| 550 |
#endif |
|
| 429 |
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
|
|
| 551 | 430 |
|
| 552 | 431 |
return tb >> 32; |
| 553 | 432 |
} |
| ... | ... | |
| 629 | 508 |
decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec); |
| 630 | 509 |
else |
| 631 | 510 |
decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec); |
| 632 |
#if defined(PPC_DEBUG_TB) |
|
| 633 |
if (loglevel != 0) {
|
|
| 634 |
fprintf(logfile, "%s: %08" PRIx32 "\n", __func__, decr); |
|
| 635 |
} |
|
| 636 |
#endif |
|
| 511 |
LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);
|
|
| 637 | 512 |
|
| 638 | 513 |
return decr; |
| 639 | 514 |
} |
| ... | ... | |
| 668 | 543 |
static always_inline void cpu_ppc_decr_excp (CPUState *env) |
| 669 | 544 |
{
|
| 670 | 545 |
/* Raise it */ |
| 671 |
#ifdef PPC_DEBUG_TB |
|
| 672 |
if (loglevel != 0) {
|
|
| 673 |
fprintf(logfile, "raise decrementer exception\n"); |
|
| 674 |
} |
|
| 675 |
#endif |
|
| 546 |
LOG_TB("raise decrementer exception\n");
|
|
| 676 | 547 |
ppc_set_irq(env, PPC_INTERRUPT_DECR, 1); |
| 677 | 548 |
} |
| 678 | 549 |
|
| 679 | 550 |
static always_inline void cpu_ppc_hdecr_excp (CPUState *env) |
| 680 | 551 |
{
|
| 681 | 552 |
/* Raise it */ |
| 682 |
#ifdef PPC_DEBUG_TB |
|
| 683 |
if (loglevel != 0) {
|
|
| 684 |
fprintf(logfile, "raise decrementer exception\n"); |
|
| 685 |
} |
|
| 686 |
#endif |
|
| 553 |
LOG_TB("raise decrementer exception\n");
|
|
| 687 | 554 |
ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1); |
| 688 | 555 |
} |
| 689 | 556 |
|
| ... | ... | |
| 696 | 563 |
ppc_tb_t *tb_env = env->tb_env; |
| 697 | 564 |
uint64_t now, next; |
| 698 | 565 |
|
| 699 |
#ifdef PPC_DEBUG_TB |
|
| 700 |
if (loglevel != 0) {
|
|
| 701 |
fprintf(logfile, "%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, |
|
| 566 |
LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
|
|
| 702 | 567 |
decr, value); |
| 703 |
} |
|
| 704 |
#endif |
|
| 705 | 568 |
now = qemu_get_clock(vm_clock); |
| 706 | 569 |
next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq); |
| 707 | 570 |
if (is_excp) |
| ... | ... | |
| 882 | 745 |
env->spr[SPR_40x_TSR] |= 1 << 26; |
| 883 | 746 |
if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) |
| 884 | 747 |
ppc_set_irq(env, PPC_INTERRUPT_FIT, 1); |
| 885 |
#ifdef PPC_DEBUG_TB |
|
| 886 |
if (loglevel != 0) {
|
|
| 887 |
fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__, |
|
| 748 |
LOG_TB("%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
|
|
| 888 | 749 |
(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), |
| 889 | 750 |
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
| 890 |
} |
|
| 891 |
#endif |
|
| 892 | 751 |
} |
| 893 | 752 |
|
| 894 | 753 |
/* Programmable interval timer */ |
| ... | ... | |
| 902 | 761 |
!((env->spr[SPR_40x_TCR] >> 26) & 0x1) || |
| 903 | 762 |
(is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
|
| 904 | 763 |
/* Stop PIT */ |
| 905 |
#ifdef PPC_DEBUG_TB |
|
| 906 |
if (loglevel != 0) {
|
|
| 907 |
fprintf(logfile, "%s: stop PIT\n", __func__); |
|
| 908 |
} |
|
| 909 |
#endif |
|
| 764 |
LOG_TB("%s: stop PIT\n", __func__);
|
|
| 910 | 765 |
qemu_del_timer(tb_env->decr_timer); |
| 911 | 766 |
} else {
|
| 912 |
#ifdef PPC_DEBUG_TB |
|
| 913 |
if (loglevel != 0) {
|
|
| 914 |
fprintf(logfile, "%s: start PIT %016" PRIx64 "\n", |
|
| 767 |
LOG_TB("%s: start PIT %016" PRIx64 "\n",
|
|
| 915 | 768 |
__func__, ppcemb_timer->pit_reload); |
| 916 |
} |
|
| 917 |
#endif |
|
| 918 | 769 |
now = qemu_get_clock(vm_clock); |
| 919 | 770 |
next = now + muldiv64(ppcemb_timer->pit_reload, |
| 920 | 771 |
ticks_per_sec, tb_env->decr_freq); |
| ... | ... | |
| 940 | 791 |
if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) |
| 941 | 792 |
ppc_set_irq(env, PPC_INTERRUPT_PIT, 1); |
| 942 | 793 |
start_stop_pit(env, tb_env, 1); |
| 943 |
#ifdef PPC_DEBUG_TB |
|
| 944 |
if (loglevel != 0) {
|
|
| 945 |
fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " " |
|
| 794 |
LOG_TB("%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
|
|
| 946 | 795 |
"%016" PRIx64 "\n", __func__, |
| 947 | 796 |
(int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), |
| 948 | 797 |
(int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), |
| 949 | 798 |
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
| 950 | 799 |
ppcemb_timer->pit_reload); |
| 951 |
} |
|
| 952 |
#endif |
|
| 953 | 800 |
} |
| 954 | 801 |
|
| 955 | 802 |
/* Watchdog timer */ |
| ... | ... | |
| 984 | 831 |
next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq); |
| 985 | 832 |
if (next == now) |
| 986 | 833 |
next++; |
| 987 |
#ifdef PPC_DEBUG_TB |
|
| 988 |
if (loglevel != 0) {
|
|
| 989 |
fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__, |
|
| 834 |
LOG_TB("%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
|
|
| 990 | 835 |
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
| 991 |
} |
|
| 992 |
#endif |
|
| 993 | 836 |
switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
|
| 994 | 837 |
case 0x0: |
| 995 | 838 |
case 0x1: |
| ... | ... | |
| 1031 | 874 |
|
| 1032 | 875 |
tb_env = env->tb_env; |
| 1033 | 876 |
ppcemb_timer = tb_env->opaque; |
| 1034 |
#ifdef PPC_DEBUG_TB |
|
| 1035 |
if (loglevel != 0) {
|
|
| 1036 |
fprintf(logfile, "%s val" ADDRX "\n", __func__, val); |
|
| 1037 |
} |
|
| 1038 |
#endif |
|
| 877 |
LOG_TB("%s val" ADDRX "\n", __func__, val);
|
|
| 1039 | 878 |
ppcemb_timer->pit_reload = val; |
| 1040 | 879 |
start_stop_pit(env, tb_env, 0); |
| 1041 | 880 |
} |
| ... | ... | |
| 1047 | 886 |
|
| 1048 | 887 |
void store_booke_tsr (CPUState *env, target_ulong val) |
| 1049 | 888 |
{
|
| 1050 |
#ifdef PPC_DEBUG_TB |
|
| 1051 |
if (loglevel != 0) {
|
|
| 1052 |
fprintf(logfile, "%s: val " ADDRX "\n", __func__, val); |
|
| 1053 |
} |
|
| 1054 |
#endif |
|
| 889 |
LOG_TB("%s: val " ADDRX "\n", __func__, val);
|
|
| 1055 | 890 |
env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000); |
| 1056 | 891 |
if (val & 0x80000000) |
| 1057 | 892 |
ppc_set_irq(env, PPC_INTERRUPT_PIT, 0); |
| ... | ... | |
| 1062 | 897 |
ppc_tb_t *tb_env; |
| 1063 | 898 |
|
| 1064 | 899 |
tb_env = env->tb_env; |
| 1065 |
#ifdef PPC_DEBUG_TB |
|
| 1066 |
if (loglevel != 0) {
|
|
| 1067 |
fprintf(logfile, "%s: val " ADDRX "\n", __func__, val); |
|
| 1068 |
} |
|
| 1069 |
#endif |
|
| 900 |
LOG_TB("%s: val " ADDRX "\n", __func__, val);
|
|
| 1070 | 901 |
env->spr[SPR_40x_TCR] = val & 0xFFC00000; |
| 1071 | 902 |
start_stop_pit(env, tb_env, 1); |
| 1072 | 903 |
cpu_4xx_wdt_cb(env); |
| ... | ... | |
| 1077 | 908 |
CPUState *env = opaque; |
| 1078 | 909 |
ppc_tb_t *tb_env = env->tb_env; |
| 1079 | 910 |
|
| 1080 |
#ifdef PPC_DEBUG_TB |
|
| 1081 |
if (loglevel != 0) {
|
|
| 1082 |
fprintf(logfile, "%s set new frequency to %" PRIu32 "\n", __func__, |
|
| 911 |
LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
|
|
| 1083 | 912 |
freq); |
| 1084 |
} |
|
| 1085 |
#endif |
|
| 1086 | 913 |
tb_env->tb_freq = freq; |
| 1087 | 914 |
tb_env->decr_freq = freq; |
| 1088 | 915 |
/* XXX: we should also update all timers */ |
| ... | ... | |
| 1102 | 929 |
tb_env->tb_freq = freq; |
| 1103 | 930 |
tb_env->decr_freq = freq; |
| 1104 | 931 |
tb_env->opaque = ppcemb_timer; |
| 1105 |
#ifdef PPC_DEBUG_TB |
|
| 1106 |
if (loglevel != 0) {
|
|
| 1107 |
fprintf(logfile, "%s freq %" PRIu32 "\n", __func__, freq); |
|
| 1108 |
} |
|
| 1109 |
#endif |
|
| 932 |
LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
|
|
| 1110 | 933 |
if (ppcemb_timer != NULL) {
|
| 1111 | 934 |
/* We use decr timer for PIT */ |
| 1112 | 935 |
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); |
| b/hw/ppc4xx_devs.c | ||
|---|---|---|
| 31 | 31 |
//#define DEBUG_UNASSIGNED |
| 32 | 32 |
#define DEBUG_UIC |
| 33 | 33 |
|
| 34 |
|
|
| 35 |
#ifdef DEBUG_UIC |
|
| 36 |
# define LOG_UIC(...) do { \
|
|
| 37 |
if (loglevel & CPU_LOG_INT) \ |
|
| 38 |
fprintf(logfile, ## __VA_ARGS__); \ |
|
| 39 |
} while (0) |
|
| 40 |
#else |
|
| 41 |
# define LOG_UIC(...) do { } while (0)
|
|
| 42 |
#endif |
|
| 43 |
|
|
| 34 | 44 |
/*****************************************************************************/ |
| 35 | 45 |
/* Generic PowerPC 4xx processor instanciation */ |
| 36 | 46 |
CPUState *ppc4xx_init (const char *cpu_model, |
| ... | ... | |
| 294 | 304 |
/* Trigger interrupt if any is pending */ |
| 295 | 305 |
ir = uic->uicsr & uic->uicer & (~uic->uiccr); |
| 296 | 306 |
cr = uic->uicsr & uic->uicer & uic->uiccr; |
| 297 |
#ifdef DEBUG_UIC |
|
| 298 |
if (loglevel & CPU_LOG_INT) {
|
|
| 299 |
fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32 |
|
| 307 |
LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
|
|
| 300 | 308 |
" uiccr %08" PRIx32 "\n" |
| 301 | 309 |
" %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", |
| 302 | 310 |
__func__, uic->uicsr, uic->uicer, uic->uiccr, |
| 303 | 311 |
uic->uicsr & uic->uicer, ir, cr); |
| 304 |
} |
|
| 305 |
#endif |
|
| 306 | 312 |
if (ir != 0x0000000) {
|
| 307 |
#ifdef DEBUG_UIC |
|
| 308 |
if (loglevel & CPU_LOG_INT) {
|
|
| 309 |
fprintf(logfile, "Raise UIC interrupt\n"); |
|
| 310 |
} |
|
| 311 |
#endif |
|
| 313 |
LOG_UIC("Raise UIC interrupt\n");
|
|
| 312 | 314 |
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]); |
| 313 | 315 |
} else {
|
| 314 |
#ifdef DEBUG_UIC |
|
| 315 |
if (loglevel & CPU_LOG_INT) {
|
|
| 316 |
fprintf(logfile, "Lower UIC interrupt\n"); |
|
| 317 |
} |
|
| 318 |
#endif |
|
| 316 |
LOG_UIC("Lower UIC interrupt\n");
|
|
| 319 | 317 |
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]); |
| 320 | 318 |
} |
| 321 | 319 |
/* Trigger critical interrupt if any is pending and update vector */ |
| ... | ... | |
| 340 | 338 |
} |
| 341 | 339 |
} |
| 342 | 340 |
} |
| 343 |
#ifdef DEBUG_UIC |
|
| 344 |
if (loglevel & CPU_LOG_INT) {
|
|
| 345 |
fprintf(logfile, "Raise UIC critical interrupt - " |
|
| 341 |
LOG_UIC("Raise UIC critical interrupt - "
|
|
| 346 | 342 |
"vector %08" PRIx32 "\n", uic->uicvr); |
| 347 |
} |
|
| 348 |
#endif |
|
| 349 | 343 |
} else {
|
| 350 |
#ifdef DEBUG_UIC |
|
| 351 |
if (loglevel & CPU_LOG_INT) {
|
|
| 352 |
fprintf(logfile, "Lower UIC critical interrupt\n"); |
|
| 353 |
} |
|
| 354 |
#endif |
|
| 344 |
LOG_UIC("Lower UIC critical interrupt\n");
|
|
| 355 | 345 |
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]); |
| 356 | 346 |
uic->uicvr = 0x00000000; |
| 357 | 347 |
} |
| ... | ... | |
| 364 | 354 |
|
| 365 | 355 |
uic = opaque; |
| 366 | 356 |
mask = 1 << (31-irq_num); |
| 367 |
#ifdef DEBUG_UIC |
|
| 368 |
if (loglevel & CPU_LOG_INT) {
|
|
| 369 |
fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32 |
|
| 357 |
LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
|
|
| 370 | 358 |
" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", |
| 371 | 359 |
__func__, irq_num, level, |
| 372 | 360 |
uic->uicsr, mask, uic->uicsr & mask, level << irq_num); |
| 373 |
} |
|
| 374 |
#endif |
|
| 375 | 361 |
if (irq_num < 0 || irq_num > 31) |
| 376 | 362 |
return; |
| 377 | 363 |
sr = uic->uicsr; |
| ... | ... | |
| 391 | 377 |
uic->level &= ~mask; |
| 392 | 378 |
} |
| 393 | 379 |
} |
| 394 |
#ifdef DEBUG_UIC |
|
| 395 |
if (loglevel & CPU_LOG_INT) {
|
|
| 396 |
fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => " |
|
| 380 |
LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
|
|
| 397 | 381 |
"%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); |
| 398 |
} |
|
| 399 |
#endif |
|
| 400 | 382 |
if (sr != uic->uicsr) |
| 401 | 383 |
ppcuic_trigger_irq(uic); |
| 402 | 384 |
} |
| ... | ... | |
| 453 | 435 |
|
| 454 | 436 |
uic = opaque; |
| 455 | 437 |
dcrn -= uic->dcr_base; |
| 456 |
#ifdef DEBUG_UIC |
|
| 457 |
if (loglevel & CPU_LOG_INT) {
|
|
| 458 |
fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val); |
|
| 459 |
} |
|
| 460 |
#endif |
|
| 438 |
LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
|
|
| 461 | 439 |
switch (dcrn) {
|
| 462 | 440 |
case DCR_UICSR: |
| 463 | 441 |
uic->uicsr &= ~val; |
| b/kqemu.c | ||
|---|---|---|
| 47 | 47 |
#define DEBUG |
| 48 | 48 |
//#define PROFILE |
| 49 | 49 |
|
| 50 |
|
|
| 51 |
#ifdef DEBUG |
|
| 52 |
# define LOG_INT(...) do { \
|
|
| 53 |
if (loglevel & CPU_LOG_INT) \ |
|
| 54 |
fprintf(logfile, ## __VA_ARGS__); \ |
|
| 55 |
} while (0) |
|
| 56 |
# define LOG_INT_STATE(env) \ |
|
| 57 |
do { \
|
|
| 58 |
if (loglevel & CPU_LOG_INT) \ |
|
| 59 |
cpu_dump_state(env, logfile, fprintf, 0); \ |
|
| 60 |
} while (0) |
|
| 61 |
#else |
|
| 62 |
# define LOG_INT(...) do { } while (0)
|
|
| 63 |
# define LOG_INT_STATE(env) do { } while (0)
|
|
| 64 |
#endif |
|
| 65 |
|
|
| 50 | 66 |
#include <unistd.h> |
| 51 | 67 |
#include <fcntl.h> |
| 52 | 68 |
#include "kqemu.h" |
| ... | ... | |
| 241 | 257 |
|
| 242 | 258 |
void kqemu_flush_page(CPUState *env, target_ulong addr) |
| 243 | 259 |
{
|
| 244 |
#if defined(DEBUG) |
|
| 245 |
if (loglevel & CPU_LOG_INT) {
|
|
| 246 |
fprintf(logfile, "kqemu_flush_page: addr=" TARGET_FMT_lx "\n", addr); |
|
| 247 |
} |
|
| 248 |
#endif |
|
| 260 |
LOG_INT("kqemu_flush_page: addr=" TARGET_FMT_lx "\n", addr);
|
|
| 249 | 261 |
if (nb_pages_to_flush >= KQEMU_MAX_PAGES_TO_FLUSH) |
| 250 | 262 |
nb_pages_to_flush = KQEMU_FLUSH_ALL; |
| 251 | 263 |
else |
| ... | ... | |
| 254 | 266 |
|
| 255 | 267 |
void kqemu_flush(CPUState *env, int global) |
| 256 | 268 |
{
|
| 257 |
#ifdef DEBUG |
|
| 258 |
if (loglevel & CPU_LOG_INT) {
|
|
| 259 |
fprintf(logfile, "kqemu_flush:\n"); |
|
| 260 |
} |
|
| 261 |
#endif |
|
| 269 |
LOG_INT("kqemu_flush:\n");
|
|
| 262 | 270 |
nb_pages_to_flush = KQEMU_FLUSH_ALL; |
| 263 | 271 |
} |
| 264 | 272 |
|
| 265 | 273 |
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr) |
| 266 | 274 |
{
|
| 267 |
#ifdef DEBUG |
|
| 268 |
if (loglevel & CPU_LOG_INT) {
|
|
| 269 |
fprintf(logfile, "kqemu_set_notdirty: addr=%08lx\n", |
|
| 275 |
LOG_INT("kqemu_set_notdirty: addr=%08lx\n",
|
|
| 270 | 276 |
(unsigned long)ram_addr); |
| 271 |
} |
|
| 272 |
#endif |
|
| 273 | 277 |
/* we only track transitions to dirty state */ |
| 274 | 278 |
if (phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] != 0xff) |
| 275 | 279 |
return; |
| ... | ... | |
| 703 | 707 |
#ifdef CONFIG_PROFILER |
| 704 | 708 |
ti = profile_getclock(); |
| 705 | 709 |
#endif |
| 706 |
#ifdef DEBUG |
|
| 707 |
if (loglevel & CPU_LOG_INT) {
|
|
| 708 |
fprintf(logfile, "kqemu: cpu_exec: enter\n"); |
|
| 709 |
cpu_dump_state(env, logfile, fprintf, 0); |
|
| 710 |
} |
|
| 711 |
#endif |
|
| 710 |
LOG_INT("kqemu: cpu_exec: enter\n");
|
|
| 711 |
LOG_INT_STATE(env); |
|
| 712 | 712 |
for(i = 0; i < CPU_NB_REGS; i++) |
| 713 | 713 |
kenv->regs[i] = env->regs[i]; |
| 714 | 714 |
kenv->eip = env->eip; |
| ... | ... | |
| 867 | 867 |
else |
| 868 | 868 |
env->hflags &= ~HF_OSFXSR_MASK; |
| 869 | 869 |
|
| 870 |
#ifdef DEBUG |
|
| 871 |
if (loglevel & CPU_LOG_INT) {
|
|
| 872 |
fprintf(logfile, "kqemu: kqemu_cpu_exec: ret=0x%x\n", ret); |
|
| 873 |
} |
|
| 874 |
#endif |
|
| 870 |
LOG_INT("kqemu: kqemu_cpu_exec: ret=0x%x\n", ret);
|
|
| 875 | 871 |
if (ret == KQEMU_RET_SYSCALL) {
|
| 876 | 872 |
/* syscall instruction */ |
| 877 | 873 |
return do_syscall(env, kenv); |
| ... | ... | |
| 884 | 880 |
#ifdef CONFIG_PROFILER |
| 885 | 881 |
kqemu_ret_int_count++; |
| 886 | 882 |
#endif |
| 887 |
#ifdef DEBUG |
|
| 888 |
if (loglevel & CPU_LOG_INT) {
|
|
| 889 |
fprintf(logfile, "kqemu: interrupt v=%02x:\n", |
|
| 890 |
env->exception_index); |
|
| 891 |
cpu_dump_state(env, logfile, fprintf, 0); |
|
| 892 |
} |
|
| 893 |
#endif |
|
| 883 |
LOG_INT("kqemu: interrupt v=%02x:\n", env->exception_index);
|
|
| 884 |
LOG_INT_STATE(env); |
|
| 894 | 885 |
return 1; |
| 895 | 886 |
} else if ((ret & 0xff00) == KQEMU_RET_EXCEPTION) {
|
| 896 | 887 |
env->exception_index = ret & 0xff; |
| ... | ... | |
| 900 | 891 |
#ifdef CONFIG_PROFILER |
| 901 | 892 |
kqemu_ret_excp_count++; |
| 902 | 893 |
#endif |
| 903 |
#ifdef DEBUG |
|
| 904 |
if (loglevel & CPU_LOG_INT) {
|
|
| 905 |
fprintf(logfile, "kqemu: exception v=%02x e=%04x:\n", |
|
| 894 |
LOG_INT("kqemu: exception v=%02x e=%04x:\n",
|
|
| 906 | 895 |
env->exception_index, env->error_code); |
| 907 |
cpu_dump_state(env, logfile, fprintf, 0); |
|
| 908 |
} |
|
| 909 |
#endif |
|
| 896 |
LOG_INT_STATE(env); |
|
| 910 | 897 |
return 1; |
| 911 | 898 |
} else if (ret == KQEMU_RET_INTR) {
|
| 912 | 899 |
#ifdef CONFIG_PROFILER |
| 913 | 900 |
kqemu_ret_intr_count++; |
| 914 | 901 |
#endif |
| 915 |
#ifdef DEBUG |
|
| 916 |
if (loglevel & CPU_LOG_INT) {
|
|
| 917 |
cpu_dump_state(env, logfile, fprintf, 0); |
|
| 918 |
} |
|
| 919 |
#endif |
|
| 902 |
LOG_INT_STATE(env); |
|
| 920 | 903 |
return 0; |
| 921 | 904 |
} else if (ret == KQEMU_RET_SOFTMMU) {
|
| 922 | 905 |
#ifdef CONFIG_PROFILER |
| ... | ... | |
| 925 | 908 |
kqemu_record_pc(pc); |
| 926 | 909 |
} |
| 927 | 910 |
#endif |
| 928 |
#ifdef DEBUG |
|
| 929 |
if (loglevel & CPU_LOG_INT) {
|
|
| 930 |
cpu_dump_state(env, logfile, fprintf, 0); |
|
| 931 |
} |
|
| 932 |
#endif |
|
| 911 |
LOG_INT_STATE(env); |
|
| 933 | 912 |
return 2; |
| 934 | 913 |
} else {
|
| 935 | 914 |
cpu_dump_state(env, stderr, fprintf, 0); |
| b/linux-user/vm86.c | ||
|---|---|---|
| 29 | 29 |
|
| 30 | 30 |
//#define DEBUG_VM86 |
| 31 | 31 |
|
| 32 |
#ifdef DEBUG_VM86 |
|
| 33 |
# define LOG_VM86(...) fprintf(logfile, ## __VA_ARGS__); |
|
| 34 |
#else |
|
| 35 |
# define LOG_VM86(...) do { } while (0)
|
|
| 36 |
#endif |
|
| 37 |
|
|
| 38 |
|
|
| 32 | 39 |
#define set_flags(X,new,mask) \ |
| 33 | 40 |
((X) = ((X) & ~(mask)) | ((new) & (mask))) |
| 34 | 41 |
|
| ... | ... | |
| 92 | 99 |
set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask); |
| 93 | 100 |
target_v86->regs.eflags = tswap32(env->eflags); |
| 94 | 101 |
unlock_user_struct(target_v86, ts->target_v86, 1); |
| 95 |
#ifdef DEBUG_VM86 |
|
| 96 |
fprintf(logfile, "save_v86_state: eflags=%08x cs:ip=%04x:%04x\n", |
|
| 97 |
env->eflags, env->segs[R_CS].selector, env->eip); |
|
| 98 |
#endif |
|
| 102 |
LOG_VM86("save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
|
|
| 103 |
env->eflags, env->segs[R_CS].selector, env->eip); |
|
| 99 | 104 |
|
| 100 | 105 |
/* restore 32 bit registers */ |
| 101 | 106 |
env->regs[R_EAX] = ts->vm86_saved_regs.eax; |
| ... | ... | |
| 121 | 126 |
'retval' */ |
| 122 | 127 |
static inline void return_to_32bit(CPUX86State *env, int retval) |
| 123 | 128 |
{
|
| 124 |
#ifdef DEBUG_VM86 |
|
| 125 |
fprintf(logfile, "return_to_32bit: ret=0x%x\n", retval); |
|
| 126 |
#endif |
|
| 129 |
LOG_VM86("return_to_32bit: ret=0x%x\n", retval);
|
|
| 127 | 130 |
save_v86_state(env); |
| 128 | 131 |
env->regs[R_EAX] = retval; |
| 129 | 132 |
} |
| ... | ... | |
| 216 | 219 |
segoffs = ldl(int_addr); |
| 217 | 220 |
if ((segoffs >> 16) == TARGET_BIOSSEG) |
| 218 | 221 |
goto cannot_handle; |
| 219 |
#if defined(DEBUG_VM86) |
|
| 220 |
fprintf(logfile, "VM86: emulating int 0x%x. CS:IP=%04x:%04x\n", |
|
| 221 |
intno, segoffs >> 16, segoffs & 0xffff); |
|
| 222 |
#endif |
|
| 222 |
LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
|
|
| 223 |
intno, segoffs >> 16, segoffs & 0xffff); |
|
| 223 | 224 |
/* save old state */ |
| 224 | 225 |
ssp = env->segs[R_SS].selector << 4; |
| 225 | 226 |
sp = env->regs[R_ESP] & 0xffff; |
| ... | ... | |
| 235 | 236 |
clear_AC(env); |
| 236 | 237 |
return; |
| 237 | 238 |
cannot_handle: |
| 238 |
#if defined(DEBUG_VM86) |
|
| 239 |
fprintf(logfile, "VM86: return to 32 bits int 0x%x\n", intno); |
|
| 240 |
#endif |
|
| 239 |
LOG_VM86("VM86: return to 32 bits int 0x%x\n", intno);
|
|
| 241 | 240 |
return_to_32bit(env, TARGET_VM86_INTx | (intno << 8)); |
| 242 | 241 |
} |
| 243 | 242 |
|
| ... | ... | |
| 274 | 273 |
ssp = env->segs[R_SS].selector << 4; |
| 275 | 274 |
sp = env->regs[R_ESP] & 0xffff; |
| 276 | 275 |
|
| 277 |
#if defined(DEBUG_VM86) |
|
| 278 |
fprintf(logfile, "VM86 exception %04x:%08x\n", |
|
| 279 |
env->segs[R_CS].selector, env->eip); |
|
| 280 |
#endif |
|
| 276 |
LOG_VM86("VM86 exception %04x:%08x\n",
|
|
| 277 |
env->segs[R_CS].selector, env->eip); |
|
| 281 | 278 |
|
| 282 | 279 |
data32 = 0; |
| 283 | 280 |
pref_done = 0; |
| ... | ... | |
| 478 | 475 |
target_v86->vm86plus.vm86dbg_intxxtab, 32); |
| 479 | 476 |
unlock_user_struct(target_v86, vm86_addr, 0); |
| 480 | 477 |
|
| 481 |
#ifdef DEBUG_VM86 |
|
| 482 |
fprintf(logfile, "do_vm86: cs:ip=%04x:%04x\n", |
|
| 483 |
env->segs[R_CS].selector, env->eip); |
|
| 484 |
#endif |
|
| 478 |
LOG_VM86("do_vm86: cs:ip=%04x:%04x\n",
|
|
| 479 |
env->segs[R_CS].selector, env->eip); |
|
| 485 | 480 |
/* now the virtual CPU is ready for vm86 execution ! */ |
| 486 | 481 |
out: |
| 487 | 482 |
return ret; |
| b/target-alpha/translate.c | ||
|---|---|---|
| 37 | 37 |
#define ALPHA_DEBUG_DISAS |
| 38 | 38 |
/* #define DO_TB_FLUSH */ |
| 39 | 39 |
|
| 40 |
|
|
| 41 |
#ifdef ALPHA_DEBUG_DISAS |
|
| 42 |
# define LOG_DISAS(...) do { \
|
|
| 43 |
if (logfile) \ |
|
| 44 |
fprintf(logfile, ## __VA_ARGS__); \ |
|
| 45 |
} while (0) |
|
| 46 |
#else |
|
| 47 |
# define LOG_DISAS(...) do { } while (0)
|
|
| 48 |
#endif |
|
| 49 |
|
|
| 40 | 50 |
typedef struct DisasContext DisasContext; |
| 41 | 51 |
struct DisasContext {
|
| 42 | 52 |
uint64_t pc; |
| ... | ... | |
| 671 | 681 |
fn7 = (insn >> 5) & 0x0000007F; |
| 672 | 682 |
fn2 = (insn >> 5) & 0x00000003; |
| 673 | 683 |
ret = 0; |
| 674 |
#if defined ALPHA_DEBUG_DISAS |
|
| 675 |
if (logfile != NULL) {
|
|
| 676 |
fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n", |
|
| 677 |
opc, ra, rb, rc, disp16); |
|
| 678 |
} |
|
| 679 |
#endif |
|
| 684 |
LOG_DISAS("opc %02x ra %d rb %d rc %d disp16 %04x\n",
|
|
| 685 |
opc, ra, rb, rc, disp16); |
|
| 680 | 686 |
switch (opc) {
|
| 681 | 687 |
case 0x00: |
| 682 | 688 |
/* CALL_PAL */ |
| ... | ... | |
| 2386 | 2392 |
gen_io_start(); |
| 2387 | 2393 |
#if defined ALPHA_DEBUG_DISAS |
| 2388 | 2394 |
insn_count++; |
| 2389 |
if (logfile != NULL) {
|
|
| 2390 |
fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n", |
|
| 2391 |
ctx.pc, ctx.mem_idx); |
|
| 2392 |
} |
|
| 2395 |
LOG_DISAS("pc " TARGET_FMT_lx " mem_idx %d\n",
|
|
| 2396 |
ctx.pc, ctx.mem_idx); |
|
| 2393 | 2397 |
#endif |
| 2394 | 2398 |
insn = ldl_code(ctx.pc); |
| 2395 | 2399 |
#if defined ALPHA_DEBUG_DISAS |
| 2396 | 2400 |
insn_count++; |
| 2397 |
if (logfile != NULL) {
|
|
| 2398 |
fprintf(logfile, "opcode %08x %d\n", insn, insn_count); |
|
| 2399 |
} |
|
| 2401 |
LOG_DISAS("opcode %08x %d\n", insn, insn_count);
|
|
| 2400 | 2402 |
#endif |
| 2401 | 2403 |
num_insns++; |
| 2402 | 2404 |
ctx.pc += 4; |
| b/target-cris/helper.c | ||
|---|---|---|
| 28 | 28 |
#include "exec-all.h" |
| 29 | 29 |
#include "host-utils.h" |
| 30 | 30 |
|
| 31 |
|
|
| 32 |
//#define CRIS_HELPER_DEBUG |
|
| 33 |
|
|
| 34 |
|
|
| 35 |
#ifdef CRIS_HELPER_DEBUG |
|
| 36 |
#define D(x) x |
|
| 37 |
#define D_LOG(...) fprintf(logfile, ## __VA_ARGS__) |
|
| 38 |
#else |
|
| 31 | 39 |
#define D(x) |
| 40 |
#define D_LOG(...) do { } while (0)
|
|
| 41 |
#endif |
|
| 32 | 42 |
|
| 33 | 43 |
#if defined(CONFIG_USER_ONLY) |
| 34 | 44 |
|
| ... | ... | |
| 98 | 108 |
r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu); |
| 99 | 109 |
} |
| 100 | 110 |
if (r > 0) |
| 101 |
D(fprintf(logfile, "%s returns %d irqreq=%x addr=%x"
|
|
| 111 |
D_LOG("%s returns %d irqreq=%x addr=%x"
|
|
| 102 | 112 |
" phy=%x ismmu=%d vec=%x pc=%x\n", |
| 103 | 113 |
__func__, r, env->interrupt_request, |
| 104 |
address, res.phy, is_softmmu, res.bf_vec, env->pc));
|
|
| 114 |
address, res.phy, is_softmmu, res.bf_vec, env->pc); |
|
| 105 | 115 |
return r; |
| 106 | 116 |
} |
| 107 | 117 |
|
| ... | ... | |
| 109 | 119 |
{
|
| 110 | 120 |
int ex_vec = -1; |
| 111 | 121 |
|
| 112 |
D(fprintf (logfile, "exception index=%d interrupt_req=%d\n",
|
|
| 122 |
D_LOG( "exception index=%d interrupt_req=%d\n",
|
|
| 113 | 123 |
env->exception_index, |
| 114 |
env->interrupt_request));
|
|
| 124 |
env->interrupt_request); |
|
| 115 | 125 |
|
| 116 | 126 |
switch (env->exception_index) |
| 117 | 127 |
{
|
| ... | ... | |
| 147 | 157 |
env->pregs[PR_EXS] = (ex_vec & 0xff) << 8; |
| 148 | 158 |
|
| 149 | 159 |
if (env->dslot) {
|
| 150 |
D(fprintf(logfile, "excp isr=%x PC=%x ds=%d SP=%x"
|
|
| 160 |
D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
|
|
| 151 | 161 |
" ERP=%x pid=%x ccs=%x cc=%d %x\n", |
| 152 | 162 |
ex_vec, env->pc, env->dslot, |
| 153 | 163 |
env->regs[R_SP], |
| 154 | 164 |
env->pregs[PR_ERP], env->pregs[PR_PID], |
| 155 | 165 |
env->pregs[PR_CCS], |
| 156 |
env->cc_op, env->cc_mask));
|
|
| 166 |
env->cc_op, env->cc_mask); |
|
| 157 | 167 |
/* We loose the btarget, btaken state here so rexec the |
| 158 | 168 |
branch. */ |
| 159 | 169 |
env->pregs[PR_ERP] -= env->dslot; |
| ... | ... | |
| 171 | 181 |
|
| 172 | 182 |
/* Apply the CRIS CCS shift. Clears U if set. */ |
| 173 | 183 |
cris_shift_ccs(env); |
| 174 |
D(fprintf (logfile, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
|
|
| 184 |
D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
|
|
| 175 | 185 |
__func__, env->pc, ex_vec, |
| 176 | 186 |
env->pregs[PR_CCS], |
| 177 | 187 |
env->pregs[PR_PID], |
| 178 |
env->pregs[PR_ERP]));
|
|
| 188 |
env->pregs[PR_ERP]); |
|
| 179 | 189 |
} |
| 180 | 190 |
|
| 181 | 191 |
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
| b/target-cris/mmu.c | ||
|---|---|---|
| 32 | 32 |
|
| 33 | 33 |
#ifdef DEBUG |
| 34 | 34 |
#define D(x) x |
| 35 |
#define D_LOG(...) fprintf(logfile, ## __VA_ARGS__) |
|
| 35 | 36 |
#else |
| 36 | 37 |
#define D(x) |
| 38 |
#define D_LOG(...) do { } while (0)
|
|
| 37 | 39 |
#endif |
| 38 | 40 |
|
| 39 | 41 |
void cris_mmu_init(CPUState *env) |
| ... | ... | |
| 180 | 182 |
tlb_pid = EXTRACT_FIELD(hi, 0, 7); |
| 181 | 183 |
tlb_g = EXTRACT_FIELD(lo, 4, 4); |
| 182 | 184 |
|
| 183 |
D(fprintf(logfile, |
|
| 184 |
"TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n", |
|
| 185 |
mmu, set, idx, tlb_vpn, vpage, lo, hi)); |
|
| 185 |
D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
|
|
| 186 |
mmu, set, idx, tlb_vpn, vpage, lo, hi); |
|
| 186 | 187 |
if ((tlb_g || (tlb_pid == pid)) |
| 187 | 188 |
&& tlb_vpn == vpage) {
|
| 188 | 189 |
match = 1; |
| ... | ... | |
| 314 | 315 |
|
| 315 | 316 |
if (tlb_v && !tlb_g && (tlb_pid == pid)) {
|
| 316 | 317 |
vaddr = tlb_vpn << TARGET_PAGE_BITS; |
| 317 |
D(fprintf(logfile, |
|
| 318 |
"flush pid=%x vaddr=%x\n", |
|
| 319 |
pid, vaddr)); |
|
| 318 |
D_LOG("flush pid=%x vaddr=%x\n",
|
|
| 319 |
pid, vaddr); |
|
| 320 | 320 |
tlb_flush_page(env, vaddr); |
| 321 | 321 |
} |
| 322 | 322 |
} |
| b/target-cris/op_helper.c | ||
|---|---|---|
| 25 | 25 |
#include "helper.h" |
| 26 | 26 |
#include "host-utils.h" |
| 27 | 27 |
|
| 28 |
//#define CRIS_OP_HELPER_DEBUG |
|
| 29 |
|
|
| 30 |
|
|
| 31 |
#ifdef CRIS_OP_HELPER_DEBUG |
|
| 32 |
#define D(x) x |
|
| 33 |
#define D_LOG(...) fprintf(logfile, ## __VA_ARGS__) |
|
| 34 |
#else |
|
| 28 | 35 |
#define D(x) |
| 36 |
#define D_LOG(...) do { } while (0)
|
|
| 37 |
#endif |
|
| 29 | 38 |
|
| 30 | 39 |
#if !defined(CONFIG_USER_ONLY) |
| 31 | 40 |
|
| ... | ... | |
| 59 | 68 |
saved_env = env; |
| 60 | 69 |
env = cpu_single_env; |
| 61 | 70 |
|
| 62 |
D(fprintf(logfile, "%s pc=%x tpc=%x ra=%x\n", __func__,
|
|
| 63 |
env->pc, env->debug1, retaddr));
|
|
| 71 |
D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__,
|
|
| 72 |
env->pc, env->debug1, retaddr); |
|
| 64 | 73 |
ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); |
| 65 | 74 |
if (unlikely(ret)) {
|
| 66 | 75 |
if (retaddr) {
|
| ... | ... | |
| 155 | 164 |
env->tlbsets[srs - 1][set][idx].lo = lo; |
| 156 | 165 |
env->tlbsets[srs - 1][set][idx].hi = hi; |
| 157 | 166 |
|
| 158 |
D(fprintf(logfile, |
|
| 159 |
"tlb flush vaddr=%x v=%d pc=%x\n", |
|
| 160 |
vaddr, tlb_v, env->pc)); |
|
| 167 |
D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
|
|
| 168 |
vaddr, tlb_v, env->pc); |
|
| 161 | 169 |
tlb_flush_page(env, vaddr); |
| 162 | 170 |
} |
| 163 | 171 |
} |
| ... | ... | |
| 213 | 221 |
{
|
| 214 | 222 |
int rflag = env->pregs[PR_CCS] & R_FLAG; |
| 215 | 223 |
|
| 216 |
D(fprintf(logfile, "rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
|
|
| 224 |
D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
|
|
| 217 | 225 |
env->pregs[PR_ERP], env->pregs[PR_PID], |
| 218 | 226 |
env->pregs[PR_CCS], |
| 219 |
env->btarget));
|
|
| 227 |
env->btarget); |
|
| 220 | 228 |
|
| 221 | 229 |
cris_ccs_rshift(env); |
| 222 | 230 |
|
| ... | ... | |
| 229 | 237 |
{
|
| 230 | 238 |
int rflag = env->pregs[PR_CCS] & R_FLAG; |
| 231 | 239 |
|
| 232 |
D(fprintf(logfile, "rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
|
|
| 240 |
D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
|
|
| 233 | 241 |
env->pregs[PR_ERP], env->pregs[PR_PID], |
| 234 | 242 |
env->pregs[PR_CCS], |
| 235 |
env->btarget));
|
|
| 243 |
env->btarget); |
|
| 236 | 244 |
|
| 237 | 245 |
cris_ccs_rshift(env); |
| 238 | 246 |
|
| b/target-cris/translate.c | ||
|---|---|---|
| 44 | 44 |
|
| 45 | 45 |
#define DISAS_CRIS 0 |
| 46 | 46 |
#if DISAS_CRIS |
| 47 |
#define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x |
|
| 47 |
# define LOG_DIS(...) do { \
|
|
| 48 |
if (loglevel & CPU_LOG_TB_IN_ASM) \ |
|
| 49 |
fprintf(logfile, ## __VA_ARGS__); \ |
|
| 50 |
} while (0) |
|
| 48 | 51 |
#else |
| 49 |
#define DIS(x)
|
|
| 52 |
# define LOG_DIS(...) do { } while (0)
|
|
| 50 | 53 |
#endif |
| 51 | 54 |
|
| 52 | 55 |
#define D(x) |
| ... | ... | |
| 1344 | 1347 |
tmp = offset; |
| 1345 | 1348 |
offset = sign_extend(offset, 8); |
| 1346 | 1349 |
|
| 1347 |
DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset));
|
|
| 1350 |
LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
|
|
| 1348 | 1351 |
|
| 1349 | 1352 |
/* op2 holds the condition-code. */ |
| 1350 | 1353 |
cris_cc_mask(dc, 0); |
| ... | ... | |
| 1358 | 1361 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7); |
| 1359 | 1362 |
imm = sign_extend(dc->op1, 7); |
| 1360 | 1363 |
|
| 1361 |
DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
|
|
| 1364 |
LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
|
|
| 1362 | 1365 |
cris_cc_mask(dc, 0); |
| 1363 | 1366 |
/* Fetch register operand, */ |
| 1364 | 1367 |
tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm); |
| ... | ... | |
| 1367 | 1370 |
} |
| 1368 | 1371 |
static unsigned int dec_addq(DisasContext *dc) |
| 1369 | 1372 |
{
|
| 1370 |
DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
|
|
| 1373 |
LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
|
|
| 1371 | 1374 |
|
| 1372 | 1375 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1373 | 1376 |
|
| ... | ... | |
| 1383 | 1386 |
|
| 1384 | 1387 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1385 | 1388 |
imm = sign_extend(dc->op1, 5); |
| 1386 |
DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
|
|
| 1389 |
LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
|
|
| 1387 | 1390 |
|
| 1388 | 1391 |
tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm)); |
| 1389 | 1392 |
return 2; |
| ... | ... | |
| 1392 | 1395 |
{
|
| 1393 | 1396 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1394 | 1397 |
|
| 1395 |
DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
|
|
| 1398 |
LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
|
|
| 1396 | 1399 |
|
| 1397 | 1400 |
cris_cc_mask(dc, CC_MASK_NZVC); |
| 1398 | 1401 |
cris_alu(dc, CC_OP_SUB, |
| ... | ... | |
| 1405 | 1408 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1406 | 1409 |
imm = sign_extend(dc->op1, 5); |
| 1407 | 1410 |
|
| 1408 |
DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
|
|
| 1411 |
LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
|
|
| 1409 | 1412 |
cris_cc_mask(dc, CC_MASK_NZVC); |
| 1410 | 1413 |
|
| 1411 | 1414 |
cris_alu(dc, CC_OP_CMP, |
| ... | ... | |
| 1418 | 1421 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1419 | 1422 |
imm = sign_extend(dc->op1, 5); |
| 1420 | 1423 |
|
| 1421 |
DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
|
|
| 1424 |
LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
|
|
| 1422 | 1425 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1423 | 1426 |
|
| 1424 | 1427 |
cris_alu(dc, CC_OP_AND, |
| ... | ... | |
| 1430 | 1433 |
uint32_t imm; |
| 1431 | 1434 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); |
| 1432 | 1435 |
imm = sign_extend(dc->op1, 5); |
| 1433 |
DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
|
|
| 1436 |
LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
|
|
| 1434 | 1437 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1435 | 1438 |
|
| 1436 | 1439 |
cris_alu(dc, CC_OP_OR, |
| ... | ... | |
| 1440 | 1443 |
static unsigned int dec_btstq(DisasContext *dc) |
| 1441 | 1444 |
{
|
| 1442 | 1445 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 1443 |
DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
|
|
| 1446 |
LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
|
|
| 1444 | 1447 |
|
| 1445 | 1448 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1446 | 1449 |
cris_evaluate_flags(dc); |
| ... | ... | |
| 1455 | 1458 |
static unsigned int dec_asrq(DisasContext *dc) |
| 1456 | 1459 |
{
|
| 1457 | 1460 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 1458 |
DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
|
|
| 1461 |
LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
|
|
| 1459 | 1462 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1460 | 1463 |
|
| 1461 | 1464 |
tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1); |
| ... | ... | |
| 1467 | 1470 |
static unsigned int dec_lslq(DisasContext *dc) |
| 1468 | 1471 |
{
|
| 1469 | 1472 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 1470 |
DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
|
|
| 1473 |
LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
|
|
| 1471 | 1474 |
|
| 1472 | 1475 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1473 | 1476 |
|
| ... | ... | |
| 1481 | 1484 |
static unsigned int dec_lsrq(DisasContext *dc) |
| 1482 | 1485 |
{
|
| 1483 | 1486 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 1484 |
DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
|
|
| 1487 |
LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
|
|
| 1485 | 1488 |
|
| 1486 | 1489 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1487 | 1490 |
|
| ... | ... | |
| 1496 | 1499 |
{
|
| 1497 | 1500 |
int size = memsize_zz(dc); |
| 1498 | 1501 |
|
| 1499 |
DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
|
|
| 1500 |
memsize_char(size), dc->op1, dc->op2));
|
|
| 1502 |
LOG_DIS("move.%c $r%u, $r%u\n",
|
|
| 1503 |
memsize_char(size), dc->op1, dc->op2); |
|
| 1501 | 1504 |
|
| 1502 | 1505 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1503 | 1506 |
if (size == 4) {
|
| ... | ... | |
| 1524 | 1527 |
{
|
| 1525 | 1528 |
int cond = dc->op2; |
| 1526 | 1529 |
|
| 1527 |
DIS(fprintf (logfile, "s%s $r%u\n",
|
|
| 1528 |
cc_name(cond), dc->op1));
|
|
| 1530 |
LOG_DIS("s%s $r%u\n",
|
|
| 1531 |
cc_name(cond), dc->op1); |
|
| 1529 | 1532 |
|
| 1530 | 1533 |
if (cond != CC_A) |
| 1531 | 1534 |
{
|
| ... | ... | |
| 1568 | 1571 |
TCGv t[2]; |
| 1569 | 1572 |
int size = memsize_zz(dc); |
| 1570 | 1573 |
|
| 1571 |
DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
|
|
| 1572 |
memsize_char(size), dc->op1, dc->op2));
|
|
| 1574 |
LOG_DIS("and.%c $r%u, $r%u\n",
|
|
| 1575 |
memsize_char(size), dc->op1, dc->op2); |
|
| 1573 | 1576 |
|
| 1574 | 1577 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1575 | 1578 |
|
| ... | ... | |
| 1583 | 1586 |
static unsigned int dec_lz_r(DisasContext *dc) |
| 1584 | 1587 |
{
|
| 1585 | 1588 |
TCGv t0; |
| 1586 |
DIS(fprintf (logfile, "lz $r%u, $r%u\n",
|
|
| 1587 |
dc->op1, dc->op2));
|
|
| 1589 |
LOG_DIS("lz $r%u, $r%u\n",
|
|
| 1590 |
dc->op1, dc->op2); |
|
| 1588 | 1591 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1589 | 1592 |
t0 = tcg_temp_new(); |
| 1590 | 1593 |
dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0); |
| ... | ... | |
| 1598 | 1601 |
TCGv t[2]; |
| 1599 | 1602 |
int size = memsize_zz(dc); |
| 1600 | 1603 |
|
| 1601 |
DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
|
|
| 1602 |
memsize_char(size), dc->op1, dc->op2));
|
|
| 1604 |
LOG_DIS("lsl.%c $r%u, $r%u\n",
|
|
| 1605 |
memsize_char(size), dc->op1, dc->op2); |
|
| 1603 | 1606 |
|
| 1604 | 1607 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1605 | 1608 |
cris_alu_alloc_temps(dc, size, t); |
| ... | ... | |
| 1615 | 1618 |
TCGv t[2]; |
| 1616 | 1619 |
int size = memsize_zz(dc); |
| 1617 | 1620 |
|
| 1618 |
DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
|
|
| 1619 |
memsize_char(size), dc->op1, dc->op2));
|
|
| 1621 |
LOG_DIS("lsr.%c $r%u, $r%u\n",
|
|
| 1622 |
memsize_char(size), dc->op1, dc->op2); |
|
| 1620 | 1623 |
|
| 1621 | 1624 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1622 | 1625 |
cris_alu_alloc_temps(dc, size, t); |
| ... | ... | |
| 1632 | 1635 |
TCGv t[2]; |
| 1633 | 1636 |
int size = memsize_zz(dc); |
| 1634 | 1637 |
|
| 1635 |
DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
|
|
| 1636 |
memsize_char(size), dc->op1, dc->op2));
|
|
| 1638 |
LOG_DIS("asr.%c $r%u, $r%u\n",
|
|
| 1639 |
memsize_char(size), dc->op1, dc->op2); |
|
| 1637 | 1640 |
|
| 1638 | 1641 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1639 | 1642 |
cris_alu_alloc_temps(dc, size, t); |
| ... | ... | |
| 1649 | 1652 |
TCGv t[2]; |
| 1650 | 1653 |
int size = memsize_zz(dc); |
| 1651 | 1654 |
|
| 1652 |
DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
|
|
| 1653 |
memsize_char(size), dc->op1, dc->op2));
|
|
| 1655 |
LOG_DIS("muls.%c $r%u, $r%u\n",
|
|
| 1656 |
memsize_char(size), dc->op1, dc->op2); |
|
| 1654 | 1657 |
cris_cc_mask(dc, CC_MASK_NZV); |
| 1655 | 1658 |
cris_alu_alloc_temps(dc, size, t); |
| 1656 | 1659 |
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]); |
| ... | ... | |
| 1665 | 1668 |
TCGv t[2]; |
| 1666 | 1669 |
int size = memsize_zz(dc); |
| 1667 | 1670 |
|
| 1668 |
DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
|
|
| 1669 |
memsize_char(size), dc->op1, dc->op2));
|
|
| 1671 |
LOG_DIS("mulu.%c $r%u, $r%u\n",
|
|
| 1672 |
memsize_char(size), dc->op1, dc->op2); |
|
| 1670 | 1673 |
cris_cc_mask(dc, CC_MASK_NZV); |
| 1671 | 1674 |
cris_alu_alloc_temps(dc, size, t); |
| 1672 | 1675 |
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); |
| ... | ... | |
| 1679 | 1682 |
|
| 1680 | 1683 |
static unsigned int dec_dstep_r(DisasContext *dc) |
| 1681 | 1684 |
{
|
| 1682 |
DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
|
|
| 1685 |
LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
|
|
| 1683 | 1686 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1684 | 1687 |
cris_alu(dc, CC_OP_DSTEP, |
| 1685 | 1688 |
cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4); |
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