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1
/*
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 * QEMU PPC CHRP/PMAC hardware System Emulator
3
 *
4
 * Copyright (c) 2004-2007 Fabrice Bellard
5
 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
23
 */
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#include "vl.h"
25

    
26
/* SMP is not enabled, for now */
27
#define MAX_CPUS 1
28

    
29
#define BIOS_FILENAME "ppc_rom.bin"
30
#define VGABIOS_FILENAME "video.x"
31
#define NVRAM_SIZE        0x2000
32

    
33
#define KERNEL_LOAD_ADDR 0x01000000
34
#define INITRD_LOAD_ADDR 0x01800000
35

    
36
/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
37
   NVRAM */
38

    
39
static int dbdma_mem_index;
40
static int cuda_mem_index;
41
static int ide0_mem_index = -1;
42
static int ide1_mem_index = -1;
43
static int openpic_mem_index = -1;
44
static int heathrow_pic_mem_index = -1;
45
static int macio_nvram_mem_index = -1;
46

    
47
/* DBDMA: currently no op - should suffice right now */
48

    
49
static void dbdma_writeb (void *opaque,
50
                          target_phys_addr_t addr, uint32_t value)
51
{
52
    printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
53
}
54

    
55
static void dbdma_writew (void *opaque,
56
                          target_phys_addr_t addr, uint32_t value)
57
{
58
}
59

    
60
static void dbdma_writel (void *opaque,
61
                          target_phys_addr_t addr, uint32_t value)
62
{
63
}
64

    
65
static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
66
{
67
    printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr);
68

    
69
    return 0;
70
}
71

    
72
static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr)
73
{
74
    return 0;
75
}
76

    
77
static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
78
{
79
    return 0;
80
}
81

    
82
static CPUWriteMemoryFunc *dbdma_write[] = {
83
    &dbdma_writeb,
84
    &dbdma_writew,
85
    &dbdma_writel,
86
};
87

    
88
static CPUReadMemoryFunc *dbdma_read[] = {
89
    &dbdma_readb,
90
    &dbdma_readw,
91
    &dbdma_readl,
92
};
93

    
94
/* macio style NVRAM device */
95
typedef struct MacIONVRAMState {
96
    uint8_t data[0x2000];
97
} MacIONVRAMState;
98

    
99
static void macio_nvram_writeb (void *opaque,
100
                                target_phys_addr_t addr, uint32_t value)
101
{
102
    MacIONVRAMState *s = opaque;
103
    addr = (addr >> 4) & 0x1fff;
104
    s->data[addr] = value;
105
    //    printf("macio_nvram_writeb %04x = %02x\n", addr, value);
106
}
107

    
108
static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
109
{
110
    MacIONVRAMState *s = opaque;
111
    uint32_t value;
112

    
113
    addr = (addr >> 4) & 0x1fff;
114
    value = s->data[addr];
115
    //    printf("macio_nvram_readb %04x = %02x\n", addr, value);
116

    
117
    return value;
118
}
119

    
120
static CPUWriteMemoryFunc *macio_nvram_write[] = {
121
    &macio_nvram_writeb,
122
    &macio_nvram_writeb,
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    &macio_nvram_writeb,
124
};
125

    
126
static CPUReadMemoryFunc *macio_nvram_read[] = {
127
    &macio_nvram_readb,
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    &macio_nvram_readb,
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    &macio_nvram_readb,
130
};
131

    
132
static MacIONVRAMState *macio_nvram_init (void)
133
{
134
    MacIONVRAMState *s;
135
    s = qemu_mallocz(sizeof(MacIONVRAMState));
136
    if (!s)
137
        return NULL;
138
    macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
139
                                                   macio_nvram_write, s);
140

    
141
    return s;
142
}
143

    
144
static void macio_map (PCIDevice *pci_dev, int region_num,
145
                       uint32_t addr, uint32_t size, int type)
146
{
147
    if (heathrow_pic_mem_index >= 0) {
148
        cpu_register_physical_memory(addr + 0x00000, 0x1000,
149
                                     heathrow_pic_mem_index);
150
    }
151
    cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
152
    cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
153
    if (ide0_mem_index >= 0)
154
        cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
155
    if (ide1_mem_index >= 0)
156
        cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
157
    if (openpic_mem_index >= 0) {
158
        cpu_register_physical_memory(addr + 0x40000, 0x40000,
159
                                     openpic_mem_index);
160
    }
161
    if (macio_nvram_mem_index >= 0)
162
        cpu_register_physical_memory(addr + 0x60000, 0x20000,
163
                                     macio_nvram_mem_index);
164
}
165

    
166
static void macio_init (PCIBus *bus, int device_id)
167
{
168
    PCIDevice *d;
169

    
170
    d = pci_register_device(bus, "macio", sizeof(PCIDevice),
171
                            -1, NULL, NULL);
172
    /* Note: this code is strongly inspirated from the corresponding code
173
       in PearPC */
174
    d->config[0x00] = 0x6b; // vendor_id
175
    d->config[0x01] = 0x10;
176
    d->config[0x02] = device_id;
177
    d->config[0x03] = device_id >> 8;
178

    
179
    d->config[0x0a] = 0x00; // class_sub = pci2pci
180
    d->config[0x0b] = 0xff; // class_base = bridge
181
    d->config[0x0e] = 0x00; // header_type
182

    
183
    d->config[0x3d] = 0x01; // interrupt on pin 1
184

    
185
    dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
186

    
187
    pci_register_io_region(d, 0, 0x80000,
188
                           PCI_ADDRESS_SPACE_MEM, macio_map);
189
}
190

    
191
/* UniN device */
192
static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
193
{
194
}
195

    
196
static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
197
{
198
    return 0;
199
}
200

    
201
static CPUWriteMemoryFunc *unin_write[] = {
202
    &unin_writel,
203
    &unin_writel,
204
    &unin_writel,
205
};
206

    
207
static CPUReadMemoryFunc *unin_read[] = {
208
    &unin_readl,
209
    &unin_readl,
210
    &unin_readl,
211
};
212

    
213
/* temporary frame buffer OSI calls for the video.x driver. The right
214
   solution is to modify the driver to use VGA PCI I/Os */
215
/* XXX: to be removed. This is no way related to emulation */
216
static int vga_osi_call (CPUState *env)
217
{
218
    static int vga_vbl_enabled;
219
    int linesize;
220

    
221
    //    printf("osi_call R5=%d\n", env->gpr[5]);
222

    
223
    /* same handler as PearPC, coming from the original MOL video
224
       driver. */
225
    switch(env->gpr[5]) {
226
    case 4:
227
        break;
228
    case 28: /* set_vmode */
229
        if (env->gpr[6] != 1 || env->gpr[7] != 0)
230
            env->gpr[3] = 1;
231
        else
232
            env->gpr[3] = 0;
233
        break;
234
    case 29: /* get_vmode_info */
235
        if (env->gpr[6] != 0) {
236
            if (env->gpr[6] != 1 || env->gpr[7] != 0) {
237
                env->gpr[3] = 1;
238
                break;
239
            }
240
        }
241
        env->gpr[3] = 0;
242
        env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
243
        env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
244
        env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
245
        env->gpr[7] = 85 << 16; /* refresh rate */
246
        env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
247
        linesize = ((graphic_depth + 7) >> 3) * graphic_width;
248
        linesize = (linesize + 3) & ~3;
249
        env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
250
        break;
251
    case 31: /* set_video power */
252
        env->gpr[3] = 0;
253
        break;
254
    case 39: /* video_ctrl */
255
        if (env->gpr[6] == 0 || env->gpr[6] == 1)
256
            vga_vbl_enabled = env->gpr[6];
257
        env->gpr[3] = 0;
258
        break;
259
    case 47:
260
        break;
261
    case 59: /* set_color */
262
        /* R6 = index, R7 = RGB */
263
        env->gpr[3] = 0;
264
        break;
265
    case 64: /* get color */
266
        /* R6 = index */
267
        env->gpr[3] = 0;
268
        break;
269
    case 116: /* set hwcursor */
270
        /* R6 = x, R7 = y, R8 = visible, R9 = data */
271
        break;
272
    default:
273
        fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
274
        break;
275
    }
276

    
277
    return 1; /* osi_call handled */
278
}
279

    
280
static uint8_t nvram_chksum (const uint8_t *buf, int n)
281
{
282
    int sum, i;
283
    sum = 0;
284
    for(i = 0; i < n; i++)
285
        sum += buf[i];
286
    return (sum & 0xff) + (sum >> 8);
287
}
288

    
289
/* set a free Mac OS NVRAM partition */
290
void pmac_format_nvram_partition (uint8_t *buf, int len)
291
{
292
    char partition_name[12] = "wwwwwwwwwwww";
293

    
294
    buf[0] = 0x7f; /* free partition magic */
295
    buf[1] = 0; /* checksum */
296
    buf[2] = len >> 8;
297
    buf[3] = len;
298
    memcpy(buf + 4, partition_name, 12);
299
    buf[1] = nvram_chksum(buf, 16);
300
}
301

    
302
/* PowerPC CHRP hardware initialisation */
303
static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
304
                           DisplayState *ds, const char **fd_filename,
305
                           int snapshot,
306
                           const char *kernel_filename,
307
                           const char *kernel_cmdline,
308
                           const char *initrd_filename,
309
                           const char *cpu_model,
310
                           int is_heathrow)
311
{
312
    CPUState *env, *envs[MAX_CPUS];
313
    char buf[1024];
314
    qemu_irq *pic, **openpic_irqs;
315
    m48t59_t *nvram;
316
    int unin_memory;
317
    int linux_boot, i;
318
    unsigned long bios_offset, vga_bios_offset;
319
    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
320
    ppc_def_t *def;
321
    PCIBus *pci_bus;
322
    const char *arch_name;
323
    int vga_bios_size, bios_size;
324
    qemu_irq *dummy_irq;
325

    
326
    linux_boot = (kernel_filename != NULL);
327

    
328
    /* init CPUs */
329
    env = cpu_init();
330
    qemu_register_reset(&cpu_ppc_reset, env);
331
    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
332

    
333
    if (cpu_model == NULL)
334
        cpu_model = "default";
335
    ppc_find_by_name(cpu_model, &def);
336
    if (def == NULL) {
337
        cpu_abort(env, "Unable to find PowerPC CPU definition\n");
338
    }
339
    for (i = 0; i < smp_cpus; i++) {
340
        cpu_ppc_register(env, def);
341
        /* Set time-base frequency to 100 Mhz */
342
        cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
343
        env->osi_call = vga_osi_call;
344
        envs[i] = env;
345
    }
346

    
347
    /* allocate RAM */
348
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
349

    
350
    /* allocate and load BIOS */
351
    bios_offset = ram_size + vga_ram_size;
352
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
353
    bios_size = load_image(buf, phys_ram_base + bios_offset);
354
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
355
        cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
356
        exit(1);
357
    }
358
    bios_size = (bios_size + 0xfff) & ~0xfff;
359
    cpu_register_physical_memory((uint32_t)(-bios_size),
360
                                 bios_size, bios_offset | IO_MEM_ROM);
361

    
362
    /* allocate and load VGA BIOS */
363
    vga_bios_offset = bios_offset + bios_size;
364
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
365
    vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
366
    if (vga_bios_size < 0) {
367
        /* if no bios is present, we can still work */
368
        fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
369
        vga_bios_size = 0;
370
    } else {
371
        /* set a specific header (XXX: find real Apple format for NDRV
372
           drivers) */
373
        phys_ram_base[vga_bios_offset] = 'N';
374
        phys_ram_base[vga_bios_offset + 1] = 'D';
375
        phys_ram_base[vga_bios_offset + 2] = 'R';
376
        phys_ram_base[vga_bios_offset + 3] = 'V';
377
        cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
378
                     vga_bios_size);
379
        vga_bios_size += 8;
380
    }
381
    vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
382

    
383
    if (linux_boot) {
384
        kernel_base = KERNEL_LOAD_ADDR;
385
        /* now we can load the kernel */
386
        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
387
        if (kernel_size < 0) {
388
            cpu_abort(env, "qemu: could not load kernel '%s'\n",
389
                      kernel_filename);
390
            exit(1);
391
        }
392
        /* load initrd */
393
        if (initrd_filename) {
394
            initrd_base = INITRD_LOAD_ADDR;
395
            initrd_size = load_image(initrd_filename,
396
                                     phys_ram_base + initrd_base);
397
            if (initrd_size < 0) {
398
                cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
399
                          initrd_filename);
400
                exit(1);
401
            }
402
        } else {
403
            initrd_base = 0;
404
            initrd_size = 0;
405
        }
406
        boot_device = 'm';
407
    } else {
408
        kernel_base = 0;
409
        kernel_size = 0;
410
        initrd_base = 0;
411
        initrd_size = 0;
412
    }
413

    
414
    if (is_heathrow) {
415
        isa_mem_base = 0x80000000;
416

    
417
        /* Register 2 MB of ISA IO space */
418
        isa_mmio_init(0xfe000000, 0x00200000);
419

    
420
        /* init basic PC hardware */
421
        if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
422
            cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
423
            exit(1);
424
        }
425
        pic = heathrow_pic_init(&heathrow_pic_mem_index);
426
        pci_bus = pci_grackle_init(0xfec00000, pic);
427
        pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
428
                     ram_size, vga_ram_size,
429
                     vga_bios_offset, vga_bios_size);
430

    
431
        /* XXX: suppress that */
432
        dummy_irq = i8259_init(NULL);
433

    
434
        /* XXX: use Mac Serial port */
435
        serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
436

    
437
        for(i = 0; i < nb_nics; i++) {
438
            if (!nd_table[i].model)
439
                nd_table[i].model = "ne2k_pci";
440
            pci_nic_init(pci_bus, &nd_table[i], -1);
441
        }
442

    
443
        pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
444

    
445
        /* cuda also initialize ADB */
446
        cuda_mem_index = cuda_init(pic[0x12]);
447

    
448
        adb_kbd_init(&adb_bus);
449
        adb_mouse_init(&adb_bus);
450

    
451
        {
452
            MacIONVRAMState *nvr;
453
            nvr = macio_nvram_init();
454
            pmac_format_nvram_partition(nvr->data, 0x2000);
455
        }
456

    
457
        macio_init(pci_bus, 0x0017);
458

    
459
        nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
460

    
461
        arch_name = "HEATHROW";
462
    } else {
463
        isa_mem_base = 0x80000000;
464

    
465
        /* Register 8 MB of ISA IO space */
466
        isa_mmio_init(0xf2000000, 0x00800000);
467

    
468
        /* UniN init */
469
        unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
470
        cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
471

    
472
        openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
473
        openpic_irqs[0] =
474
            qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
475
        for (i = 0; i < smp_cpus; i++) {
476
            /* Mac99 IRQ connection between OpenPIC outputs pins
477
             * and PowerPC input pins
478
             */
479
            switch (PPC_INPUT(env)) {
480
            case PPC_FLAGS_INPUT_6xx:
481
                openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
482
                openpic_irqs[i][OPENPIC_OUTPUT_INT] =
483
                    ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
484
                openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
485
                    ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
486
                openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
487
                    ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
488
                /* Not connected ? */
489
                openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
490
                /* Check this */
491
                openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
492
                    ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
493
                break;
494
            case PPC_FLAGS_INPUT_970:
495
                openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
496
                openpic_irqs[i][OPENPIC_OUTPUT_INT] =
497
                    ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
498
                openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
499
                    ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
500
                openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
501
                    ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
502
                /* Not connected ? */
503
                openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
504
                /* Check this */
505
                openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
506
                    ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
507
                break;
508
            default:
509
                cpu_abort(env, "Bus model not supported on mac99 machine\n");
510
                exit(1);
511
            }
512
        }
513
        pic = openpic_init(NULL, &openpic_mem_index, smp_cpus,
514
                           openpic_irqs, NULL);
515
        pci_bus = pci_pmac_init(pic);
516
        /* init basic PC hardware */
517
        pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
518
                     ram_size, vga_ram_size,
519
                     vga_bios_offset, vga_bios_size);
520

    
521
        /* XXX: suppress that */
522
        dummy_irq = i8259_init(NULL);
523

    
524
        /* XXX: use Mac Serial port */
525
        serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
526
        for(i = 0; i < nb_nics; i++) {
527
            if (!nd_table[i].model)
528
                nd_table[i].model = "ne2k_pci";
529
            pci_nic_init(pci_bus, &nd_table[i], -1);
530
        }
531
#if 1
532
        ide0_mem_index = pmac_ide_init(&bs_table[0], pic[0x13]);
533
        ide1_mem_index = pmac_ide_init(&bs_table[2], pic[0x14]);
534
#else
535
        pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
536
#endif
537
        /* cuda also initialize ADB */
538
        cuda_mem_index = cuda_init(pic[0x19]);
539

    
540
        adb_kbd_init(&adb_bus);
541
        adb_mouse_init(&adb_bus);
542

    
543
        macio_init(pci_bus, 0x0022);
544

    
545
        nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
546

    
547
        arch_name = "MAC99";
548
    }
549

    
550
    if (usb_enabled) {
551
        usb_ohci_init_pci(pci_bus, 3, -1);
552
    }
553

    
554
    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
555
        graphic_depth = 15;
556

    
557
    PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device,
558
                         kernel_base, kernel_size,
559
                         kernel_cmdline,
560
                         initrd_base, initrd_size,
561
                         /* XXX: need an option to load a NVRAM image */
562
                         0,
563
                         graphic_width, graphic_height, graphic_depth);
564
    /* No PCI init: the BIOS will do it */
565

    
566
    /* Special port to get debug messages from Open-Firmware */
567
    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
568
}
569

    
570
static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device,
571
                             DisplayState *ds, const char **fd_filename,
572
                             int snapshot,
573
                             const char *kernel_filename,
574
                             const char *kernel_cmdline,
575
                             const char *initrd_filename,
576
                             const char *cpu_model)
577
{
578
    ppc_chrp_init(ram_size, vga_ram_size, boot_device,
579
                  ds, fd_filename, snapshot,
580
                  kernel_filename, kernel_cmdline,
581
                  initrd_filename, cpu_model, 0);
582
}
583

    
584
static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device,
585
                               DisplayState *ds, const char **fd_filename,
586
                               int snapshot,
587
                               const char *kernel_filename,
588
                               const char *kernel_cmdline,
589
                               const char *initrd_filename,
590
                               const char *cpu_model)
591
{
592
    ppc_chrp_init(ram_size, vga_ram_size, boot_device,
593
                  ds, fd_filename, snapshot,
594
                  kernel_filename, kernel_cmdline,
595
                  initrd_filename, cpu_model, 1);
596
}
597

    
598
QEMUMachine core99_machine = {
599
    "mac99",
600
    "Mac99 based PowerMAC",
601
    ppc_core99_init,
602
};
603

    
604
QEMUMachine heathrow_machine = {
605
    "g3bw",
606
    "Heathrow based PowerMAC",
607
    ppc_heathrow_init,
608
};