target-alpha: update STATUS
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5370 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert palcode ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5360 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert locked load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5359 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: misc fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5355 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert FP ops to TCG
- Convert FP ops to TCG- Fix S format- Implement F and G formats (untested)- Fix MF_FPCR an MT_FPCR- Fix FTOIS, FTOIT, ITOFF, ITOFS, ITOFT- Fix CPYSN, CPYSE
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5354 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: factorize load/store code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5353 c046a42c-6fe2-441c-8c8c-71466251a162
Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: switch most load/store ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5255 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert remaining arith3 functions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5254 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix one more literal sign issue
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5251 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: instruction decoding simplification
Use a litteral value of 0 when rb31 is used. This reduces the testsin the instruction decoding. Also remove almost unused corner cases.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5250 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert cmp* instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5249 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: fix a missing literal sign issue
Reported by Tristan Gingold
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5248 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: switch a few helpers to TCG
Switch a few helpers to TCG and implement RC and RS instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5247 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert byte manipulation instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5246 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: convert cmov and bcond to TCG
Patch mostly by Tristan Gingold
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5245 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: small optimizations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5238 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix TCG register names
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5237 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert some arith3 instructions to TCG
Replace gen_arith3 generic macro and dyngen ops by instruction specificoptimized TCG code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5236 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert arith2 instructions to TCG
Replace gen_arith2 generic macro and dyngon ops by instruction specificoptimized TCG code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5235 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: fix helper.h
the content of target-alpha/helper.h is duplicated twice
(Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5212 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: fix lit sign
according to the alpha arch reference, the literal field of an operateinstruction is unsigned:
If bit <12> of the instruction is 1, an 8-bit zero-extended literalconstant is formed by bits<20:13> of the instruction. The l teral is interpreted as a positive...
Fix warnings that would be caused by gcc flag -Wwrite-strings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5206 c046a42c-6fe2-441c-8c8c-71466251a162
fix alpha cmovxx instruction
The CMOV instruction is defined by the alpha manual as:
CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate formatCMOVxx Ra.rq,#b.ib,Rc.wq !Operate format
Operation:IF TEST THENRc ← Rbv
The current qemu behavior inverses Ra and Rb. This is fixed by this...
alpha: add target-alpha/helper.h (missing from commit r5150)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5161 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: convert a few more instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5152 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: directly access ir registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5151 c046a42c-6fe2-441c-8c8c-71466251a162
convert of few alpha insn to TCG
(based on a patch from Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5150 c046a42c-6fe2-441c-8c8c-71466251a162
Fix call_pal() prototype for alpha system emulation
(Hervé Poussineau)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5131 c046a42c-6fe2-441c-8c8c-71466251a162
Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
Fix warnings that would be generated by gcc -Wstrict-prototypes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5021 c046a42c-6fe2-441c-8c8c-71466251a162
Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
Move interrupt_request and user_mode_only to common cpu state.Save and restore env->interrupt_request and env->halted.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing static qualifiers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4801 c046a42c-6fe2-441c-8c8c-71466251a162
Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
Fix typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
Move clone() register setup to target specific code. Handle fork-like clone.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
Push common interrupt variables to cpu-defs.h (Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
moved halted field to CPU_COMMON
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
Fix off-by-one unwinding error.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
Factorize code in translate.c
(Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
Remove osdep.c/qemu-img code duplication
(Kevin Wolf)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
use the TCG code generator
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc host compile problem reported by Shaddy Baddah
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3750 c046a42c-6fe2-441c-8c8c-71466251a162
reduce verbosity
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3629 c046a42c-6fe2-441c-8c8c-71466251a162
fixed invalid type
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3582 c046a42c-6fe2-441c-8c8c-71466251a162
added cpu_model parameter to cpu_init()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
For consistency, move muls64 / mulu64 prototypes to host-utils.hMake x86_64 optimized versions inline.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3523 c046a42c-6fe2-441c-8c8c-71466251a162
Adjust s390 addresses (the MSB is defined as "to be ignored").
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
Make Alpha and PowerPC targets use shared helpers for clz, clo, ctz, cto and ctpop.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3466 c046a42c-6fe2-441c-8c8c-71466251a162
Alpha coding style and inlining fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3462 c046a42c-6fe2-441c-8c8c-71466251a162
Use host-utils for Alpha 64x64 bits multiplications.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3443 c046a42c-6fe2-441c-8c8c-71466251a162
New status file for Alpha emulation target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3422 c046a42c-6fe2-441c-8c8c-71466251a162
Allow Alpha target to use supervisor and executive mode micro-ops.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3389 c046a42c-6fe2-441c-8c8c-71466251a162
Generate micro-ops for Alpha executive and supervisor modes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3385 c046a42c-6fe2-441c-8c8c-71466251a162
Replace is_user variable with mmu_idx in softmmu core, allowing support of more than 2 mmu access modes.Add backward compatibility is_user variable in targets code when needed.Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions....
Move get_sp_from_cpustate from cpu.h to target_signal.h.Enable sigaltstack processing for more architectures.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3253 c046a42c-6fe2-441c-8c8c-71466251a162
linux-user sigaltstack() syscall, by Thayne Harbaugh.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3252 c046a42c-6fe2-441c-8c8c-71466251a162
Move likely and unlikely macros in a common place (Aurelien Jarno).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3192 c046a42c-6fe2-441c-8c8c-71466251a162
find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
Fix tb->size mishandling, by Daniel Jacobowitz.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3160 c046a42c-6fe2-441c-8c8c-71466251a162
Move target-specific defines to the target directories.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2940 c046a42c-6fe2-441c-8c8c-71466251a162
Clean up of some target specifics in exec.c/cpu-exec.c.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2936 c046a42c-6fe2-441c-8c8c-71466251a162
Avoid compiler warning.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2935 c046a42c-6fe2-441c-8c8c-71466251a162
Fix miscellaneous display warnings for PowerPC & alpha targetsand parallel CFI flash driver.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2661 c046a42c-6fe2-441c-8c8c-71466251a162
cpu_get_phys_page_debug should return target_phys_addr_t instead of target_ulong to be consistent.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2633 c046a42c-6fe2-441c-8c8c-71466251a162
Fix alpha target compilation on 32 bits hosts.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2608 c046a42c-6fe2-441c-8c8c-71466251a162
Alpha architecture emulation core.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2597 c046a42c-6fe2-441c-8c8c-71466251a162