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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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//#define DEBUG_PCI
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#define PCI_VENDOR_ID 0x00 /* 16 bits */ |
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#define PCI_DEVICE_ID 0x02 /* 16 bits */ |
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#define PCI_COMMAND 0x04 /* 16 bits */ |
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
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#define PCI_CLASS_DEVICE 0x0a /* Device class */ |
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
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#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
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#define PCI_MIN_GNT 0x3e /* 8 bits */ |
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#define PCI_MAX_LAT 0x3f /* 8 bits */ |
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/* just used for simpler irq handling. */
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#define PCI_DEVICES_MAX 64 |
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#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) |
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struct PCIBus {
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int bus_num;
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int devfn_min;
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void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level); |
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uint32_t config_reg; /* XXX: suppress */
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openpic_t *openpic; /* XXX: suppress */
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PCIDevice *devices[256];
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}; |
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target_phys_addr_t pci_mem_base; |
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static int pci_irq_index; |
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static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS]; |
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static PCIBus *first_bus;
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static PCIBus *pci_register_bus(void) |
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{ |
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PCIBus *bus; |
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bus = qemu_mallocz(sizeof(PCIBus));
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first_bus = bus; |
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return bus;
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} |
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|
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/* -1 for devfn means auto assign */
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PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
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int instance_size, int devfn, |
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PCIConfigReadFunc *config_read, |
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PCIConfigWriteFunc *config_write) |
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{ |
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PCIDevice *pci_dev; |
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if (pci_irq_index >= PCI_DEVICES_MAX)
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return NULL; |
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|
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if (devfn < 0) { |
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for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
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if (!bus->devices[devfn])
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goto found;
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} |
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return NULL; |
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found: ;
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} |
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pci_dev = qemu_mallocz(instance_size); |
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if (!pci_dev)
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return NULL; |
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pci_dev->bus = bus; |
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pci_dev->devfn = devfn; |
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pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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|
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if (!config_read)
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config_read = pci_default_read_config; |
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if (!config_write)
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config_write = pci_default_write_config; |
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pci_dev->config_read = config_read; |
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pci_dev->config_write = config_write; |
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pci_dev->irq_index = pci_irq_index++; |
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bus->devices[devfn] = pci_dev; |
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return pci_dev;
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} |
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void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
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uint32_t size, int type,
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PCIMapIORegionFunc *map_func) |
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{ |
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PCIIORegion *r; |
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if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
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return;
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r = &pci_dev->io_regions[region_num]; |
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r->addr = -1;
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r->size = size; |
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r->type = type; |
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r->map_func = map_func; |
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} |
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static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
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{ |
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PCIBus *s = opaque; |
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s->config_reg = val; |
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} |
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static uint32_t pci_addr_readl(void* opaque, uint32_t addr) |
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{ |
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PCIBus *s = opaque; |
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return s->config_reg;
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} |
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static void pci_update_mappings(PCIDevice *d) |
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{ |
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PCIIORegion *r; |
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int cmd, i;
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uint32_t last_addr, new_addr, config_ofs; |
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cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
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for(i = 0; i < PCI_NUM_REGIONS; i++) { |
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r = &d->io_regions[i]; |
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if (i == PCI_ROM_SLOT) {
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config_ofs = 0x30;
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} else {
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config_ofs = 0x10 + i * 4; |
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} |
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if (r->size != 0) { |
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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if (cmd & PCI_COMMAND_IO) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
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config_ofs)); |
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we have only 64K ioports on PC */
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if (last_addr <= new_addr || new_addr == 0 || |
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last_addr >= 0x10000) {
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new_addr = -1;
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} |
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} else {
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new_addr = -1;
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} |
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} else {
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if (cmd & PCI_COMMAND_MEMORY) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
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config_ofs)); |
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/* the ROM slot has a specific enable bit */
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if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
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goto no_mem_map;
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we do not support wrapping */
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/* XXX: as we cannot support really dynamic
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mappings, we handle specific values as invalid
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mappings. */
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if (last_addr <= new_addr || new_addr == 0 || |
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last_addr == -1) {
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new_addr = -1;
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} |
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} else {
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no_mem_map:
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new_addr = -1;
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} |
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} |
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/* now do the real mapping */
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if (new_addr != r->addr) {
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if (r->addr != -1) { |
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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int class;
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/* NOTE: specific hack for IDE in PC case:
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only one byte must be mapped. */
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class = d->config[0x0a] | (d->config[0x0b] << 8); |
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if (class == 0x0101 && r->size == 4) { |
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isa_unassign_ioport(r->addr + 2, 1); |
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} else {
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isa_unassign_ioport(r->addr, r->size); |
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} |
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} else {
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cpu_register_physical_memory(r->addr + pci_mem_base, |
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r->size, |
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IO_MEM_UNASSIGNED); |
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} |
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} |
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r->addr = new_addr; |
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if (r->addr != -1) { |
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r->map_func(d, i, r->addr, r->size, r->type); |
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} |
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} |
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} |
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} |
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} |
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uint32_t pci_default_read_config(PCIDevice *d, |
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uint32_t address, int len)
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{ |
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uint32_t val; |
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switch(len) {
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case 1: |
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val = d->config[address]; |
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break;
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case 2: |
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val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
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break;
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default:
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case 4: |
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val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
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break;
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} |
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return val;
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} |
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void pci_default_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{ |
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int can_write, i;
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uint32_t end, addr; |
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if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || |
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(address >= 0x30 && address < 0x34))) { |
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PCIIORegion *r; |
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int reg;
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if ( address >= 0x30 ) { |
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reg = PCI_ROM_SLOT; |
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}else{
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reg = (address - 0x10) >> 2; |
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} |
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r = &d->io_regions[reg]; |
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if (r->size == 0) |
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goto default_config;
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/* compute the stored value */
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if (reg == PCI_ROM_SLOT) {
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/* keep ROM enable bit */
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val &= (~(r->size - 1)) | 1; |
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} else {
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val &= ~(r->size - 1);
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val |= r->type; |
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} |
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*(uint32_t *)(d->config + address) = cpu_to_le32(val); |
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pci_update_mappings(d); |
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return;
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} |
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default_config:
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/* not efficient, but simple */
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addr = address; |
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for(i = 0; i < len; i++) { |
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/* default read/write accesses */
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switch(d->config[0x0e]) { |
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case 0x00: |
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case 0x80: |
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switch(addr) {
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case 0x00: |
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case 0x01: |
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case 0x02: |
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case 0x03: |
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case 0x08: |
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case 0x09: |
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case 0x0a: |
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case 0x0b: |
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case 0x0e: |
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case 0x10 ... 0x27: /* base */ |
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case 0x30 ... 0x33: /* rom */ |
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case 0x3d: |
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can_write = 0;
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break;
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default:
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can_write = 1;
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break;
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} |
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break;
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default:
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case 0x01: |
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switch(addr) {
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case 0x00: |
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case 0x01: |
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case 0x02: |
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case 0x03: |
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case 0x08: |
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case 0x09: |
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case 0x0a: |
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case 0x0b: |
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case 0x0e: |
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case 0x38 ... 0x3b: /* rom */ |
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case 0x3d: |
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can_write = 0;
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break;
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default:
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can_write = 1;
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break;
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} |
306 |
break;
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} |
308 |
if (can_write) {
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d->config[addr] = val; |
310 |
} |
311 |
addr++; |
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val >>= 8;
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} |
314 |
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end = address + len; |
316 |
if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
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/* if the command register is modified, we must modify the mappings */
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pci_update_mappings(d); |
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} |
320 |
} |
321 |
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static void pci_data_write(void *opaque, uint32_t addr, |
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uint32_t val, int len)
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{ |
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PCIBus *s = opaque; |
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PCIDevice *pci_dev; |
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int config_addr, bus_num;
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#if defined(DEBUG_PCI) && 0 |
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printf("pci_data_write: addr=%08x val=%08x len=%d\n",
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s->config_reg, val, len); |
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#endif
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if (!(s->config_reg & (1 << 31))) { |
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return;
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} |
336 |
if ((s->config_reg & 0x3) != 0) { |
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return;
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} |
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bus_num = (s->config_reg >> 16) & 0xff; |
340 |
if (bus_num != 0) |
341 |
return;
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pci_dev = s->devices[(s->config_reg >> 8) & 0xff]; |
343 |
if (!pci_dev)
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return;
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config_addr = (s->config_reg & 0xfc) | (addr & 3); |
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#if defined(DEBUG_PCI)
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printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
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pci_dev->name, config_addr, val, len); |
349 |
#endif
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350 |
pci_dev->config_write(pci_dev, config_addr, val, len); |
351 |
} |
352 |
|
353 |
static uint32_t pci_data_read(void *opaque, uint32_t addr, |
354 |
int len)
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355 |
{ |
356 |
PCIBus *s = opaque; |
357 |
PCIDevice *pci_dev; |
358 |
int config_addr, bus_num;
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uint32_t val; |
360 |
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361 |
if (!(s->config_reg & (1 << 31))) |
362 |
goto fail;
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363 |
if ((s->config_reg & 0x3) != 0) |
364 |
goto fail;
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bus_num = (s->config_reg >> 16) & 0xff; |
366 |
if (bus_num != 0) |
367 |
goto fail;
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368 |
pci_dev = s->devices[(s->config_reg >> 8) & 0xff]; |
369 |
if (!pci_dev) {
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370 |
fail:
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371 |
switch(len) {
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372 |
case 1: |
373 |
val = 0xff;
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374 |
break;
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375 |
case 2: |
376 |
val = 0xffff;
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377 |
break;
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378 |
default:
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379 |
case 4: |
380 |
val = 0xffffffff;
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381 |
break;
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382 |
} |
383 |
goto the_end;
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384 |
} |
385 |
config_addr = (s->config_reg & 0xfc) | (addr & 3); |
386 |
val = pci_dev->config_read(pci_dev, config_addr, len); |
387 |
#if defined(DEBUG_PCI)
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388 |
printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
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389 |
pci_dev->name, config_addr, val, len); |
390 |
#endif
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391 |
the_end:
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392 |
#if defined(DEBUG_PCI) && 0 |
393 |
printf("pci_data_read: addr=%08x val=%08x len=%d\n",
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394 |
s->config_reg, val, len); |
395 |
#endif
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396 |
return val;
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397 |
} |
398 |
|
399 |
static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val) |
400 |
{ |
401 |
pci_data_write(opaque, addr, val, 1);
|
402 |
} |
403 |
|
404 |
static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val) |
405 |
{ |
406 |
pci_data_write(opaque, addr, val, 2);
|
407 |
} |
408 |
|
409 |
static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val) |
410 |
{ |
411 |
pci_data_write(opaque, addr, val, 4);
|
412 |
} |
413 |
|
414 |
static uint32_t pci_data_readb(void* opaque, uint32_t addr) |
415 |
{ |
416 |
return pci_data_read(opaque, addr, 1); |
417 |
} |
418 |
|
419 |
static uint32_t pci_data_readw(void* opaque, uint32_t addr) |
420 |
{ |
421 |
return pci_data_read(opaque, addr, 2); |
422 |
} |
423 |
|
424 |
static uint32_t pci_data_readl(void* opaque, uint32_t addr) |
425 |
{ |
426 |
return pci_data_read(opaque, addr, 4); |
427 |
} |
428 |
|
429 |
/* i440FX PCI bridge */
|
430 |
|
431 |
static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level); |
432 |
|
433 |
PCIBus *i440fx_init(void)
|
434 |
{ |
435 |
PCIBus *s; |
436 |
PCIDevice *d; |
437 |
|
438 |
s = pci_register_bus(); |
439 |
s->set_irq = piix3_set_irq; |
440 |
|
441 |
register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s); |
442 |
register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s); |
443 |
|
444 |
register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s); |
445 |
register_ioport_write(0xcfc, 4, 2, pci_data_writew, s); |
446 |
register_ioport_write(0xcfc, 4, 4, pci_data_writel, s); |
447 |
register_ioport_read(0xcfc, 4, 1, pci_data_readb, s); |
448 |
register_ioport_read(0xcfc, 4, 2, pci_data_readw, s); |
449 |
register_ioport_read(0xcfc, 4, 4, pci_data_readl, s); |
450 |
|
451 |
d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0, |
452 |
NULL, NULL); |
453 |
|
454 |
d->config[0x00] = 0x86; // vendor_id |
455 |
d->config[0x01] = 0x80; |
456 |
d->config[0x02] = 0x37; // device_id |
457 |
d->config[0x03] = 0x12; |
458 |
d->config[0x08] = 0x02; // revision |
459 |
d->config[0x0a] = 0x00; // class_sub = host2pci |
460 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
461 |
d->config[0x0e] = 0x00; // header_type |
462 |
return s;
|
463 |
} |
464 |
|
465 |
/* PIIX3 PCI to ISA bridge */
|
466 |
|
467 |
typedef struct PIIX3State { |
468 |
PCIDevice dev; |
469 |
} PIIX3State; |
470 |
|
471 |
PIIX3State *piix3_state; |
472 |
|
473 |
/* return the global irq number corresponding to a given device irq
|
474 |
pin. We could also use the bus number to have a more precise
|
475 |
mapping. */
|
476 |
static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
477 |
{ |
478 |
int slot_addend;
|
479 |
slot_addend = (pci_dev->devfn >> 3);
|
480 |
return (irq_num + slot_addend) & 3; |
481 |
} |
482 |
|
483 |
static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
484 |
{ |
485 |
int irq_index, shift, pic_irq, pic_level;
|
486 |
uint32_t *p; |
487 |
|
488 |
irq_num = pci_slot_get_pirq(pci_dev, irq_num); |
489 |
irq_index = pci_dev->irq_index; |
490 |
p = &pci_irq_levels[irq_num][irq_index >> 5];
|
491 |
shift = (irq_index & 0x1f);
|
492 |
*p = (*p & ~(1 << shift)) | (level << shift);
|
493 |
|
494 |
/* now we change the pic irq level according to the piix irq mappings */
|
495 |
pic_irq = piix3_state->dev.config[0x60 + irq_num];
|
496 |
if (pic_irq < 16) { |
497 |
/* the pic level is the logical OR of all the PCI irqs mapped
|
498 |
to it */
|
499 |
pic_level = 0;
|
500 |
#if (PCI_IRQ_WORDS == 2) |
501 |
pic_level = ((pci_irq_levels[irq_num][0] |
|
502 |
pci_irq_levels[irq_num][1]) != 0); |
503 |
#else
|
504 |
{ |
505 |
int i;
|
506 |
pic_level = 0;
|
507 |
for(i = 0; i < PCI_IRQ_WORDS; i++) { |
508 |
if (pci_irq_levels[irq_num][i]) {
|
509 |
pic_level = 1;
|
510 |
break;
|
511 |
} |
512 |
} |
513 |
} |
514 |
#endif
|
515 |
pic_set_irq(pic_irq, pic_level); |
516 |
} |
517 |
} |
518 |
|
519 |
static void piix3_reset(PIIX3State *d) |
520 |
{ |
521 |
uint8_t *pci_conf = d->dev.config; |
522 |
|
523 |
pci_conf[0x04] = 0x07; // master, memory and I/O |
524 |
pci_conf[0x05] = 0x00; |
525 |
pci_conf[0x06] = 0x00; |
526 |
pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
527 |
pci_conf[0x4c] = 0x4d; |
528 |
pci_conf[0x4e] = 0x03; |
529 |
pci_conf[0x4f] = 0x00; |
530 |
pci_conf[0x60] = 0x80; |
531 |
pci_conf[0x69] = 0x02; |
532 |
pci_conf[0x70] = 0x80; |
533 |
pci_conf[0x76] = 0x0c; |
534 |
pci_conf[0x77] = 0x0c; |
535 |
pci_conf[0x78] = 0x02; |
536 |
pci_conf[0x79] = 0x00; |
537 |
pci_conf[0x80] = 0x00; |
538 |
pci_conf[0x82] = 0x00; |
539 |
pci_conf[0xa0] = 0x08; |
540 |
pci_conf[0xa0] = 0x08; |
541 |
pci_conf[0xa2] = 0x00; |
542 |
pci_conf[0xa3] = 0x00; |
543 |
pci_conf[0xa4] = 0x00; |
544 |
pci_conf[0xa5] = 0x00; |
545 |
pci_conf[0xa6] = 0x00; |
546 |
pci_conf[0xa7] = 0x00; |
547 |
pci_conf[0xa8] = 0x0f; |
548 |
pci_conf[0xaa] = 0x00; |
549 |
pci_conf[0xab] = 0x00; |
550 |
pci_conf[0xac] = 0x00; |
551 |
pci_conf[0xae] = 0x00; |
552 |
} |
553 |
|
554 |
void piix3_init(PCIBus *bus)
|
555 |
{ |
556 |
PIIX3State *d; |
557 |
uint8_t *pci_conf; |
558 |
|
559 |
d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State), |
560 |
-1, NULL, NULL); |
561 |
piix3_state = d; |
562 |
pci_conf = d->dev.config; |
563 |
|
564 |
pci_conf[0x00] = 0x86; // Intel |
565 |
pci_conf[0x01] = 0x80; |
566 |
pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
567 |
pci_conf[0x03] = 0x70; |
568 |
pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
569 |
pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
570 |
pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
571 |
|
572 |
piix3_reset(d); |
573 |
} |
574 |
|
575 |
/* PREP pci init */
|
576 |
|
577 |
static inline void set_config(PCIBus *s, target_phys_addr_t addr) |
578 |
{ |
579 |
int devfn, i;
|
580 |
|
581 |
for(i = 0; i < 11; i++) { |
582 |
if ((addr & (1 << (11 + i))) != 0) |
583 |
break;
|
584 |
} |
585 |
devfn = ((addr >> 8) & 7) | (i << 3); |
586 |
s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8); |
587 |
} |
588 |
|
589 |
static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
590 |
{ |
591 |
PCIBus *s = opaque; |
592 |
set_config(s, addr); |
593 |
pci_data_write(s, addr, val, 1);
|
594 |
} |
595 |
|
596 |
static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val) |
597 |
{ |
598 |
PCIBus *s = opaque; |
599 |
set_config(s, addr); |
600 |
#ifdef TARGET_WORDS_BIGENDIAN
|
601 |
val = bswap16(val); |
602 |
#endif
|
603 |
pci_data_write(s, addr, val, 2);
|
604 |
} |
605 |
|
606 |
static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
607 |
{ |
608 |
PCIBus *s = opaque; |
609 |
set_config(s, addr); |
610 |
#ifdef TARGET_WORDS_BIGENDIAN
|
611 |
val = bswap32(val); |
612 |
#endif
|
613 |
pci_data_write(s, addr, val, 4);
|
614 |
} |
615 |
|
616 |
static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) |
617 |
{ |
618 |
PCIBus *s = opaque; |
619 |
uint32_t val; |
620 |
set_config(s, addr); |
621 |
val = pci_data_read(s, addr, 1);
|
622 |
return val;
|
623 |
} |
624 |
|
625 |
static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr) |
626 |
{ |
627 |
PCIBus *s = opaque; |
628 |
uint32_t val; |
629 |
set_config(s, addr); |
630 |
val = pci_data_read(s, addr, 2);
|
631 |
#ifdef TARGET_WORDS_BIGENDIAN
|
632 |
val = bswap16(val); |
633 |
#endif
|
634 |
return val;
|
635 |
} |
636 |
|
637 |
static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr) |
638 |
{ |
639 |
PCIBus *s = opaque; |
640 |
uint32_t val; |
641 |
set_config(s, addr); |
642 |
val = pci_data_read(s, addr, 4);
|
643 |
#ifdef TARGET_WORDS_BIGENDIAN
|
644 |
val = bswap32(val); |
645 |
#endif
|
646 |
return val;
|
647 |
} |
648 |
|
649 |
static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
|
650 |
&PPC_PCIIO_writeb, |
651 |
&PPC_PCIIO_writew, |
652 |
&PPC_PCIIO_writel, |
653 |
}; |
654 |
|
655 |
static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
|
656 |
&PPC_PCIIO_readb, |
657 |
&PPC_PCIIO_readw, |
658 |
&PPC_PCIIO_readl, |
659 |
}; |
660 |
|
661 |
static void prep_set_irq(PCIDevice *d, int irq_num, int level) |
662 |
{ |
663 |
/* XXX: we do not simulate the hardware - we rely on the BIOS to
|
664 |
set correctly for irq line field */
|
665 |
pic_set_irq(d->config[PCI_INTERRUPT_LINE], level); |
666 |
} |
667 |
|
668 |
PCIBus *pci_prep_init(void)
|
669 |
{ |
670 |
PCIBus *s; |
671 |
PCIDevice *d; |
672 |
int PPC_io_memory;
|
673 |
|
674 |
s = pci_register_bus(); |
675 |
s->set_irq = prep_set_irq; |
676 |
|
677 |
PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
|
678 |
PPC_PCIIO_write, s); |
679 |
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); |
680 |
|
681 |
d = pci_register_device(s, "PREP PCI Bridge", sizeof(PCIDevice), 0, |
682 |
NULL, NULL); |
683 |
|
684 |
/* XXX: put correct IDs */
|
685 |
d->config[0x00] = 0x11; // vendor_id |
686 |
d->config[0x01] = 0x10; |
687 |
d->config[0x02] = 0x26; // device_id |
688 |
d->config[0x03] = 0x00; |
689 |
d->config[0x08] = 0x02; // revision |
690 |
d->config[0x0a] = 0x04; // class_sub = pci2pci |
691 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge |
692 |
d->config[0x0e] = 0x01; // header_type |
693 |
return s;
|
694 |
} |
695 |
|
696 |
|
697 |
/* pmac pci init */
|
698 |
|
699 |
#if 0
|
700 |
/* Grackle PCI host */
|
701 |
static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
|
702 |
uint32_t val)
|
703 |
{
|
704 |
PCIBus *s = opaque;
|
705 |
#ifdef TARGET_WORDS_BIGENDIAN
|
706 |
val = bswap32(val);
|
707 |
#endif
|
708 |
s->config_reg = val; |
709 |
} |
710 |
|
711 |
static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) |
712 |
{ |
713 |
PCIBus *s = opaque; |
714 |
uint32_t val; |
715 |
|
716 |
val = s->config_reg; |
717 |
#ifdef TARGET_WORDS_BIGENDIAN
|
718 |
val = bswap32(val); |
719 |
#endif
|
720 |
return val;
|
721 |
} |
722 |
|
723 |
static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
|
724 |
&pci_grackle_config_writel, |
725 |
&pci_grackle_config_writel, |
726 |
&pci_grackle_config_writel, |
727 |
}; |
728 |
|
729 |
static CPUReadMemoryFunc *pci_grackle_config_read[] = {
|
730 |
&pci_grackle_config_readl, |
731 |
&pci_grackle_config_readl, |
732 |
&pci_grackle_config_readl, |
733 |
}; |
734 |
|
735 |
static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr, |
736 |
uint32_t val) |
737 |
{ |
738 |
PCIBus *s = opaque; |
739 |
pci_data_write(s, addr, val, 1);
|
740 |
} |
741 |
|
742 |
static void pci_grackle_writew (void *opaque, target_phys_addr_t addr, |
743 |
uint32_t val) |
744 |
{ |
745 |
PCIBus *s = opaque; |
746 |
#ifdef TARGET_WORDS_BIGENDIAN
|
747 |
val = bswap16(val); |
748 |
#endif
|
749 |
pci_data_write(s, addr, val, 2);
|
750 |
} |
751 |
|
752 |
static void pci_grackle_writel (void *opaque, target_phys_addr_t addr, |
753 |
uint32_t val) |
754 |
{ |
755 |
PCIBus *s = opaque; |
756 |
#ifdef TARGET_WORDS_BIGENDIAN
|
757 |
val = bswap32(val); |
758 |
#endif
|
759 |
pci_data_write(s, addr, val, 4);
|
760 |
} |
761 |
|
762 |
static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr) |
763 |
{ |
764 |
PCIBus *s = opaque; |
765 |
uint32_t val; |
766 |
val = pci_data_read(s, addr, 1);
|
767 |
return val;
|
768 |
} |
769 |
|
770 |
static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr) |
771 |
{ |
772 |
PCIBus *s = opaque; |
773 |
uint32_t val; |
774 |
val = pci_data_read(s, addr, 2);
|
775 |
#ifdef TARGET_WORDS_BIGENDIAN
|
776 |
val = bswap16(val); |
777 |
#endif
|
778 |
return val;
|
779 |
} |
780 |
|
781 |
static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr) |
782 |
{ |
783 |
PCIBus *s = opaque; |
784 |
uint32_t val; |
785 |
|
786 |
val = pci_data_read(s, addr, 4);
|
787 |
#ifdef TARGET_WORDS_BIGENDIAN
|
788 |
val = bswap32(val); |
789 |
#endif
|
790 |
return val;
|
791 |
} |
792 |
|
793 |
static CPUWriteMemoryFunc *pci_grackle_write[] = {
|
794 |
&pci_grackle_writeb, |
795 |
&pci_grackle_writew, |
796 |
&pci_grackle_writel, |
797 |
}; |
798 |
|
799 |
static CPUReadMemoryFunc *pci_grackle_read[] = {
|
800 |
&pci_grackle_readb, |
801 |
&pci_grackle_readw, |
802 |
&pci_grackle_readl, |
803 |
}; |
804 |
#endif
|
805 |
|
806 |
/* Uninorth PCI host (for all Mac99 and newer machines */
|
807 |
static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr, |
808 |
uint32_t val) |
809 |
{ |
810 |
PCIBus *s = opaque; |
811 |
int i;
|
812 |
|
813 |
#ifdef TARGET_WORDS_BIGENDIAN
|
814 |
val = bswap32(val); |
815 |
#endif
|
816 |
|
817 |
for (i = 11; i < 32; i++) { |
818 |
if ((val & (1 << i)) != 0) |
819 |
break;
|
820 |
} |
821 |
#if 0
|
822 |
s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
|
823 |
#else
|
824 |
s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11); |
825 |
#endif
|
826 |
} |
827 |
|
828 |
static uint32_t pci_unin_main_config_readl (void *opaque, |
829 |
target_phys_addr_t addr) |
830 |
{ |
831 |
PCIBus *s = opaque; |
832 |
uint32_t val; |
833 |
int devfn;
|
834 |
|
835 |
devfn = (s->config_reg >> 8) & 0xFF; |
836 |
val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC); |
837 |
#ifdef TARGET_WORDS_BIGENDIAN
|
838 |
val = bswap32(val); |
839 |
#endif
|
840 |
|
841 |
return val;
|
842 |
} |
843 |
|
844 |
static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
|
845 |
&pci_unin_main_config_writel, |
846 |
&pci_unin_main_config_writel, |
847 |
&pci_unin_main_config_writel, |
848 |
}; |
849 |
|
850 |
static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
|
851 |
&pci_unin_main_config_readl, |
852 |
&pci_unin_main_config_readl, |
853 |
&pci_unin_main_config_readl, |
854 |
}; |
855 |
|
856 |
static void pci_unin_main_writeb (void *opaque, target_phys_addr_t addr, |
857 |
uint32_t val) |
858 |
{ |
859 |
PCIBus *s = opaque; |
860 |
pci_data_write(s, addr & 7, val, 1); |
861 |
} |
862 |
|
863 |
static void pci_unin_main_writew (void *opaque, target_phys_addr_t addr, |
864 |
uint32_t val) |
865 |
{ |
866 |
PCIBus *s = opaque; |
867 |
#ifdef TARGET_WORDS_BIGENDIAN
|
868 |
val = bswap16(val); |
869 |
#endif
|
870 |
pci_data_write(s, addr & 7, val, 2); |
871 |
} |
872 |
|
873 |
static void pci_unin_main_writel (void *opaque, target_phys_addr_t addr, |
874 |
uint32_t val) |
875 |
{ |
876 |
PCIBus *s = opaque; |
877 |
#ifdef TARGET_WORDS_BIGENDIAN
|
878 |
val = bswap32(val); |
879 |
#endif
|
880 |
pci_data_write(s, addr & 7, val, 4); |
881 |
} |
882 |
|
883 |
static uint32_t pci_unin_main_readb (void *opaque, target_phys_addr_t addr) |
884 |
{ |
885 |
PCIBus *s = opaque; |
886 |
uint32_t val; |
887 |
|
888 |
val = pci_data_read(s, addr & 7, 1); |
889 |
|
890 |
return val;
|
891 |
} |
892 |
|
893 |
static uint32_t pci_unin_main_readw (void *opaque, target_phys_addr_t addr) |
894 |
{ |
895 |
PCIBus *s = opaque; |
896 |
uint32_t val; |
897 |
|
898 |
val = pci_data_read(s, addr & 7, 2); |
899 |
#ifdef TARGET_WORDS_BIGENDIAN
|
900 |
val = bswap16(val); |
901 |
#endif
|
902 |
|
903 |
return val;
|
904 |
} |
905 |
|
906 |
static uint32_t pci_unin_main_readl (void *opaque, target_phys_addr_t addr) |
907 |
{ |
908 |
PCIBus *s = opaque; |
909 |
uint32_t val; |
910 |
|
911 |
val = pci_data_read(s, addr, 4);
|
912 |
#ifdef TARGET_WORDS_BIGENDIAN
|
913 |
val = bswap32(val); |
914 |
#endif
|
915 |
|
916 |
return val;
|
917 |
} |
918 |
|
919 |
static CPUWriteMemoryFunc *pci_unin_main_write[] = {
|
920 |
&pci_unin_main_writeb, |
921 |
&pci_unin_main_writew, |
922 |
&pci_unin_main_writel, |
923 |
}; |
924 |
|
925 |
static CPUReadMemoryFunc *pci_unin_main_read[] = {
|
926 |
&pci_unin_main_readb, |
927 |
&pci_unin_main_readw, |
928 |
&pci_unin_main_readl, |
929 |
}; |
930 |
|
931 |
#if 0
|
932 |
|
933 |
static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
|
934 |
uint32_t val)
|
935 |
{
|
936 |
PCIBus *s = opaque;
|
937 |
|
938 |
#ifdef TARGET_WORDS_BIGENDIAN
|
939 |
val = bswap32(val);
|
940 |
#endif
|
941 |
s->config_reg = 0x80000000 | (val & ~0x00000001); |
942 |
} |
943 |
|
944 |
static uint32_t pci_unin_config_readl (void *opaque, |
945 |
target_phys_addr_t addr) |
946 |
{ |
947 |
PCIBus *s = opaque; |
948 |
uint32_t val; |
949 |
|
950 |
val = (s->config_reg | 0x00000001) & ~0x80000000; |
951 |
#ifdef TARGET_WORDS_BIGENDIAN
|
952 |
val = bswap32(val); |
953 |
#endif
|
954 |
|
955 |
return val;
|
956 |
} |
957 |
|
958 |
static CPUWriteMemoryFunc *pci_unin_config_write[] = {
|
959 |
&pci_unin_config_writel, |
960 |
&pci_unin_config_writel, |
961 |
&pci_unin_config_writel, |
962 |
}; |
963 |
|
964 |
static CPUReadMemoryFunc *pci_unin_config_read[] = {
|
965 |
&pci_unin_config_readl, |
966 |
&pci_unin_config_readl, |
967 |
&pci_unin_config_readl, |
968 |
}; |
969 |
|
970 |
static void pci_unin_writeb (void *opaque, target_phys_addr_t addr, |
971 |
uint32_t val) |
972 |
{ |
973 |
PCIBus *s = opaque; |
974 |
pci_data_write(s, addr & 3, val, 1); |
975 |
} |
976 |
|
977 |
static void pci_unin_writew (void *opaque, target_phys_addr_t addr, |
978 |
uint32_t val) |
979 |
{ |
980 |
PCIBus *s = opaque; |
981 |
#ifdef TARGET_WORDS_BIGENDIAN
|
982 |
val = bswap16(val); |
983 |
#endif
|
984 |
pci_data_write(s, addr & 3, val, 2); |
985 |
} |
986 |
|
987 |
static void pci_unin_writel (void *opaque, target_phys_addr_t addr, |
988 |
uint32_t val) |
989 |
{ |
990 |
PCIBus *s = opaque; |
991 |
#ifdef TARGET_WORDS_BIGENDIAN
|
992 |
val = bswap32(val); |
993 |
#endif
|
994 |
pci_data_write(s, addr & 3, val, 4); |
995 |
} |
996 |
|
997 |
static uint32_t pci_unin_readb (void *opaque, target_phys_addr_t addr) |
998 |
{ |
999 |
PCIBus *s = opaque; |
1000 |
uint32_t val; |
1001 |
|
1002 |
val = pci_data_read(s, addr & 3, 1); |
1003 |
|
1004 |
return val;
|
1005 |
} |
1006 |
|
1007 |
static uint32_t pci_unin_readw (void *opaque, target_phys_addr_t addr) |
1008 |
{ |
1009 |
PCIBus *s = opaque; |
1010 |
uint32_t val; |
1011 |
|
1012 |
val = pci_data_read(s, addr & 3, 2); |
1013 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1014 |
val = bswap16(val); |
1015 |
#endif
|
1016 |
|
1017 |
return val;
|
1018 |
} |
1019 |
|
1020 |
static uint32_t pci_unin_readl (void *opaque, target_phys_addr_t addr) |
1021 |
{ |
1022 |
PCIBus *s = opaque; |
1023 |
uint32_t val; |
1024 |
|
1025 |
val = pci_data_read(s, addr & 3, 4); |
1026 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1027 |
val = bswap32(val); |
1028 |
#endif
|
1029 |
|
1030 |
return val;
|
1031 |
} |
1032 |
|
1033 |
static CPUWriteMemoryFunc *pci_unin_write[] = {
|
1034 |
&pci_unin_writeb, |
1035 |
&pci_unin_writew, |
1036 |
&pci_unin_writel, |
1037 |
}; |
1038 |
|
1039 |
static CPUReadMemoryFunc *pci_unin_read[] = {
|
1040 |
&pci_unin_readb, |
1041 |
&pci_unin_readw, |
1042 |
&pci_unin_readl, |
1043 |
}; |
1044 |
#endif
|
1045 |
|
1046 |
static void pmac_set_irq(PCIDevice *d, int irq_num, int level) |
1047 |
{ |
1048 |
openpic_t *openpic; |
1049 |
/* XXX: we do not simulate the hardware - we rely on the BIOS to
|
1050 |
set correctly for irq line field */
|
1051 |
openpic = d->bus->openpic; |
1052 |
#ifdef TARGET_PPC
|
1053 |
if (openpic)
|
1054 |
openpic_set_irq(openpic, d->config[PCI_INTERRUPT_LINE], level); |
1055 |
#endif
|
1056 |
} |
1057 |
|
1058 |
void pci_pmac_set_openpic(PCIBus *bus, openpic_t *openpic)
|
1059 |
{ |
1060 |
bus->openpic = openpic; |
1061 |
} |
1062 |
|
1063 |
PCIBus *pci_pmac_init(void)
|
1064 |
{ |
1065 |
PCIBus *s; |
1066 |
PCIDevice *d; |
1067 |
int pci_mem_config, pci_mem_data;
|
1068 |
|
1069 |
/* Use values found on a real PowerMac */
|
1070 |
/* Uninorth main bus */
|
1071 |
s = pci_register_bus(); |
1072 |
s->set_irq = pmac_set_irq; |
1073 |
|
1074 |
pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
|
1075 |
pci_unin_main_config_write, s); |
1076 |
pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
|
1077 |
pci_unin_main_write, s); |
1078 |
cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config); |
1079 |
cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data); |
1080 |
s->devfn_min = 11 << 3; |
1081 |
d = pci_register_device(s, "Uni-north main", sizeof(PCIDevice), |
1082 |
11 << 3, NULL, NULL); |
1083 |
d->config[0x00] = 0x6b; // vendor_id : Apple |
1084 |
d->config[0x01] = 0x10; |
1085 |
d->config[0x02] = 0x1F; // device_id |
1086 |
d->config[0x03] = 0x00; |
1087 |
d->config[0x08] = 0x00; // revision |
1088 |
d->config[0x0A] = 0x00; // class_sub = pci host |
1089 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge |
1090 |
d->config[0x0C] = 0x08; // cache_line_size |
1091 |
d->config[0x0D] = 0x10; // latency_timer |
1092 |
d->config[0x0E] = 0x00; // header_type |
1093 |
d->config[0x34] = 0x00; // capabilities_pointer |
1094 |
|
1095 |
#if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly
|
1096 |
/* pci-to-pci bridge */
|
1097 |
d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
|
1098 |
NULL, NULL);
|
1099 |
d->config[0x00] = 0x11; // vendor_id : TI
|
1100 |
d->config[0x01] = 0x10;
|
1101 |
d->config[0x02] = 0x26; // device_id
|
1102 |
d->config[0x03] = 0x00;
|
1103 |
d->config[0x08] = 0x05; // revision
|
1104 |
d->config[0x0A] = 0x04; // class_sub = pci2pci
|
1105 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge
|
1106 |
d->config[0x0C] = 0x08; // cache_line_size
|
1107 |
d->config[0x0D] = 0x20; // latency_timer
|
1108 |
d->config[0x0E] = 0x01; // header_type
|
1109 |
|
1110 |
d->config[0x18] = 0x01; // primary_bus
|
1111 |
d->config[0x19] = 0x02; // secondary_bus
|
1112 |
d->config[0x1A] = 0x02; // subordinate_bus
|
1113 |
d->config[0x1B] = 0x20; // secondary_latency_timer
|
1114 |
d->config[0x1C] = 0x11; // io_base
|
1115 |
d->config[0x1D] = 0x01; // io_limit
|
1116 |
d->config[0x20] = 0x00; // memory_base
|
1117 |
d->config[0x21] = 0x80;
|
1118 |
d->config[0x22] = 0x00; // memory_limit
|
1119 |
d->config[0x23] = 0x80;
|
1120 |
d->config[0x24] = 0x01; // prefetchable_memory_base
|
1121 |
d->config[0x25] = 0x80;
|
1122 |
d->config[0x26] = 0xF1; // prefectchable_memory_limit
|
1123 |
d->config[0x27] = 0x7F;
|
1124 |
// d->config[0x34] = 0xdc // capabilities_pointer
|
1125 |
#endif
|
1126 |
#if 0 // XXX: not needed for now
|
1127 |
/* Uninorth AGP bus */
|
1128 |
s = &pci_bridge[1];
|
1129 |
pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
|
1130 |
pci_unin_config_write, s);
|
1131 |
pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
|
1132 |
pci_unin_write, s);
|
1133 |
cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
|
1134 |
cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
|
1135 |
|
1136 |
d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
|
1137 |
NULL, NULL);
|
1138 |
d->config[0x00] = 0x6b; // vendor_id : Apple
|
1139 |
d->config[0x01] = 0x10;
|
1140 |
d->config[0x02] = 0x20; // device_id
|
1141 |
d->config[0x03] = 0x00;
|
1142 |
d->config[0x08] = 0x00; // revision
|
1143 |
d->config[0x0A] = 0x00; // class_sub = pci host
|
1144 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge
|
1145 |
d->config[0x0C] = 0x08; // cache_line_size
|
1146 |
d->config[0x0D] = 0x10; // latency_timer
|
1147 |
d->config[0x0E] = 0x00; // header_type
|
1148 |
// d->config[0x34] = 0x80; // capabilities_pointer
|
1149 |
#endif
|
1150 |
|
1151 |
#if 0 // XXX: not needed for now
|
1152 |
/* Uninorth internal bus */
|
1153 |
s = &pci_bridge[2];
|
1154 |
pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
|
1155 |
pci_unin_config_write, s);
|
1156 |
pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
|
1157 |
pci_unin_write, s);
|
1158 |
cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
|
1159 |
cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
|
1160 |
|
1161 |
d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
|
1162 |
3, 11 << 3, NULL, NULL);
|
1163 |
d->config[0x00] = 0x6b; // vendor_id : Apple
|
1164 |
d->config[0x01] = 0x10;
|
1165 |
d->config[0x02] = 0x1E; // device_id
|
1166 |
d->config[0x03] = 0x00;
|
1167 |
d->config[0x08] = 0x00; // revision
|
1168 |
d->config[0x0A] = 0x00; // class_sub = pci host
|
1169 |
d->config[0x0B] = 0x06; // class_base = PCI_bridge
|
1170 |
d->config[0x0C] = 0x08; // cache_line_size
|
1171 |
d->config[0x0D] = 0x10; // latency_timer
|
1172 |
d->config[0x0E] = 0x00; // header_type
|
1173 |
d->config[0x34] = 0x00; // capabilities_pointer
|
1174 |
#endif
|
1175 |
|
1176 |
#if 0 // Grackle ?
|
1177 |
/* same values as PearPC - check this */
|
1178 |
d->config[0x00] = 0x11; // vendor_id
|
1179 |
d->config[0x01] = 0x10;
|
1180 |
d->config[0x02] = 0x26; // device_id
|
1181 |
d->config[0x03] = 0x00;
|
1182 |
d->config[0x08] = 0x02; // revision
|
1183 |
d->config[0x0a] = 0x04; // class_sub = pci2pci
|
1184 |
d->config[0x0b] = 0x06; // class_base = PCI_bridge
|
1185 |
d->config[0x0e] = 0x01; // header_type
|
1186 |
|
1187 |
d->config[0x18] = 0x0; // primary_bus
|
1188 |
d->config[0x19] = 0x1; // secondary_bus
|
1189 |
d->config[0x1a] = 0x1; // subordinate_bus
|
1190 |
d->config[0x1c] = 0x10; // io_base
|
1191 |
d->config[0x1d] = 0x20; // io_limit
|
1192 |
|
1193 |
d->config[0x20] = 0x80; // memory_base
|
1194 |
d->config[0x21] = 0x80;
|
1195 |
d->config[0x22] = 0x90; // memory_limit
|
1196 |
d->config[0x23] = 0x80;
|
1197 |
|
1198 |
d->config[0x24] = 0x00; // prefetchable_memory_base
|
1199 |
d->config[0x25] = 0x84;
|
1200 |
d->config[0x26] = 0x00; // prefetchable_memory_limit
|
1201 |
d->config[0x27] = 0x85;
|
1202 |
#endif
|
1203 |
return s;
|
1204 |
} |
1205 |
|
1206 |
/***********************************************************/
|
1207 |
/* generic PCI irq support */
|
1208 |
|
1209 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
1210 |
void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level) |
1211 |
{ |
1212 |
PCIBus *bus = pci_dev->bus; |
1213 |
bus->set_irq(pci_dev, irq_num, level); |
1214 |
} |
1215 |
|
1216 |
/***********************************************************/
|
1217 |
/* monitor info on PCI */
|
1218 |
|
1219 |
static void pci_info_device(PCIDevice *d) |
1220 |
{ |
1221 |
int i, class;
|
1222 |
PCIIORegion *r; |
1223 |
|
1224 |
printf(" Bus %2d, device %3d, function %d:\n",
|
1225 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
1226 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
1227 |
printf(" ");
|
1228 |
switch(class) {
|
1229 |
case 0x0101: |
1230 |
printf("IDE controller");
|
1231 |
break;
|
1232 |
case 0x0200: |
1233 |
printf("Ethernet controller");
|
1234 |
break;
|
1235 |
case 0x0300: |
1236 |
printf("VGA controller");
|
1237 |
break;
|
1238 |
default:
|
1239 |
printf("Class %04x", class);
|
1240 |
break;
|
1241 |
} |
1242 |
printf(": PCI device %04x:%04x\n",
|
1243 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
1244 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
1245 |
|
1246 |
if (d->config[PCI_INTERRUPT_PIN] != 0) { |
1247 |
printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
1248 |
} |
1249 |
for(i = 0;i < PCI_NUM_REGIONS; i++) { |
1250 |
r = &d->io_regions[i]; |
1251 |
if (r->size != 0) { |
1252 |
printf(" BAR%d: ", i);
|
1253 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
1254 |
printf("I/O at 0x%04x [0x%04x].\n",
|
1255 |
r->addr, r->addr + r->size - 1);
|
1256 |
} else {
|
1257 |
printf("32 bit memory at 0x%08x [0x%08x].\n",
|
1258 |
r->addr, r->addr + r->size - 1);
|
1259 |
} |
1260 |
} |
1261 |
} |
1262 |
} |
1263 |
|
1264 |
void pci_info(void) |
1265 |
{ |
1266 |
PCIBus *bus = first_bus; |
1267 |
PCIDevice *d; |
1268 |
int devfn;
|
1269 |
|
1270 |
if (bus) {
|
1271 |
for(devfn = 0; devfn < 256; devfn++) { |
1272 |
d = bus->devices[devfn]; |
1273 |
if (d)
|
1274 |
pci_info_device(d); |
1275 |
} |
1276 |
} |
1277 |
} |
1278 |
|
1279 |
/***********************************************************/
|
1280 |
/* XXX: the following should be moved to the PC BIOS */
|
1281 |
|
1282 |
static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
|
1283 |
{ |
1284 |
return cpu_inb(cpu_single_env, addr);
|
1285 |
} |
1286 |
|
1287 |
static void isa_outb(uint32_t val, uint32_t addr) |
1288 |
{ |
1289 |
cpu_outb(cpu_single_env, addr, val); |
1290 |
} |
1291 |
|
1292 |
static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
|
1293 |
{ |
1294 |
return cpu_inw(cpu_single_env, addr);
|
1295 |
} |
1296 |
|
1297 |
static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr) |
1298 |
{ |
1299 |
cpu_outw(cpu_single_env, addr, val); |
1300 |
} |
1301 |
|
1302 |
static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
|
1303 |
{ |
1304 |
return cpu_inl(cpu_single_env, addr);
|
1305 |
} |
1306 |
|
1307 |
static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr) |
1308 |
{ |
1309 |
cpu_outl(cpu_single_env, addr, val); |
1310 |
} |
1311 |
|
1312 |
static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val) |
1313 |
{ |
1314 |
PCIBus *s = d->bus; |
1315 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1316 |
(d->devfn << 8) | addr;
|
1317 |
pci_data_write(s, 0, val, 4); |
1318 |
} |
1319 |
|
1320 |
static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val) |
1321 |
{ |
1322 |
PCIBus *s = d->bus; |
1323 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1324 |
(d->devfn << 8) | (addr & ~3); |
1325 |
pci_data_write(s, addr & 3, val, 2); |
1326 |
} |
1327 |
|
1328 |
static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val) |
1329 |
{ |
1330 |
PCIBus *s = d->bus; |
1331 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1332 |
(d->devfn << 8) | (addr & ~3); |
1333 |
pci_data_write(s, addr & 3, val, 1); |
1334 |
} |
1335 |
|
1336 |
static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
|
1337 |
{ |
1338 |
PCIBus *s = d->bus; |
1339 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1340 |
(d->devfn << 8) | addr;
|
1341 |
return pci_data_read(s, 0, 4); |
1342 |
} |
1343 |
|
1344 |
static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
|
1345 |
{ |
1346 |
PCIBus *s = d->bus; |
1347 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1348 |
(d->devfn << 8) | (addr & ~3); |
1349 |
return pci_data_read(s, addr & 3, 2); |
1350 |
} |
1351 |
|
1352 |
static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
|
1353 |
{ |
1354 |
PCIBus *s = d->bus; |
1355 |
s->config_reg = 0x80000000 | (s->bus_num << 16) | |
1356 |
(d->devfn << 8) | (addr & ~3); |
1357 |
return pci_data_read(s, addr & 3, 1); |
1358 |
} |
1359 |
|
1360 |
static uint32_t pci_bios_io_addr;
|
1361 |
static uint32_t pci_bios_mem_addr;
|
1362 |
/* host irqs corresponding to PCI irqs A-D */
|
1363 |
static uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; |
1364 |
|
1365 |
static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr) |
1366 |
{ |
1367 |
PCIIORegion *r; |
1368 |
uint16_t cmd; |
1369 |
uint32_t ofs; |
1370 |
|
1371 |
if ( region_num == PCI_ROM_SLOT ) {
|
1372 |
ofs = 0x30;
|
1373 |
}else{
|
1374 |
ofs = 0x10 + region_num * 4; |
1375 |
} |
1376 |
|
1377 |
pci_config_writel(d, ofs, addr); |
1378 |
r = &d->io_regions[region_num]; |
1379 |
|
1380 |
/* enable memory mappings */
|
1381 |
cmd = pci_config_readw(d, PCI_COMMAND); |
1382 |
if ( region_num == PCI_ROM_SLOT )
|
1383 |
cmd |= 2;
|
1384 |
else if (r->type & PCI_ADDRESS_SPACE_IO) |
1385 |
cmd |= 1;
|
1386 |
else
|
1387 |
cmd |= 2;
|
1388 |
pci_config_writew(d, PCI_COMMAND, cmd); |
1389 |
} |
1390 |
|
1391 |
static void pci_bios_init_device(PCIDevice *d) |
1392 |
{ |
1393 |
int class;
|
1394 |
PCIIORegion *r; |
1395 |
uint32_t *paddr; |
1396 |
int i, pin, pic_irq, vendor_id, device_id;
|
1397 |
|
1398 |
class = pci_config_readw(d, PCI_CLASS_DEVICE); |
1399 |
vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
1400 |
device_id = pci_config_readw(d, PCI_DEVICE_ID); |
1401 |
switch(class) {
|
1402 |
case 0x0101: |
1403 |
if (vendor_id == 0x8086 && device_id == 0x7010) { |
1404 |
/* PIIX3 IDE */
|
1405 |
pci_config_writew(d, 0x40, 0x8000); // enable IDE0 |
1406 |
pci_config_writew(d, 0x42, 0x8000); // enable IDE1 |
1407 |
goto default_map;
|
1408 |
} else {
|
1409 |
/* IDE: we map it as in ISA mode */
|
1410 |
pci_set_io_region_addr(d, 0, 0x1f0); |
1411 |
pci_set_io_region_addr(d, 1, 0x3f4); |
1412 |
pci_set_io_region_addr(d, 2, 0x170); |
1413 |
pci_set_io_region_addr(d, 3, 0x374); |
1414 |
} |
1415 |
break;
|
1416 |
case 0x0300: |
1417 |
if (vendor_id != 0x1234) |
1418 |
goto default_map;
|
1419 |
/* VGA: map frame buffer to default Bochs VBE address */
|
1420 |
pci_set_io_region_addr(d, 0, 0xE0000000); |
1421 |
break;
|
1422 |
case 0x0800: |
1423 |
/* PIC */
|
1424 |
vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
1425 |
device_id = pci_config_readw(d, PCI_DEVICE_ID); |
1426 |
if (vendor_id == 0x1014) { |
1427 |
/* IBM */
|
1428 |
if (device_id == 0x0046 || device_id == 0xFFFF) { |
1429 |
/* MPIC & MPIC2 */
|
1430 |
pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000); |
1431 |
} |
1432 |
} |
1433 |
break;
|
1434 |
case 0xff00: |
1435 |
if (vendor_id == 0x0106b && |
1436 |
(device_id == 0x0017 || device_id == 0x0022)) { |
1437 |
/* macio bridge */
|
1438 |
pci_set_io_region_addr(d, 0, 0x80800000); |
1439 |
} |
1440 |
break;
|
1441 |
default:
|
1442 |
default_map:
|
1443 |
/* default memory mappings */
|
1444 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
1445 |
r = &d->io_regions[i]; |
1446 |
if (r->size) {
|
1447 |
if (r->type & PCI_ADDRESS_SPACE_IO)
|
1448 |
paddr = &pci_bios_io_addr; |
1449 |
else
|
1450 |
paddr = &pci_bios_mem_addr; |
1451 |
*paddr = (*paddr + r->size - 1) & ~(r->size - 1); |
1452 |
pci_set_io_region_addr(d, i, *paddr); |
1453 |
*paddr += r->size; |
1454 |
} |
1455 |
} |
1456 |
break;
|
1457 |
} |
1458 |
|
1459 |
/* map the interrupt */
|
1460 |
pin = pci_config_readb(d, PCI_INTERRUPT_PIN); |
1461 |
if (pin != 0) { |
1462 |
pin = pci_slot_get_pirq(d, pin - 1);
|
1463 |
pic_irq = pci_irqs[pin]; |
1464 |
pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq); |
1465 |
} |
1466 |
} |
1467 |
|
1468 |
/*
|
1469 |
* This function initializes the PCI devices as a normal PCI BIOS
|
1470 |
* would do. It is provided just in case the BIOS has no support for
|
1471 |
* PCI.
|
1472 |
*/
|
1473 |
void pci_bios_init(void) |
1474 |
{ |
1475 |
PCIBus *bus; |
1476 |
PCIDevice *d; |
1477 |
int devfn, i, irq;
|
1478 |
uint8_t elcr[2];
|
1479 |
|
1480 |
pci_bios_io_addr = 0xc000;
|
1481 |
pci_bios_mem_addr = 0xf0000000;
|
1482 |
|
1483 |
/* activate IRQ mappings */
|
1484 |
elcr[0] = 0x00; |
1485 |
elcr[1] = 0x00; |
1486 |
for(i = 0; i < 4; i++) { |
1487 |
irq = pci_irqs[i]; |
1488 |
/* set to trigger level */
|
1489 |
elcr[irq >> 3] |= (1 << (irq & 7)); |
1490 |
/* activate irq remapping in PIIX */
|
1491 |
pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
|
1492 |
} |
1493 |
isa_outb(elcr[0], 0x4d0); |
1494 |
isa_outb(elcr[1], 0x4d1); |
1495 |
|
1496 |
bus = first_bus; |
1497 |
if (bus) {
|
1498 |
for(devfn = 0; devfn < 256; devfn++) { |
1499 |
d = bus->devices[devfn]; |
1500 |
if (d)
|
1501 |
pci_bios_init_device(d); |
1502 |
} |
1503 |
} |
1504 |
} |