Revision d26bc211 target-mips/translate.c
b/target-mips/translate.c | ||
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590 | 590 |
} \ |
591 | 591 |
} while (0) |
592 | 592 |
|
593 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
593 |
#if defined(TARGET_MIPS64) |
|
594 | 594 |
#define GEN_LOAD_IMM_TN(Tn, Imm) \ |
595 | 595 |
do { \ |
596 | 596 |
if (Imm == 0) { \ |
... | ... | |
638 | 638 |
|
639 | 639 |
static always_inline void gen_save_pc(target_ulong pc) |
640 | 640 |
{ |
641 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
641 |
#if defined(TARGET_MIPS64) |
|
642 | 642 |
if (pc == (int32_t)pc) { |
643 | 643 |
gen_op_save_pc(pc); |
644 | 644 |
} else { |
... | ... | |
651 | 651 |
|
652 | 652 |
static always_inline void gen_save_btarget(target_ulong btarget) |
653 | 653 |
{ |
654 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
654 |
#if defined(TARGET_MIPS64) |
|
655 | 655 |
if (btarget == (int32_t)btarget) { |
656 | 656 |
gen_op_save_btarget(btarget); |
657 | 657 |
} else { |
... | ... | |
802 | 802 |
} |
803 | 803 |
#endif |
804 | 804 |
|
805 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
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|
805 |
#if defined(TARGET_MIPS64) |
|
806 | 806 |
OP_LD_TABLE(d); |
807 | 807 |
OP_LD_TABLE(dl); |
808 | 808 |
OP_LD_TABLE(dr); |
... | ... | |
852 | 852 |
/* Don't do NOP if destination is zero: we must perform the actual |
853 | 853 |
memory access. */ |
854 | 854 |
switch (opc) { |
855 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
855 |
#if defined(TARGET_MIPS64) |
|
856 | 856 |
case OPC_LWU: |
857 | 857 |
op_ldst(lwu); |
858 | 858 |
GEN_STORE_TN_REG(rt, T0); |
... | ... | |
1048 | 1048 |
switch (opc) { |
1049 | 1049 |
case OPC_ADDI: |
1050 | 1050 |
case OPC_ADDIU: |
1051 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
1051 |
#if defined(TARGET_MIPS64) |
|
1052 | 1052 |
case OPC_DADDI: |
1053 | 1053 |
case OPC_DADDIU: |
1054 | 1054 |
#endif |
... | ... | |
1068 | 1068 |
case OPC_SLL: |
1069 | 1069 |
case OPC_SRA: |
1070 | 1070 |
case OPC_SRL: |
1071 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
1071 |
#if defined(TARGET_MIPS64) |
|
1072 | 1072 |
case OPC_DSLL: |
1073 | 1073 |
case OPC_DSRA: |
1074 | 1074 |
case OPC_DSRL: |
... | ... | |
1091 | 1091 |
gen_op_add(); |
1092 | 1092 |
opn = "addiu"; |
1093 | 1093 |
break; |
1094 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
1094 |
#if defined(TARGET_MIPS64) |
|
1095 | 1095 |
case OPC_DADDI: |
1096 | 1096 |
save_cpu_state(ctx, 1); |
1097 | 1097 |
gen_op_daddo(); |
... | ... | |
1155 | 1155 |
break; |
1156 | 1156 |
} |
1157 | 1157 |
break; |
1158 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
1158 |
#if defined(TARGET_MIPS64) |
|
1159 | 1159 |
case OPC_DSLL: |
1160 | 1160 |
gen_op_dsll(); |
1161 | 1161 |
opn = "dsll"; |
... | ... | |
1260 | 1260 |
gen_op_sub(); |
1261 | 1261 |
opn = "subu"; |
1262 | 1262 |
break; |
1263 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
1263 |
#if defined(TARGET_MIPS64) |
|
1264 | 1264 |
case OPC_DADD: |
1265 | 1265 |
save_cpu_state(ctx, 1); |
1266 | 1266 |
gen_op_daddo(); |
... | ... | |
1346 | 1346 |
break; |
1347 | 1347 |
} |
1348 | 1348 |
break; |
1349 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
1349 |
#if defined(TARGET_MIPS64) |
|
1350 | 1350 |
case OPC_DSLLV: |
1351 | 1351 |
gen_op_dsllv(); |
1352 | 1352 |
opn = "dsllv"; |
... | ... | |
1451 | 1451 |
gen_op_multu(); |
1452 | 1452 |
opn = "multu"; |
1453 | 1453 |
break; |
1454 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
1454 |
#if defined(TARGET_MIPS64) |
|
1455 | 1455 |
case OPC_DDIV: |
1456 | 1456 |
gen_op_ddiv(); |
1457 | 1457 |
opn = "ddiv"; |
... | ... | |
1512 | 1512 |
gen_op_clz(); |
1513 | 1513 |
opn = "clz"; |
1514 | 1514 |
break; |
1515 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
1515 |
#if defined(TARGET_MIPS64) |
|
1516 | 1516 |
case OPC_DCLO: |
1517 | 1517 |
gen_op_dclo(); |
1518 | 1518 |
opn = "dclo"; |
... | ... | |
2319 | 2319 |
case 20: |
2320 | 2320 |
switch (sel) { |
2321 | 2321 |
case 0: |
2322 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
2322 |
#if defined(TARGET_MIPS64) |
|
2323 | 2323 |
check_insn(env, ctx, ISA_MIPS3); |
2324 | 2324 |
gen_op_mfc0_xcontext(); |
2325 | 2325 |
rn = "XContext"; |
... | ... | |
2901 | 2901 |
case 20: |
2902 | 2902 |
switch (sel) { |
2903 | 2903 |
case 0: |
2904 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
2904 |
#if defined(TARGET_MIPS64) |
|
2905 | 2905 |
check_insn(env, ctx, ISA_MIPS3); |
2906 | 2906 |
gen_op_mtc0_xcontext(); |
2907 | 2907 |
rn = "XContext"; |
... | ... | |
3111 | 3111 |
generate_exception(ctx, EXCP_RI); |
3112 | 3112 |
} |
3113 | 3113 |
|
3114 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
3114 |
#if defined(TARGET_MIPS64) |
|
3115 | 3115 |
static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) |
3116 | 3116 |
{ |
3117 | 3117 |
const char *rn = "invalid"; |
... | ... | |
4254 | 4254 |
#endif |
4255 | 4255 |
generate_exception(ctx, EXCP_RI); |
4256 | 4256 |
} |
4257 |
#endif /* TARGET_MIPSN32 || TARGET_MIPS64 */
|
|
4257 |
#endif /* TARGET_MIPS64 */ |
|
4258 | 4258 |
|
4259 | 4259 |
static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, |
4260 | 4260 |
int u, int sel, int h) |
... | ... | |
4604 | 4604 |
gen_mtc0(env, ctx, rd, ctx->opcode & 0x7); |
4605 | 4605 |
opn = "mtc0"; |
4606 | 4606 |
break; |
4607 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
4607 |
#if defined(TARGET_MIPS64) |
|
4608 | 4608 |
case OPC_DMFC0: |
4609 | 4609 |
check_insn(env, ctx, ISA_MIPS3); |
4610 | 4610 |
if (rt == 0) { |
... | ... | |
5877 | 5877 |
/* MIPS16 extension to MIPS32 */ |
5878 | 5878 |
/* SmartMIPS extension to MIPS32 */ |
5879 | 5879 |
|
5880 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
5880 |
#if defined(TARGET_MIPS64) |
|
5881 | 5881 |
|
5882 | 5882 |
/* MDMX extension to MIPS64 */ |
5883 | 5883 |
|
... | ... | |
5987 | 5987 |
} |
5988 | 5988 |
break; |
5989 | 5989 |
|
5990 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
5990 |
#if defined(TARGET_MIPS64) |
|
5991 | 5991 |
/* MIPS64 specific opcodes */ |
5992 | 5992 |
case OPC_DSLL: |
5993 | 5993 |
case OPC_DSRL ... OPC_DSRA: |
... | ... | |
6043 | 6043 |
} |
6044 | 6044 |
/* Treat as NOP. */ |
6045 | 6045 |
break; |
6046 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
6046 |
#if defined(TARGET_MIPS64) |
|
6047 | 6047 |
case OPC_DCLZ ... OPC_DCLO: |
6048 | 6048 |
check_insn(env, ctx, ISA_MIPS64); |
6049 | 6049 |
check_mips_64(ctx); |
... | ... | |
6130 | 6130 |
gen_op_yield(); |
6131 | 6131 |
GEN_STORE_TN_REG(rd, T0); |
6132 | 6132 |
break; |
6133 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
6133 |
#if defined(TARGET_MIPS64) |
|
6134 | 6134 |
case OPC_DEXTM ... OPC_DEXT: |
6135 | 6135 |
case OPC_DINSM ... OPC_DINS: |
6136 | 6136 |
check_insn(env, ctx, ISA_MIPS64R2); |
... | ... | |
6192 | 6192 |
case OPC_MTC0: |
6193 | 6193 |
case OPC_MFTR: |
6194 | 6194 |
case OPC_MTTR: |
6195 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
6195 |
#if defined(TARGET_MIPS64) |
|
6196 | 6196 |
case OPC_DMFC0: |
6197 | 6197 |
case OPC_DMTC0: |
6198 | 6198 |
#endif |
... | ... | |
6313 | 6313 |
case OPC_CTC1: |
6314 | 6314 |
gen_cp1(ctx, op1, rt, rd); |
6315 | 6315 |
break; |
6316 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
6316 |
#if defined(TARGET_MIPS64) |
|
6317 | 6317 |
case OPC_DMFC1: |
6318 | 6318 |
case OPC_DMTC1: |
6319 | 6319 |
check_insn(env, ctx, ISA_MIPS3); |
... | ... | |
6398 | 6398 |
} |
6399 | 6399 |
break; |
6400 | 6400 |
|
6401 |
#if defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)
|
|
6401 |
#if defined(TARGET_MIPS64) |
|
6402 | 6402 |
/* MIPS64 opcodes */ |
6403 | 6403 |
case OPC_LWU: |
6404 | 6404 |
case OPC_LDL ... OPC_LDR: |
... | ... | |
6665 | 6665 |
} |
6666 | 6666 |
} |
6667 | 6667 |
|
6668 |
#if (defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
|
|
6668 |
#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
|
|
6669 | 6669 |
/* Debug help: The architecture requires 32bit code to maintain proper |
6670 | 6670 |
sign-extened values on 64bit machines. */ |
6671 | 6671 |
|
... | ... | |
6720 | 6720 |
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); |
6721 | 6721 |
if (env->hflags & MIPS_HFLAG_FPU) |
6722 | 6722 |
fpu_dump_state(env, f, cpu_fprintf, flags); |
6723 |
#if (defined(TARGET_MIPSN32) || defined(TARGET_MIPS64)) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
|
|
6723 |
#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
|
|
6724 | 6724 |
cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags); |
6725 | 6725 |
#endif |
6726 | 6726 |
} |
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