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/*
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* QEMU Floppy disk emulator (Intel 82078)
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*
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* Copyright (c) 2003, 2007 Jocelyn Mayer
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* Copyright (c) 2008 Herv? Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* The controller is used in Sun4m systems in a slightly different
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* way. There are changes in DOR register and DMA is not available.
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*/
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#include "hw.h" |
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#include "fdc.h" |
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#include "qemu-error.h" |
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#include "qemu-timer.h" |
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#include "isa.h" |
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#include "sysbus.h" |
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#include "qdev-addr.h" |
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#include "blockdev.h" |
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#include "sysemu.h" |
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/********************************************************/
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/* debug Floppy devices */
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//#define DEBUG_FLOPPY
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#ifdef DEBUG_FLOPPY
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#define FLOPPY_DPRINTF(fmt, ...) \
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do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define FLOPPY_DPRINTF(fmt, ...)
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#endif
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|
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#define FLOPPY_ERROR(fmt, ...) \
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do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) |
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|
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/********************************************************/
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/* Floppy drive emulation */
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|
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#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
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#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
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/* Will always be a fixed parameter for us */
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#define FD_SECTOR_LEN 512 |
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#define FD_SECTOR_SC 2 /* Sector size code */ |
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#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */ |
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|
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/* Floppy disk drive emulation */
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typedef enum FDiskFlags { |
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FDISK_DBL_SIDES = 0x01,
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} FDiskFlags; |
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|
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typedef struct FDrive { |
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BlockDriverState *bs; |
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/* Drive status */
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FDriveType drive; |
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uint8_t perpendicular; /* 2.88 MB access mode */
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/* Position */
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uint8_t head; |
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uint8_t track; |
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uint8_t sect; |
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/* Media */
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FDiskFlags flags; |
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uint8_t last_sect; /* Nb sector per track */
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uint8_t max_track; /* Nb of tracks */
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uint16_t bps; /* Bytes per sector */
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uint8_t ro; /* Is read-only */
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} FDrive; |
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|
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static void fd_init(FDrive *drv) |
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{
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/* Drive */
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drv->drive = FDRIVE_DRV_NONE; |
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drv->perpendicular = 0;
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/* Disk */
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drv->last_sect = 0;
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drv->max_track = 0;
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} |
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static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect, |
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uint8_t last_sect) |
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{
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return (((track * 2) + head) * last_sect) + sect - 1; |
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} |
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|
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/* Returns current position, in sectors, for given drive */
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static int fd_sector(FDrive *drv) |
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{
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return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
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} |
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/* Seek to a new position:
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* returns 0 if already on right track
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* returns 1 if track changed
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* returns 2 if track is invalid
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* returns 3 if sector is invalid
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* returns 4 if seek is disabled
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*/
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static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect, |
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int enable_seek)
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{
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uint32_t sector; |
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int ret;
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if (track > drv->max_track ||
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(head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) { |
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FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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head, track, sect, 1,
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(drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, |
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drv->max_track, drv->last_sect); |
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return 2; |
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} |
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if (sect > drv->last_sect) {
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FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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head, track, sect, 1,
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(drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1, |
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drv->max_track, drv->last_sect); |
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return 3; |
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} |
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sector = fd_sector_calc(head, track, sect, drv->last_sect); |
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ret = 0;
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if (sector != fd_sector(drv)) {
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#if 0
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if (!enable_seek) {
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FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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head, track, sect, 1, drv->max_track, drv->last_sect);
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return 4;
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}
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#endif
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drv->head = head; |
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if (drv->track != track)
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ret = 1;
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drv->track = track; |
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drv->sect = sect; |
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} |
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return ret;
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} |
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/* Set drive back to track 0 */
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static void fd_recalibrate(FDrive *drv) |
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{
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FLOPPY_DPRINTF("recalibrate\n");
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drv->head = 0;
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drv->track = 0;
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drv->sect = 1;
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} |
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/* Revalidate a disk drive after a disk change */
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static void fd_revalidate(FDrive *drv) |
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{
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int nb_heads, max_track, last_sect, ro;
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FDriveType drive; |
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FLOPPY_DPRINTF("revalidate\n");
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if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) { |
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ro = bdrv_is_read_only(drv->bs); |
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bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track, |
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&last_sect, drv->drive, &drive); |
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if (nb_heads != 0 && max_track != 0 && last_sect != 0) { |
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FLOPPY_DPRINTF("User defined disk (%d %d %d)",
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nb_heads - 1, max_track, last_sect);
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} else {
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FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
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max_track, last_sect, ro ? "ro" : "rw"); |
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} |
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if (nb_heads == 1) { |
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drv->flags &= ~FDISK_DBL_SIDES; |
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} else {
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drv->flags |= FDISK_DBL_SIDES; |
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} |
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drv->max_track = max_track; |
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drv->last_sect = last_sect; |
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drv->ro = ro; |
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drv->drive = drive; |
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} else {
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FLOPPY_DPRINTF("No disk in drive\n");
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drv->last_sect = 0;
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drv->max_track = 0;
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drv->flags &= ~FDISK_DBL_SIDES; |
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} |
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} |
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|
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/********************************************************/
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/* Intel 82078 floppy disk controller emulation */
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static void fdctrl_reset(FDCtrl *fdctrl, int do_irq); |
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static void fdctrl_reset_fifo(FDCtrl *fdctrl); |
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static int fdctrl_transfer_handler (void *opaque, int nchan, |
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int dma_pos, int dma_len); |
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static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0); |
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static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
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static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
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static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
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static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value); |
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static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
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static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value); |
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static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
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static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value); |
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static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
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static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value); |
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static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
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enum {
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FD_DIR_WRITE = 0,
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FD_DIR_READ = 1,
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FD_DIR_SCANE = 2,
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FD_DIR_SCANL = 3,
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FD_DIR_SCANH = 4,
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}; |
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|
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enum {
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FD_STATE_MULTI = 0x01, /* multi track flag */ |
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FD_STATE_FORMAT = 0x02, /* format flag */ |
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FD_STATE_SEEK = 0x04, /* seek flag */ |
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}; |
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|
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enum {
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FD_REG_SRA = 0x00,
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FD_REG_SRB = 0x01,
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FD_REG_DOR = 0x02,
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FD_REG_TDR = 0x03,
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FD_REG_MSR = 0x04,
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FD_REG_DSR = 0x04,
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FD_REG_FIFO = 0x05,
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FD_REG_DIR = 0x07,
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}; |
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|
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enum {
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FD_CMD_READ_TRACK = 0x02,
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FD_CMD_SPECIFY = 0x03,
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FD_CMD_SENSE_DRIVE_STATUS = 0x04,
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FD_CMD_WRITE = 0x05,
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FD_CMD_READ = 0x06,
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FD_CMD_RECALIBRATE = 0x07,
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FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
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FD_CMD_WRITE_DELETED = 0x09,
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FD_CMD_READ_ID = 0x0a,
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FD_CMD_READ_DELETED = 0x0c,
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FD_CMD_FORMAT_TRACK = 0x0d,
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FD_CMD_DUMPREG = 0x0e,
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FD_CMD_SEEK = 0x0f,
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FD_CMD_VERSION = 0x10,
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FD_CMD_SCAN_EQUAL = 0x11,
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FD_CMD_PERPENDICULAR_MODE = 0x12,
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FD_CMD_CONFIGURE = 0x13,
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FD_CMD_LOCK = 0x14,
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FD_CMD_VERIFY = 0x16,
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FD_CMD_POWERDOWN_MODE = 0x17,
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FD_CMD_PART_ID = 0x18,
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FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
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FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
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FD_CMD_SAVE = 0x2e,
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FD_CMD_OPTION = 0x33,
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FD_CMD_RESTORE = 0x4e,
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FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
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FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
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FD_CMD_FORMAT_AND_WRITE = 0xcd,
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FD_CMD_RELATIVE_SEEK_IN = 0xcf,
|
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}; |
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|
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enum {
|
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FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */ |
| 282 |
FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */ |
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FD_CONFIG_POLL = 0x10, /* Poll enabled */ |
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FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */ |
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FD_CONFIG_EIS = 0x40, /* No implied seeks */ |
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}; |
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|
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enum {
|
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FD_SR0_EQPMT = 0x10,
|
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FD_SR0_SEEK = 0x20,
|
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FD_SR0_ABNTERM = 0x40,
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FD_SR0_INVCMD = 0x80,
|
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FD_SR0_RDYCHG = 0xc0,
|
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}; |
| 295 |
|
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enum {
|
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FD_SR1_EC = 0x80, /* End of cylinder */ |
| 298 |
}; |
| 299 |
|
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enum {
|
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FD_SR2_SNS = 0x04, /* Scan not satisfied */ |
| 302 |
FD_SR2_SEH = 0x08, /* Scan equal hit */ |
| 303 |
}; |
| 304 |
|
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enum {
|
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FD_SRA_DIR = 0x01,
|
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FD_SRA_nWP = 0x02,
|
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FD_SRA_nINDX = 0x04,
|
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FD_SRA_HDSEL = 0x08,
|
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FD_SRA_nTRK0 = 0x10,
|
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FD_SRA_STEP = 0x20,
|
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FD_SRA_nDRV2 = 0x40,
|
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FD_SRA_INTPEND = 0x80,
|
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}; |
| 315 |
|
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enum {
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FD_SRB_MTR0 = 0x01,
|
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FD_SRB_MTR1 = 0x02,
|
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FD_SRB_WGATE = 0x04,
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FD_SRB_RDATA = 0x08,
|
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FD_SRB_WDATA = 0x10,
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FD_SRB_DR0 = 0x20,
|
| 323 |
}; |
| 324 |
|
| 325 |
enum {
|
| 326 |
#if MAX_FD == 4 |
| 327 |
FD_DOR_SELMASK = 0x03,
|
| 328 |
#else
|
| 329 |
FD_DOR_SELMASK = 0x01,
|
| 330 |
#endif
|
| 331 |
FD_DOR_nRESET = 0x04,
|
| 332 |
FD_DOR_DMAEN = 0x08,
|
| 333 |
FD_DOR_MOTEN0 = 0x10,
|
| 334 |
FD_DOR_MOTEN1 = 0x20,
|
| 335 |
FD_DOR_MOTEN2 = 0x40,
|
| 336 |
FD_DOR_MOTEN3 = 0x80,
|
| 337 |
}; |
| 338 |
|
| 339 |
enum {
|
| 340 |
#if MAX_FD == 4 |
| 341 |
FD_TDR_BOOTSEL = 0x0c,
|
| 342 |
#else
|
| 343 |
FD_TDR_BOOTSEL = 0x04,
|
| 344 |
#endif
|
| 345 |
}; |
| 346 |
|
| 347 |
enum {
|
| 348 |
FD_DSR_DRATEMASK= 0x03,
|
| 349 |
FD_DSR_PWRDOWN = 0x40,
|
| 350 |
FD_DSR_SWRESET = 0x80,
|
| 351 |
}; |
| 352 |
|
| 353 |
enum {
|
| 354 |
FD_MSR_DRV0BUSY = 0x01,
|
| 355 |
FD_MSR_DRV1BUSY = 0x02,
|
| 356 |
FD_MSR_DRV2BUSY = 0x04,
|
| 357 |
FD_MSR_DRV3BUSY = 0x08,
|
| 358 |
FD_MSR_CMDBUSY = 0x10,
|
| 359 |
FD_MSR_NONDMA = 0x20,
|
| 360 |
FD_MSR_DIO = 0x40,
|
| 361 |
FD_MSR_RQM = 0x80,
|
| 362 |
}; |
| 363 |
|
| 364 |
enum {
|
| 365 |
FD_DIR_DSKCHG = 0x80,
|
| 366 |
}; |
| 367 |
|
| 368 |
#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
|
| 369 |
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
|
| 370 |
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
|
| 371 |
|
| 372 |
struct FDCtrl {
|
| 373 |
/* Controller's identification */
|
| 374 |
uint8_t version; |
| 375 |
/* HW */
|
| 376 |
qemu_irq irq; |
| 377 |
int dma_chann;
|
| 378 |
/* Controller state */
|
| 379 |
QEMUTimer *result_timer; |
| 380 |
uint8_t sra; |
| 381 |
uint8_t srb; |
| 382 |
uint8_t dor; |
| 383 |
uint8_t dor_vmstate; /* only used as temp during vmstate */
|
| 384 |
uint8_t tdr; |
| 385 |
uint8_t dsr; |
| 386 |
uint8_t msr; |
| 387 |
uint8_t cur_drv; |
| 388 |
uint8_t status0; |
| 389 |
uint8_t status1; |
| 390 |
uint8_t status2; |
| 391 |
/* Command FIFO */
|
| 392 |
uint8_t *fifo; |
| 393 |
int32_t fifo_size; |
| 394 |
uint32_t data_pos; |
| 395 |
uint32_t data_len; |
| 396 |
uint8_t data_state; |
| 397 |
uint8_t data_dir; |
| 398 |
uint8_t eot; /* last wanted sector */
|
| 399 |
/* States kept only to be returned back */
|
| 400 |
/* Timers state */
|
| 401 |
uint8_t timer0; |
| 402 |
uint8_t timer1; |
| 403 |
/* precompensation */
|
| 404 |
uint8_t precomp_trk; |
| 405 |
uint8_t config; |
| 406 |
uint8_t lock; |
| 407 |
/* Power down config (also with status regB access mode */
|
| 408 |
uint8_t pwrd; |
| 409 |
/* Sun4m quirks? */
|
| 410 |
int sun4m;
|
| 411 |
/* Floppy drives */
|
| 412 |
uint8_t num_floppies; |
| 413 |
FDrive drives[MAX_FD]; |
| 414 |
int reset_sensei;
|
| 415 |
}; |
| 416 |
|
| 417 |
typedef struct FDCtrlSysBus { |
| 418 |
SysBusDevice busdev; |
| 419 |
struct FDCtrl state;
|
| 420 |
} FDCtrlSysBus; |
| 421 |
|
| 422 |
typedef struct FDCtrlISABus { |
| 423 |
ISADevice busdev; |
| 424 |
struct FDCtrl state;
|
| 425 |
int32_t bootindexA; |
| 426 |
int32_t bootindexB; |
| 427 |
} FDCtrlISABus; |
| 428 |
|
| 429 |
static uint32_t fdctrl_read (void *opaque, uint32_t reg) |
| 430 |
{
|
| 431 |
FDCtrl *fdctrl = opaque; |
| 432 |
uint32_t retval; |
| 433 |
|
| 434 |
switch (reg) {
|
| 435 |
case FD_REG_SRA:
|
| 436 |
retval = fdctrl_read_statusA(fdctrl); |
| 437 |
break;
|
| 438 |
case FD_REG_SRB:
|
| 439 |
retval = fdctrl_read_statusB(fdctrl); |
| 440 |
break;
|
| 441 |
case FD_REG_DOR:
|
| 442 |
retval = fdctrl_read_dor(fdctrl); |
| 443 |
break;
|
| 444 |
case FD_REG_TDR:
|
| 445 |
retval = fdctrl_read_tape(fdctrl); |
| 446 |
break;
|
| 447 |
case FD_REG_MSR:
|
| 448 |
retval = fdctrl_read_main_status(fdctrl); |
| 449 |
break;
|
| 450 |
case FD_REG_FIFO:
|
| 451 |
retval = fdctrl_read_data(fdctrl); |
| 452 |
break;
|
| 453 |
case FD_REG_DIR:
|
| 454 |
retval = fdctrl_read_dir(fdctrl); |
| 455 |
break;
|
| 456 |
default:
|
| 457 |
retval = (uint32_t)(-1);
|
| 458 |
break;
|
| 459 |
} |
| 460 |
FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval); |
| 461 |
|
| 462 |
return retval;
|
| 463 |
} |
| 464 |
|
| 465 |
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value) |
| 466 |
{
|
| 467 |
FDCtrl *fdctrl = opaque; |
| 468 |
|
| 469 |
FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value); |
| 470 |
|
| 471 |
switch (reg) {
|
| 472 |
case FD_REG_DOR:
|
| 473 |
fdctrl_write_dor(fdctrl, value); |
| 474 |
break;
|
| 475 |
case FD_REG_TDR:
|
| 476 |
fdctrl_write_tape(fdctrl, value); |
| 477 |
break;
|
| 478 |
case FD_REG_DSR:
|
| 479 |
fdctrl_write_rate(fdctrl, value); |
| 480 |
break;
|
| 481 |
case FD_REG_FIFO:
|
| 482 |
fdctrl_write_data(fdctrl, value); |
| 483 |
break;
|
| 484 |
default:
|
| 485 |
break;
|
| 486 |
} |
| 487 |
} |
| 488 |
|
| 489 |
static uint32_t fdctrl_read_port (void *opaque, uint32_t reg) |
| 490 |
{
|
| 491 |
return fdctrl_read(opaque, reg & 7); |
| 492 |
} |
| 493 |
|
| 494 |
static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value) |
| 495 |
{
|
| 496 |
fdctrl_write(opaque, reg & 7, value);
|
| 497 |
} |
| 498 |
|
| 499 |
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg) |
| 500 |
{
|
| 501 |
return fdctrl_read(opaque, (uint32_t)reg);
|
| 502 |
} |
| 503 |
|
| 504 |
static void fdctrl_write_mem (void *opaque, |
| 505 |
target_phys_addr_t reg, uint32_t value) |
| 506 |
{
|
| 507 |
fdctrl_write(opaque, (uint32_t)reg, value); |
| 508 |
} |
| 509 |
|
| 510 |
static CPUReadMemoryFunc * const fdctrl_mem_read[3] = { |
| 511 |
fdctrl_read_mem, |
| 512 |
fdctrl_read_mem, |
| 513 |
fdctrl_read_mem, |
| 514 |
}; |
| 515 |
|
| 516 |
static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = { |
| 517 |
fdctrl_write_mem, |
| 518 |
fdctrl_write_mem, |
| 519 |
fdctrl_write_mem, |
| 520 |
}; |
| 521 |
|
| 522 |
static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = { |
| 523 |
fdctrl_read_mem, |
| 524 |
NULL,
|
| 525 |
NULL,
|
| 526 |
}; |
| 527 |
|
| 528 |
static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = { |
| 529 |
fdctrl_write_mem, |
| 530 |
NULL,
|
| 531 |
NULL,
|
| 532 |
}; |
| 533 |
|
| 534 |
static const VMStateDescription vmstate_fdrive = { |
| 535 |
.name = "fdrive",
|
| 536 |
.version_id = 1,
|
| 537 |
.minimum_version_id = 1,
|
| 538 |
.minimum_version_id_old = 1,
|
| 539 |
.fields = (VMStateField []) {
|
| 540 |
VMSTATE_UINT8(head, FDrive), |
| 541 |
VMSTATE_UINT8(track, FDrive), |
| 542 |
VMSTATE_UINT8(sect, FDrive), |
| 543 |
VMSTATE_END_OF_LIST() |
| 544 |
} |
| 545 |
}; |
| 546 |
|
| 547 |
static void fdc_pre_save(void *opaque) |
| 548 |
{
|
| 549 |
FDCtrl *s = opaque; |
| 550 |
|
| 551 |
s->dor_vmstate = s->dor | GET_CUR_DRV(s); |
| 552 |
} |
| 553 |
|
| 554 |
static int fdc_post_load(void *opaque, int version_id) |
| 555 |
{
|
| 556 |
FDCtrl *s = opaque; |
| 557 |
|
| 558 |
SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK); |
| 559 |
s->dor = s->dor_vmstate & ~FD_DOR_SELMASK; |
| 560 |
return 0; |
| 561 |
} |
| 562 |
|
| 563 |
static const VMStateDescription vmstate_fdc = { |
| 564 |
.name = "fdc",
|
| 565 |
.version_id = 2,
|
| 566 |
.minimum_version_id = 2,
|
| 567 |
.minimum_version_id_old = 2,
|
| 568 |
.pre_save = fdc_pre_save, |
| 569 |
.post_load = fdc_post_load, |
| 570 |
.fields = (VMStateField []) {
|
| 571 |
/* Controller State */
|
| 572 |
VMSTATE_UINT8(sra, FDCtrl), |
| 573 |
VMSTATE_UINT8(srb, FDCtrl), |
| 574 |
VMSTATE_UINT8(dor_vmstate, FDCtrl), |
| 575 |
VMSTATE_UINT8(tdr, FDCtrl), |
| 576 |
VMSTATE_UINT8(dsr, FDCtrl), |
| 577 |
VMSTATE_UINT8(msr, FDCtrl), |
| 578 |
VMSTATE_UINT8(status0, FDCtrl), |
| 579 |
VMSTATE_UINT8(status1, FDCtrl), |
| 580 |
VMSTATE_UINT8(status2, FDCtrl), |
| 581 |
/* Command FIFO */
|
| 582 |
VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
|
| 583 |
uint8_t), |
| 584 |
VMSTATE_UINT32(data_pos, FDCtrl), |
| 585 |
VMSTATE_UINT32(data_len, FDCtrl), |
| 586 |
VMSTATE_UINT8(data_state, FDCtrl), |
| 587 |
VMSTATE_UINT8(data_dir, FDCtrl), |
| 588 |
VMSTATE_UINT8(eot, FDCtrl), |
| 589 |
/* States kept only to be returned back */
|
| 590 |
VMSTATE_UINT8(timer0, FDCtrl), |
| 591 |
VMSTATE_UINT8(timer1, FDCtrl), |
| 592 |
VMSTATE_UINT8(precomp_trk, FDCtrl), |
| 593 |
VMSTATE_UINT8(config, FDCtrl), |
| 594 |
VMSTATE_UINT8(lock, FDCtrl), |
| 595 |
VMSTATE_UINT8(pwrd, FDCtrl), |
| 596 |
VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl), |
| 597 |
VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
|
| 598 |
vmstate_fdrive, FDrive), |
| 599 |
VMSTATE_END_OF_LIST() |
| 600 |
} |
| 601 |
}; |
| 602 |
|
| 603 |
static void fdctrl_external_reset_sysbus(DeviceState *d) |
| 604 |
{
|
| 605 |
FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev); |
| 606 |
FDCtrl *s = &sys->state; |
| 607 |
|
| 608 |
fdctrl_reset(s, 0);
|
| 609 |
} |
| 610 |
|
| 611 |
static void fdctrl_external_reset_isa(DeviceState *d) |
| 612 |
{
|
| 613 |
FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev); |
| 614 |
FDCtrl *s = &isa->state; |
| 615 |
|
| 616 |
fdctrl_reset(s, 0);
|
| 617 |
} |
| 618 |
|
| 619 |
static void fdctrl_handle_tc(void *opaque, int irq, int level) |
| 620 |
{
|
| 621 |
//FDCtrl *s = opaque;
|
| 622 |
|
| 623 |
if (level) {
|
| 624 |
// XXX
|
| 625 |
FLOPPY_DPRINTF("TC pulsed\n");
|
| 626 |
} |
| 627 |
} |
| 628 |
|
| 629 |
/* XXX: may change if moved to bdrv */
|
| 630 |
FDriveType fdctrl_get_drive_type(FDCtrl *fdctrl, int drive_num)
|
| 631 |
{
|
| 632 |
return fdctrl->drives[drive_num].drive;
|
| 633 |
} |
| 634 |
|
| 635 |
/* Change IRQ state */
|
| 636 |
static void fdctrl_reset_irq(FDCtrl *fdctrl) |
| 637 |
{
|
| 638 |
if (!(fdctrl->sra & FD_SRA_INTPEND))
|
| 639 |
return;
|
| 640 |
FLOPPY_DPRINTF("Reset interrupt\n");
|
| 641 |
qemu_set_irq(fdctrl->irq, 0);
|
| 642 |
fdctrl->sra &= ~FD_SRA_INTPEND; |
| 643 |
} |
| 644 |
|
| 645 |
static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0) |
| 646 |
{
|
| 647 |
/* Sparc mutation */
|
| 648 |
if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
|
| 649 |
/* XXX: not sure */
|
| 650 |
fdctrl->msr &= ~FD_MSR_CMDBUSY; |
| 651 |
fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; |
| 652 |
fdctrl->status0 = status0; |
| 653 |
return;
|
| 654 |
} |
| 655 |
if (!(fdctrl->sra & FD_SRA_INTPEND)) {
|
| 656 |
qemu_set_irq(fdctrl->irq, 1);
|
| 657 |
fdctrl->sra |= FD_SRA_INTPEND; |
| 658 |
} |
| 659 |
fdctrl->reset_sensei = 0;
|
| 660 |
fdctrl->status0 = status0; |
| 661 |
FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
|
| 662 |
} |
| 663 |
|
| 664 |
/* Reset controller */
|
| 665 |
static void fdctrl_reset(FDCtrl *fdctrl, int do_irq) |
| 666 |
{
|
| 667 |
int i;
|
| 668 |
|
| 669 |
FLOPPY_DPRINTF("reset controller\n");
|
| 670 |
fdctrl_reset_irq(fdctrl); |
| 671 |
/* Initialise controller */
|
| 672 |
fdctrl->sra = 0;
|
| 673 |
fdctrl->srb = 0xc0;
|
| 674 |
if (!fdctrl->drives[1].bs) |
| 675 |
fdctrl->sra |= FD_SRA_nDRV2; |
| 676 |
fdctrl->cur_drv = 0;
|
| 677 |
fdctrl->dor = FD_DOR_nRESET; |
| 678 |
fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0; |
| 679 |
fdctrl->msr = FD_MSR_RQM; |
| 680 |
/* FIFO state */
|
| 681 |
fdctrl->data_pos = 0;
|
| 682 |
fdctrl->data_len = 0;
|
| 683 |
fdctrl->data_state = 0;
|
| 684 |
fdctrl->data_dir = FD_DIR_WRITE; |
| 685 |
for (i = 0; i < MAX_FD; i++) |
| 686 |
fd_recalibrate(&fdctrl->drives[i]); |
| 687 |
fdctrl_reset_fifo(fdctrl); |
| 688 |
if (do_irq) {
|
| 689 |
fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG); |
| 690 |
fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT; |
| 691 |
} |
| 692 |
} |
| 693 |
|
| 694 |
static inline FDrive *drv0(FDCtrl *fdctrl) |
| 695 |
{
|
| 696 |
return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2]; |
| 697 |
} |
| 698 |
|
| 699 |
static inline FDrive *drv1(FDCtrl *fdctrl) |
| 700 |
{
|
| 701 |
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2)) |
| 702 |
return &fdctrl->drives[1]; |
| 703 |
else
|
| 704 |
return &fdctrl->drives[0]; |
| 705 |
} |
| 706 |
|
| 707 |
#if MAX_FD == 4 |
| 708 |
static inline FDrive *drv2(FDCtrl *fdctrl) |
| 709 |
{
|
| 710 |
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2)) |
| 711 |
return &fdctrl->drives[2]; |
| 712 |
else
|
| 713 |
return &fdctrl->drives[1]; |
| 714 |
} |
| 715 |
|
| 716 |
static inline FDrive *drv3(FDCtrl *fdctrl) |
| 717 |
{
|
| 718 |
if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2)) |
| 719 |
return &fdctrl->drives[3]; |
| 720 |
else
|
| 721 |
return &fdctrl->drives[2]; |
| 722 |
} |
| 723 |
#endif
|
| 724 |
|
| 725 |
static FDrive *get_cur_drv(FDCtrl *fdctrl)
|
| 726 |
{
|
| 727 |
switch (fdctrl->cur_drv) {
|
| 728 |
case 0: return drv0(fdctrl); |
| 729 |
case 1: return drv1(fdctrl); |
| 730 |
#if MAX_FD == 4 |
| 731 |
case 2: return drv2(fdctrl); |
| 732 |
case 3: return drv3(fdctrl); |
| 733 |
#endif
|
| 734 |
default: return NULL; |
| 735 |
} |
| 736 |
} |
| 737 |
|
| 738 |
/* Status A register : 0x00 (read-only) */
|
| 739 |
static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
|
| 740 |
{
|
| 741 |
uint32_t retval = fdctrl->sra; |
| 742 |
|
| 743 |
FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
|
| 744 |
|
| 745 |
return retval;
|
| 746 |
} |
| 747 |
|
| 748 |
/* Status B register : 0x01 (read-only) */
|
| 749 |
static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
|
| 750 |
{
|
| 751 |
uint32_t retval = fdctrl->srb; |
| 752 |
|
| 753 |
FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
|
| 754 |
|
| 755 |
return retval;
|
| 756 |
} |
| 757 |
|
| 758 |
/* Digital output register : 0x02 */
|
| 759 |
static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
|
| 760 |
{
|
| 761 |
uint32_t retval = fdctrl->dor; |
| 762 |
|
| 763 |
/* Selected drive */
|
| 764 |
retval |= fdctrl->cur_drv; |
| 765 |
FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
|
| 766 |
|
| 767 |
return retval;
|
| 768 |
} |
| 769 |
|
| 770 |
static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value) |
| 771 |
{
|
| 772 |
FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
|
| 773 |
|
| 774 |
/* Motors */
|
| 775 |
if (value & FD_DOR_MOTEN0)
|
| 776 |
fdctrl->srb |= FD_SRB_MTR0; |
| 777 |
else
|
| 778 |
fdctrl->srb &= ~FD_SRB_MTR0; |
| 779 |
if (value & FD_DOR_MOTEN1)
|
| 780 |
fdctrl->srb |= FD_SRB_MTR1; |
| 781 |
else
|
| 782 |
fdctrl->srb &= ~FD_SRB_MTR1; |
| 783 |
|
| 784 |
/* Drive */
|
| 785 |
if (value & 1) |
| 786 |
fdctrl->srb |= FD_SRB_DR0; |
| 787 |
else
|
| 788 |
fdctrl->srb &= ~FD_SRB_DR0; |
| 789 |
|
| 790 |
/* Reset */
|
| 791 |
if (!(value & FD_DOR_nRESET)) {
|
| 792 |
if (fdctrl->dor & FD_DOR_nRESET) {
|
| 793 |
FLOPPY_DPRINTF("controller enter RESET state\n");
|
| 794 |
} |
| 795 |
} else {
|
| 796 |
if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
| 797 |
FLOPPY_DPRINTF("controller out of RESET state\n");
|
| 798 |
fdctrl_reset(fdctrl, 1);
|
| 799 |
fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
| 800 |
} |
| 801 |
} |
| 802 |
/* Selected drive */
|
| 803 |
fdctrl->cur_drv = value & FD_DOR_SELMASK; |
| 804 |
|
| 805 |
fdctrl->dor = value; |
| 806 |
} |
| 807 |
|
| 808 |
/* Tape drive register : 0x03 */
|
| 809 |
static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
|
| 810 |
{
|
| 811 |
uint32_t retval = fdctrl->tdr; |
| 812 |
|
| 813 |
FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
|
| 814 |
|
| 815 |
return retval;
|
| 816 |
} |
| 817 |
|
| 818 |
static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value) |
| 819 |
{
|
| 820 |
/* Reset mode */
|
| 821 |
if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
| 822 |
FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
|
| 823 |
return;
|
| 824 |
} |
| 825 |
FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
|
| 826 |
/* Disk boot selection indicator */
|
| 827 |
fdctrl->tdr = value & FD_TDR_BOOTSEL; |
| 828 |
/* Tape indicators: never allow */
|
| 829 |
} |
| 830 |
|
| 831 |
/* Main status register : 0x04 (read) */
|
| 832 |
static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
|
| 833 |
{
|
| 834 |
uint32_t retval = fdctrl->msr; |
| 835 |
|
| 836 |
fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
| 837 |
fdctrl->dor |= FD_DOR_nRESET; |
| 838 |
|
| 839 |
/* Sparc mutation */
|
| 840 |
if (fdctrl->sun4m) {
|
| 841 |
retval |= FD_MSR_DIO; |
| 842 |
fdctrl_reset_irq(fdctrl); |
| 843 |
}; |
| 844 |
|
| 845 |
FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
|
| 846 |
|
| 847 |
return retval;
|
| 848 |
} |
| 849 |
|
| 850 |
/* Data select rate register : 0x04 (write) */
|
| 851 |
static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value) |
| 852 |
{
|
| 853 |
/* Reset mode */
|
| 854 |
if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
| 855 |
FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
|
| 856 |
return;
|
| 857 |
} |
| 858 |
FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
|
| 859 |
/* Reset: autoclear */
|
| 860 |
if (value & FD_DSR_SWRESET) {
|
| 861 |
fdctrl->dor &= ~FD_DOR_nRESET; |
| 862 |
fdctrl_reset(fdctrl, 1);
|
| 863 |
fdctrl->dor |= FD_DOR_nRESET; |
| 864 |
} |
| 865 |
if (value & FD_DSR_PWRDOWN) {
|
| 866 |
fdctrl_reset(fdctrl, 1);
|
| 867 |
} |
| 868 |
fdctrl->dsr = value; |
| 869 |
} |
| 870 |
|
| 871 |
static int fdctrl_media_changed(FDrive *drv) |
| 872 |
{
|
| 873 |
int ret;
|
| 874 |
|
| 875 |
if (!drv->bs)
|
| 876 |
return 0; |
| 877 |
ret = bdrv_media_changed(drv->bs); |
| 878 |
if (ret) {
|
| 879 |
fd_revalidate(drv); |
| 880 |
} |
| 881 |
return ret;
|
| 882 |
} |
| 883 |
|
| 884 |
/* Digital input register : 0x07 (read-only) */
|
| 885 |
static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
|
| 886 |
{
|
| 887 |
uint32_t retval = 0;
|
| 888 |
|
| 889 |
if (fdctrl_media_changed(drv0(fdctrl))
|
| 890 |
|| fdctrl_media_changed(drv1(fdctrl)) |
| 891 |
#if MAX_FD == 4 |
| 892 |
|| fdctrl_media_changed(drv2(fdctrl)) |
| 893 |
|| fdctrl_media_changed(drv3(fdctrl)) |
| 894 |
#endif
|
| 895 |
) |
| 896 |
retval |= FD_DIR_DSKCHG; |
| 897 |
if (retval != 0) { |
| 898 |
FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
|
| 899 |
} |
| 900 |
|
| 901 |
return retval;
|
| 902 |
} |
| 903 |
|
| 904 |
/* FIFO state control */
|
| 905 |
static void fdctrl_reset_fifo(FDCtrl *fdctrl) |
| 906 |
{
|
| 907 |
fdctrl->data_dir = FD_DIR_WRITE; |
| 908 |
fdctrl->data_pos = 0;
|
| 909 |
fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO); |
| 910 |
} |
| 911 |
|
| 912 |
/* Set FIFO status for the host to read */
|
| 913 |
static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq) |
| 914 |
{
|
| 915 |
fdctrl->data_dir = FD_DIR_READ; |
| 916 |
fdctrl->data_len = fifo_len; |
| 917 |
fdctrl->data_pos = 0;
|
| 918 |
fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO; |
| 919 |
if (do_irq)
|
| 920 |
fdctrl_raise_irq(fdctrl, 0x00);
|
| 921 |
} |
| 922 |
|
| 923 |
/* Set an error: unimplemented/unknown command */
|
| 924 |
static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction) |
| 925 |
{
|
| 926 |
FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]); |
| 927 |
fdctrl->fifo[0] = FD_SR0_INVCMD;
|
| 928 |
fdctrl_set_fifo(fdctrl, 1, 0); |
| 929 |
} |
| 930 |
|
| 931 |
/* Seek to next sector */
|
| 932 |
static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv) |
| 933 |
{
|
| 934 |
FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
|
| 935 |
cur_drv->head, cur_drv->track, cur_drv->sect, |
| 936 |
fd_sector(cur_drv)); |
| 937 |
/* XXX: cur_drv->sect >= cur_drv->last_sect should be an
|
| 938 |
error in fact */
|
| 939 |
if (cur_drv->sect >= cur_drv->last_sect ||
|
| 940 |
cur_drv->sect == fdctrl->eot) {
|
| 941 |
cur_drv->sect = 1;
|
| 942 |
if (FD_MULTI_TRACK(fdctrl->data_state)) {
|
| 943 |
if (cur_drv->head == 0 && |
| 944 |
(cur_drv->flags & FDISK_DBL_SIDES) != 0) {
|
| 945 |
cur_drv->head = 1;
|
| 946 |
} else {
|
| 947 |
cur_drv->head = 0;
|
| 948 |
cur_drv->track++; |
| 949 |
if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) |
| 950 |
return 0; |
| 951 |
} |
| 952 |
} else {
|
| 953 |
cur_drv->track++; |
| 954 |
return 0; |
| 955 |
} |
| 956 |
FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
|
| 957 |
cur_drv->head, cur_drv->track, |
| 958 |
cur_drv->sect, fd_sector(cur_drv)); |
| 959 |
} else {
|
| 960 |
cur_drv->sect++; |
| 961 |
} |
| 962 |
return 1; |
| 963 |
} |
| 964 |
|
| 965 |
/* Callback for transfer end (stop or abort) */
|
| 966 |
static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0, |
| 967 |
uint8_t status1, uint8_t status2) |
| 968 |
{
|
| 969 |
FDrive *cur_drv; |
| 970 |
|
| 971 |
cur_drv = get_cur_drv(fdctrl); |
| 972 |
FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
|
| 973 |
status0, status1, status2, |
| 974 |
status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
|
| 975 |
fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl); |
| 976 |
fdctrl->fifo[1] = status1;
|
| 977 |
fdctrl->fifo[2] = status2;
|
| 978 |
fdctrl->fifo[3] = cur_drv->track;
|
| 979 |
fdctrl->fifo[4] = cur_drv->head;
|
| 980 |
fdctrl->fifo[5] = cur_drv->sect;
|
| 981 |
fdctrl->fifo[6] = FD_SECTOR_SC;
|
| 982 |
fdctrl->data_dir = FD_DIR_READ; |
| 983 |
if (!(fdctrl->msr & FD_MSR_NONDMA)) {
|
| 984 |
DMA_release_DREQ(fdctrl->dma_chann); |
| 985 |
} |
| 986 |
fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; |
| 987 |
fdctrl->msr &= ~FD_MSR_NONDMA; |
| 988 |
fdctrl_set_fifo(fdctrl, 7, 1); |
| 989 |
} |
| 990 |
|
| 991 |
/* Prepare a data transfer (either DMA or FIFO) */
|
| 992 |
static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction) |
| 993 |
{
|
| 994 |
FDrive *cur_drv; |
| 995 |
uint8_t kh, kt, ks; |
| 996 |
int did_seek = 0; |
| 997 |
|
| 998 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
| 999 |
cur_drv = get_cur_drv(fdctrl); |
| 1000 |
kt = fdctrl->fifo[2];
|
| 1001 |
kh = fdctrl->fifo[3];
|
| 1002 |
ks = fdctrl->fifo[4];
|
| 1003 |
FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
|
| 1004 |
GET_CUR_DRV(fdctrl), kh, kt, ks, |
| 1005 |
fd_sector_calc(kh, kt, ks, cur_drv->last_sect)); |
| 1006 |
switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
|
| 1007 |
case 2: |
| 1008 |
/* sect too big */
|
| 1009 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
| 1010 |
fdctrl->fifo[3] = kt;
|
| 1011 |
fdctrl->fifo[4] = kh;
|
| 1012 |
fdctrl->fifo[5] = ks;
|
| 1013 |
return;
|
| 1014 |
case 3: |
| 1015 |
/* track too big */
|
| 1016 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
|
| 1017 |
fdctrl->fifo[3] = kt;
|
| 1018 |
fdctrl->fifo[4] = kh;
|
| 1019 |
fdctrl->fifo[5] = ks;
|
| 1020 |
return;
|
| 1021 |
case 4: |
| 1022 |
/* No seek enabled */
|
| 1023 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
| 1024 |
fdctrl->fifo[3] = kt;
|
| 1025 |
fdctrl->fifo[4] = kh;
|
| 1026 |
fdctrl->fifo[5] = ks;
|
| 1027 |
return;
|
| 1028 |
case 1: |
| 1029 |
did_seek = 1;
|
| 1030 |
break;
|
| 1031 |
default:
|
| 1032 |
break;
|
| 1033 |
} |
| 1034 |
|
| 1035 |
/* Set the FIFO state */
|
| 1036 |
fdctrl->data_dir = direction; |
| 1037 |
fdctrl->data_pos = 0;
|
| 1038 |
fdctrl->msr |= FD_MSR_CMDBUSY; |
| 1039 |
if (fdctrl->fifo[0] & 0x80) |
| 1040 |
fdctrl->data_state |= FD_STATE_MULTI; |
| 1041 |
else
|
| 1042 |
fdctrl->data_state &= ~FD_STATE_MULTI; |
| 1043 |
if (did_seek)
|
| 1044 |
fdctrl->data_state |= FD_STATE_SEEK; |
| 1045 |
else
|
| 1046 |
fdctrl->data_state &= ~FD_STATE_SEEK; |
| 1047 |
if (fdctrl->fifo[5] == 00) { |
| 1048 |
fdctrl->data_len = fdctrl->fifo[8];
|
| 1049 |
} else {
|
| 1050 |
int tmp;
|
| 1051 |
fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]); |
| 1052 |
tmp = (fdctrl->fifo[6] - ks + 1); |
| 1053 |
if (fdctrl->fifo[0] & 0x80) |
| 1054 |
tmp += fdctrl->fifo[6];
|
| 1055 |
fdctrl->data_len *= tmp; |
| 1056 |
} |
| 1057 |
fdctrl->eot = fdctrl->fifo[6];
|
| 1058 |
if (fdctrl->dor & FD_DOR_DMAEN) {
|
| 1059 |
int dma_mode;
|
| 1060 |
/* DMA transfer are enabled. Check if DMA channel is well programmed */
|
| 1061 |
dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); |
| 1062 |
dma_mode = (dma_mode >> 2) & 3; |
| 1063 |
FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
|
| 1064 |
dma_mode, direction, |
| 1065 |
(128 << fdctrl->fifo[5]) * |
| 1066 |
(cur_drv->last_sect - ks + 1), fdctrl->data_len);
|
| 1067 |
if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
|
| 1068 |
direction == FD_DIR_SCANH) && dma_mode == 0) ||
|
| 1069 |
(direction == FD_DIR_WRITE && dma_mode == 2) ||
|
| 1070 |
(direction == FD_DIR_READ && dma_mode == 1)) {
|
| 1071 |
/* No access is allowed until DMA transfer has completed */
|
| 1072 |
fdctrl->msr &= ~FD_MSR_RQM; |
| 1073 |
/* Now, we just have to wait for the DMA controller to
|
| 1074 |
* recall us...
|
| 1075 |
*/
|
| 1076 |
DMA_hold_DREQ(fdctrl->dma_chann); |
| 1077 |
DMA_schedule(fdctrl->dma_chann); |
| 1078 |
return;
|
| 1079 |
} else {
|
| 1080 |
FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
|
| 1081 |
} |
| 1082 |
} |
| 1083 |
FLOPPY_DPRINTF("start non-DMA transfer\n");
|
| 1084 |
fdctrl->msr |= FD_MSR_NONDMA; |
| 1085 |
if (direction != FD_DIR_WRITE)
|
| 1086 |
fdctrl->msr |= FD_MSR_DIO; |
| 1087 |
/* IO based transfer: calculate len */
|
| 1088 |
fdctrl_raise_irq(fdctrl, 0x00);
|
| 1089 |
|
| 1090 |
return;
|
| 1091 |
} |
| 1092 |
|
| 1093 |
/* Prepare a transfer of deleted data */
|
| 1094 |
static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction) |
| 1095 |
{
|
| 1096 |
FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
|
| 1097 |
|
| 1098 |
/* We don't handle deleted data,
|
| 1099 |
* so we don't return *ANYTHING*
|
| 1100 |
*/
|
| 1101 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
| 1102 |
} |
| 1103 |
|
| 1104 |
/* handlers for DMA transfers */
|
| 1105 |
static int fdctrl_transfer_handler (void *opaque, int nchan, |
| 1106 |
int dma_pos, int dma_len) |
| 1107 |
{
|
| 1108 |
FDCtrl *fdctrl; |
| 1109 |
FDrive *cur_drv; |
| 1110 |
int len, start_pos, rel_pos;
|
| 1111 |
uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; |
| 1112 |
|
| 1113 |
fdctrl = opaque; |
| 1114 |
if (fdctrl->msr & FD_MSR_RQM) {
|
| 1115 |
FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
|
| 1116 |
return 0; |
| 1117 |
} |
| 1118 |
cur_drv = get_cur_drv(fdctrl); |
| 1119 |
if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
|
| 1120 |
fdctrl->data_dir == FD_DIR_SCANH) |
| 1121 |
status2 = FD_SR2_SNS; |
| 1122 |
if (dma_len > fdctrl->data_len)
|
| 1123 |
dma_len = fdctrl->data_len; |
| 1124 |
if (cur_drv->bs == NULL) { |
| 1125 |
if (fdctrl->data_dir == FD_DIR_WRITE)
|
| 1126 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
| 1127 |
else
|
| 1128 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
| 1129 |
len = 0;
|
| 1130 |
goto transfer_error;
|
| 1131 |
} |
| 1132 |
rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; |
| 1133 |
for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
|
| 1134 |
len = dma_len - fdctrl->data_pos; |
| 1135 |
if (len + rel_pos > FD_SECTOR_LEN)
|
| 1136 |
len = FD_SECTOR_LEN - rel_pos; |
| 1137 |
FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
|
| 1138 |
"(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
|
| 1139 |
fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head, |
| 1140 |
cur_drv->track, cur_drv->sect, fd_sector(cur_drv), |
| 1141 |
fd_sector(cur_drv) * FD_SECTOR_LEN); |
| 1142 |
if (fdctrl->data_dir != FD_DIR_WRITE ||
|
| 1143 |
len < FD_SECTOR_LEN || rel_pos != 0) {
|
| 1144 |
/* READ & SCAN commands and realign to a sector for WRITE */
|
| 1145 |
if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
|
| 1146 |
fdctrl->fifo, 1) < 0) { |
| 1147 |
FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
|
| 1148 |
fd_sector(cur_drv)); |
| 1149 |
/* Sure, image size is too small... */
|
| 1150 |
memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
|
| 1151 |
} |
| 1152 |
} |
| 1153 |
switch (fdctrl->data_dir) {
|
| 1154 |
case FD_DIR_READ:
|
| 1155 |
/* READ commands */
|
| 1156 |
DMA_write_memory (nchan, fdctrl->fifo + rel_pos, |
| 1157 |
fdctrl->data_pos, len); |
| 1158 |
break;
|
| 1159 |
case FD_DIR_WRITE:
|
| 1160 |
/* WRITE commands */
|
| 1161 |
DMA_read_memory (nchan, fdctrl->fifo + rel_pos, |
| 1162 |
fdctrl->data_pos, len); |
| 1163 |
if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
|
| 1164 |
fdctrl->fifo, 1) < 0) { |
| 1165 |
FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
|
| 1166 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
| 1167 |
goto transfer_error;
|
| 1168 |
} |
| 1169 |
break;
|
| 1170 |
default:
|
| 1171 |
/* SCAN commands */
|
| 1172 |
{
|
| 1173 |
uint8_t tmpbuf[FD_SECTOR_LEN]; |
| 1174 |
int ret;
|
| 1175 |
DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); |
| 1176 |
ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); |
| 1177 |
if (ret == 0) { |
| 1178 |
status2 = FD_SR2_SEH; |
| 1179 |
goto end_transfer;
|
| 1180 |
} |
| 1181 |
if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) || |
| 1182 |
(ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
|
| 1183 |
status2 = 0x00;
|
| 1184 |
goto end_transfer;
|
| 1185 |
} |
| 1186 |
} |
| 1187 |
break;
|
| 1188 |
} |
| 1189 |
fdctrl->data_pos += len; |
| 1190 |
rel_pos = fdctrl->data_pos % FD_SECTOR_LEN; |
| 1191 |
if (rel_pos == 0) { |
| 1192 |
/* Seek to next sector */
|
| 1193 |
if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
|
| 1194 |
break;
|
| 1195 |
} |
| 1196 |
} |
| 1197 |
end_transfer:
|
| 1198 |
len = fdctrl->data_pos - start_pos; |
| 1199 |
FLOPPY_DPRINTF("end transfer %d %d %d\n",
|
| 1200 |
fdctrl->data_pos, len, fdctrl->data_len); |
| 1201 |
if (fdctrl->data_dir == FD_DIR_SCANE ||
|
| 1202 |
fdctrl->data_dir == FD_DIR_SCANL || |
| 1203 |
fdctrl->data_dir == FD_DIR_SCANH) |
| 1204 |
status2 = FD_SR2_SEH; |
| 1205 |
if (FD_DID_SEEK(fdctrl->data_state))
|
| 1206 |
status0 |= FD_SR0_SEEK; |
| 1207 |
fdctrl->data_len -= len; |
| 1208 |
fdctrl_stop_transfer(fdctrl, status0, status1, status2); |
| 1209 |
transfer_error:
|
| 1210 |
|
| 1211 |
return len;
|
| 1212 |
} |
| 1213 |
|
| 1214 |
/* Data register : 0x05 */
|
| 1215 |
static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
|
| 1216 |
{
|
| 1217 |
FDrive *cur_drv; |
| 1218 |
uint32_t retval = 0;
|
| 1219 |
int pos;
|
| 1220 |
|
| 1221 |
cur_drv = get_cur_drv(fdctrl); |
| 1222 |
fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
| 1223 |
if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
|
| 1224 |
FLOPPY_ERROR("controller not ready for reading\n");
|
| 1225 |
return 0; |
| 1226 |
} |
| 1227 |
pos = fdctrl->data_pos; |
| 1228 |
if (fdctrl->msr & FD_MSR_NONDMA) {
|
| 1229 |
pos %= FD_SECTOR_LEN; |
| 1230 |
if (pos == 0) { |
| 1231 |
if (fdctrl->data_pos != 0) |
| 1232 |
if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
|
| 1233 |
FLOPPY_DPRINTF("error seeking to next sector %d\n",
|
| 1234 |
fd_sector(cur_drv)); |
| 1235 |
return 0; |
| 1236 |
} |
| 1237 |
if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
| 1238 |
FLOPPY_DPRINTF("error getting sector %d\n",
|
| 1239 |
fd_sector(cur_drv)); |
| 1240 |
/* Sure, image size is too small... */
|
| 1241 |
memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
|
| 1242 |
} |
| 1243 |
} |
| 1244 |
} |
| 1245 |
retval = fdctrl->fifo[pos]; |
| 1246 |
if (++fdctrl->data_pos == fdctrl->data_len) {
|
| 1247 |
fdctrl->data_pos = 0;
|
| 1248 |
/* Switch from transfer mode to status mode
|
| 1249 |
* then from status mode to command mode
|
| 1250 |
*/
|
| 1251 |
if (fdctrl->msr & FD_MSR_NONDMA) {
|
| 1252 |
fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
| 1253 |
} else {
|
| 1254 |
fdctrl_reset_fifo(fdctrl); |
| 1255 |
fdctrl_reset_irq(fdctrl); |
| 1256 |
} |
| 1257 |
} |
| 1258 |
FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
|
| 1259 |
|
| 1260 |
return retval;
|
| 1261 |
} |
| 1262 |
|
| 1263 |
static void fdctrl_format_sector(FDCtrl *fdctrl) |
| 1264 |
{
|
| 1265 |
FDrive *cur_drv; |
| 1266 |
uint8_t kh, kt, ks; |
| 1267 |
|
| 1268 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
| 1269 |
cur_drv = get_cur_drv(fdctrl); |
| 1270 |
kt = fdctrl->fifo[6];
|
| 1271 |
kh = fdctrl->fifo[7];
|
| 1272 |
ks = fdctrl->fifo[8];
|
| 1273 |
FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
|
| 1274 |
GET_CUR_DRV(fdctrl), kh, kt, ks, |
| 1275 |
fd_sector_calc(kh, kt, ks, cur_drv->last_sect)); |
| 1276 |
switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
|
| 1277 |
case 2: |
| 1278 |
/* sect too big */
|
| 1279 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
| 1280 |
fdctrl->fifo[3] = kt;
|
| 1281 |
fdctrl->fifo[4] = kh;
|
| 1282 |
fdctrl->fifo[5] = ks;
|
| 1283 |
return;
|
| 1284 |
case 3: |
| 1285 |
/* track too big */
|
| 1286 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
|
| 1287 |
fdctrl->fifo[3] = kt;
|
| 1288 |
fdctrl->fifo[4] = kh;
|
| 1289 |
fdctrl->fifo[5] = ks;
|
| 1290 |
return;
|
| 1291 |
case 4: |
| 1292 |
/* No seek enabled */
|
| 1293 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00); |
| 1294 |
fdctrl->fifo[3] = kt;
|
| 1295 |
fdctrl->fifo[4] = kh;
|
| 1296 |
fdctrl->fifo[5] = ks;
|
| 1297 |
return;
|
| 1298 |
case 1: |
| 1299 |
fdctrl->data_state |= FD_STATE_SEEK; |
| 1300 |
break;
|
| 1301 |
default:
|
| 1302 |
break;
|
| 1303 |
} |
| 1304 |
memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
|
| 1305 |
if (cur_drv->bs == NULL || |
| 1306 |
bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
| 1307 |
FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
|
| 1308 |
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00); |
| 1309 |
} else {
|
| 1310 |
if (cur_drv->sect == cur_drv->last_sect) {
|
| 1311 |
fdctrl->data_state &= ~FD_STATE_FORMAT; |
| 1312 |
/* Last sector done */
|
| 1313 |
if (FD_DID_SEEK(fdctrl->data_state))
|
| 1314 |
fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
| 1315 |
else
|
| 1316 |
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
| 1317 |
} else {
|
| 1318 |
/* More to do */
|
| 1319 |
fdctrl->data_pos = 0;
|
| 1320 |
fdctrl->data_len = 4;
|
| 1321 |
} |
| 1322 |
} |
| 1323 |
} |
| 1324 |
|
| 1325 |
static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction) |
| 1326 |
{
|
| 1327 |
fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0; |
| 1328 |
fdctrl->fifo[0] = fdctrl->lock << 4; |
| 1329 |
fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
|
| 1330 |
} |
| 1331 |
|
| 1332 |
static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction) |
| 1333 |
{
|
| 1334 |
FDrive *cur_drv = get_cur_drv(fdctrl); |
| 1335 |
|
| 1336 |
/* Drives position */
|
| 1337 |
fdctrl->fifo[0] = drv0(fdctrl)->track;
|
| 1338 |
fdctrl->fifo[1] = drv1(fdctrl)->track;
|
| 1339 |
#if MAX_FD == 4 |
| 1340 |
fdctrl->fifo[2] = drv2(fdctrl)->track;
|
| 1341 |
fdctrl->fifo[3] = drv3(fdctrl)->track;
|
| 1342 |
#else
|
| 1343 |
fdctrl->fifo[2] = 0; |
| 1344 |
fdctrl->fifo[3] = 0; |
| 1345 |
#endif
|
| 1346 |
/* timers */
|
| 1347 |
fdctrl->fifo[4] = fdctrl->timer0;
|
| 1348 |
fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0); |
| 1349 |
fdctrl->fifo[6] = cur_drv->last_sect;
|
| 1350 |
fdctrl->fifo[7] = (fdctrl->lock << 7) | |
| 1351 |
(cur_drv->perpendicular << 2);
|
| 1352 |
fdctrl->fifo[8] = fdctrl->config;
|
| 1353 |
fdctrl->fifo[9] = fdctrl->precomp_trk;
|
| 1354 |
fdctrl_set_fifo(fdctrl, 10, 0); |
| 1355 |
} |
| 1356 |
|
| 1357 |
static void fdctrl_handle_version(FDCtrl *fdctrl, int direction) |
| 1358 |
{
|
| 1359 |
/* Controller's version */
|
| 1360 |
fdctrl->fifo[0] = fdctrl->version;
|
| 1361 |
fdctrl_set_fifo(fdctrl, 1, 1); |
| 1362 |
} |
| 1363 |
|
| 1364 |
static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction) |
| 1365 |
{
|
| 1366 |
fdctrl->fifo[0] = 0x41; /* Stepping 1 */ |
| 1367 |
fdctrl_set_fifo(fdctrl, 1, 0); |
| 1368 |
} |
| 1369 |
|
| 1370 |
static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction) |
| 1371 |
{
|
| 1372 |
FDrive *cur_drv = get_cur_drv(fdctrl); |
| 1373 |
|
| 1374 |
/* Drives position */
|
| 1375 |
drv0(fdctrl)->track = fdctrl->fifo[3];
|
| 1376 |
drv1(fdctrl)->track = fdctrl->fifo[4];
|
| 1377 |
#if MAX_FD == 4 |
| 1378 |
drv2(fdctrl)->track = fdctrl->fifo[5];
|
| 1379 |
drv3(fdctrl)->track = fdctrl->fifo[6];
|
| 1380 |
#endif
|
| 1381 |
/* timers */
|
| 1382 |
fdctrl->timer0 = fdctrl->fifo[7];
|
| 1383 |
fdctrl->timer1 = fdctrl->fifo[8];
|
| 1384 |
cur_drv->last_sect = fdctrl->fifo[9];
|
| 1385 |
fdctrl->lock = fdctrl->fifo[10] >> 7; |
| 1386 |
cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF; |
| 1387 |
fdctrl->config = fdctrl->fifo[11];
|
| 1388 |
fdctrl->precomp_trk = fdctrl->fifo[12];
|
| 1389 |
fdctrl->pwrd = fdctrl->fifo[13];
|
| 1390 |
fdctrl_reset_fifo(fdctrl); |
| 1391 |
} |
| 1392 |
|
| 1393 |
static void fdctrl_handle_save(FDCtrl *fdctrl, int direction) |
| 1394 |
{
|
| 1395 |
FDrive *cur_drv = get_cur_drv(fdctrl); |
| 1396 |
|
| 1397 |
fdctrl->fifo[0] = 0; |
| 1398 |
fdctrl->fifo[1] = 0; |
| 1399 |
/* Drives position */
|
| 1400 |
fdctrl->fifo[2] = drv0(fdctrl)->track;
|
| 1401 |
fdctrl->fifo[3] = drv1(fdctrl)->track;
|
| 1402 |
#if MAX_FD == 4 |
| 1403 |
fdctrl->fifo[4] = drv2(fdctrl)->track;
|
| 1404 |
fdctrl->fifo[5] = drv3(fdctrl)->track;
|
| 1405 |
#else
|
| 1406 |
fdctrl->fifo[4] = 0; |
| 1407 |
fdctrl->fifo[5] = 0; |
| 1408 |
#endif
|
| 1409 |
/* timers */
|
| 1410 |
fdctrl->fifo[6] = fdctrl->timer0;
|
| 1411 |
fdctrl->fifo[7] = fdctrl->timer1;
|
| 1412 |
fdctrl->fifo[8] = cur_drv->last_sect;
|
| 1413 |
fdctrl->fifo[9] = (fdctrl->lock << 7) | |
| 1414 |
(cur_drv->perpendicular << 2);
|
| 1415 |
fdctrl->fifo[10] = fdctrl->config;
|
| 1416 |
fdctrl->fifo[11] = fdctrl->precomp_trk;
|
| 1417 |
fdctrl->fifo[12] = fdctrl->pwrd;
|
| 1418 |
fdctrl->fifo[13] = 0; |
| 1419 |
fdctrl->fifo[14] = 0; |
| 1420 |
fdctrl_set_fifo(fdctrl, 15, 1); |
| 1421 |
} |
| 1422 |
|
| 1423 |
static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction) |
| 1424 |
{
|
| 1425 |
FDrive *cur_drv = get_cur_drv(fdctrl); |
| 1426 |
|
| 1427 |
/* XXX: should set main status register to busy */
|
| 1428 |
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; |
| 1429 |
qemu_mod_timer(fdctrl->result_timer, |
| 1430 |
qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
|
| 1431 |
} |
| 1432 |
|
| 1433 |
static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction) |
| 1434 |
{
|
| 1435 |
FDrive *cur_drv; |
| 1436 |
|
| 1437 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
| 1438 |
cur_drv = get_cur_drv(fdctrl); |
| 1439 |
fdctrl->data_state |= FD_STATE_FORMAT; |
| 1440 |
if (fdctrl->fifo[0] & 0x80) |
| 1441 |
fdctrl->data_state |= FD_STATE_MULTI; |
| 1442 |
else
|
| 1443 |
fdctrl->data_state &= ~FD_STATE_MULTI; |
| 1444 |
fdctrl->data_state &= ~FD_STATE_SEEK; |
| 1445 |
cur_drv->bps = |
| 1446 |
fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2]; |
| 1447 |
#if 0
|
| 1448 |
cur_drv->last_sect =
|
| 1449 |
cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
|
| 1450 |
fdctrl->fifo[3] / 2;
|
| 1451 |
#else
|
| 1452 |
cur_drv->last_sect = fdctrl->fifo[3];
|
| 1453 |
#endif
|
| 1454 |
/* TODO: implement format using DMA expected by the Bochs BIOS
|
| 1455 |
* and Linux fdformat (read 3 bytes per sector via DMA and fill
|
| 1456 |
* the sector with the specified fill byte
|
| 1457 |
*/
|
| 1458 |
fdctrl->data_state &= ~FD_STATE_FORMAT; |
| 1459 |
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
| 1460 |
} |
| 1461 |
|
| 1462 |
static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction) |
| 1463 |
{
|
| 1464 |
fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF; |
| 1465 |
fdctrl->timer1 = fdctrl->fifo[2] >> 1; |
| 1466 |
if (fdctrl->fifo[2] & 1) |
| 1467 |
fdctrl->dor &= ~FD_DOR_DMAEN; |
| 1468 |
else
|
| 1469 |
fdctrl->dor |= FD_DOR_DMAEN; |
| 1470 |
/* No result back */
|
| 1471 |
fdctrl_reset_fifo(fdctrl); |
| 1472 |
} |
| 1473 |
|
| 1474 |
static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction) |
| 1475 |
{
|
| 1476 |
FDrive *cur_drv; |
| 1477 |
|
| 1478 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
| 1479 |
cur_drv = get_cur_drv(fdctrl); |
| 1480 |
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1; |
| 1481 |
/* 1 Byte status back */
|
| 1482 |
fdctrl->fifo[0] = (cur_drv->ro << 6) | |
| 1483 |
(cur_drv->track == 0 ? 0x10 : 0x00) | |
| 1484 |
(cur_drv->head << 2) |
|
| 1485 |
GET_CUR_DRV(fdctrl) | |
| 1486 |
0x28;
|
| 1487 |
fdctrl_set_fifo(fdctrl, 1, 0); |
| 1488 |
} |
| 1489 |
|
| 1490 |
static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction) |
| 1491 |
{
|
| 1492 |
FDrive *cur_drv; |
| 1493 |
|
| 1494 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
| 1495 |
cur_drv = get_cur_drv(fdctrl); |
| 1496 |
fd_recalibrate(cur_drv); |
| 1497 |
fdctrl_reset_fifo(fdctrl); |
| 1498 |
/* Raise Interrupt */
|
| 1499 |
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
| 1500 |
} |
| 1501 |
|
| 1502 |
static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction) |
| 1503 |
{
|
| 1504 |
FDrive *cur_drv = get_cur_drv(fdctrl); |
| 1505 |
|
| 1506 |
if(fdctrl->reset_sensei > 0) { |
| 1507 |
fdctrl->fifo[0] =
|
| 1508 |
FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei; |
| 1509 |
fdctrl->reset_sensei--; |
| 1510 |
} else {
|
| 1511 |
/* XXX: status0 handling is broken for read/write
|
| 1512 |
commands, so we do this hack. It should be suppressed
|
| 1513 |
ASAP */
|
| 1514 |
fdctrl->fifo[0] =
|
| 1515 |
FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
|
| 1516 |
} |
| 1517 |
|
| 1518 |
fdctrl->fifo[1] = cur_drv->track;
|
| 1519 |
fdctrl_set_fifo(fdctrl, 2, 0); |
| 1520 |
fdctrl_reset_irq(fdctrl); |
| 1521 |
fdctrl->status0 = FD_SR0_RDYCHG; |
| 1522 |
} |
| 1523 |
|
| 1524 |
static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction) |
| 1525 |
{
|
| 1526 |
FDrive *cur_drv; |
| 1527 |
|
| 1528 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
| 1529 |
cur_drv = get_cur_drv(fdctrl); |
| 1530 |
fdctrl_reset_fifo(fdctrl); |
| 1531 |
if (fdctrl->fifo[2] > cur_drv->max_track) { |
| 1532 |
fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK); |
| 1533 |
} else {
|
| 1534 |
cur_drv->track = fdctrl->fifo[2];
|
| 1535 |
/* Raise Interrupt */
|
| 1536 |
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
| 1537 |
} |
| 1538 |
} |
| 1539 |
|
| 1540 |
static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction) |
| 1541 |
{
|
| 1542 |
FDrive *cur_drv = get_cur_drv(fdctrl); |
| 1543 |
|
| 1544 |
if (fdctrl->fifo[1] & 0x80) |
| 1545 |
cur_drv->perpendicular = fdctrl->fifo[1] & 0x7; |
| 1546 |
/* No result back */
|
| 1547 |
fdctrl_reset_fifo(fdctrl); |
| 1548 |
} |
| 1549 |
|
| 1550 |
static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction) |
| 1551 |
{
|
| 1552 |
fdctrl->config = fdctrl->fifo[2];
|
| 1553 |
fdctrl->precomp_trk = fdctrl->fifo[3];
|
| 1554 |
/* No result back */
|
| 1555 |
fdctrl_reset_fifo(fdctrl); |
| 1556 |
} |
| 1557 |
|
| 1558 |
static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction) |
| 1559 |
{
|
| 1560 |
fdctrl->pwrd = fdctrl->fifo[1];
|
| 1561 |
fdctrl->fifo[0] = fdctrl->fifo[1]; |
| 1562 |
fdctrl_set_fifo(fdctrl, 1, 1); |
| 1563 |
} |
| 1564 |
|
| 1565 |
static void fdctrl_handle_option(FDCtrl *fdctrl, int direction) |
| 1566 |
{
|
| 1567 |
/* No result back */
|
| 1568 |
fdctrl_reset_fifo(fdctrl); |
| 1569 |
} |
| 1570 |
|
| 1571 |
static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction) |
| 1572 |
{
|
| 1573 |
FDrive *cur_drv = get_cur_drv(fdctrl); |
| 1574 |
|
| 1575 |
if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) { |
| 1576 |
/* Command parameters done */
|
| 1577 |
if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) { |
| 1578 |
fdctrl->fifo[0] = fdctrl->fifo[1]; |
| 1579 |
fdctrl->fifo[2] = 0; |
| 1580 |
fdctrl->fifo[3] = 0; |
| 1581 |
fdctrl_set_fifo(fdctrl, 4, 1); |
| 1582 |
} else {
|
| 1583 |
fdctrl_reset_fifo(fdctrl); |
| 1584 |
} |
| 1585 |
} else if (fdctrl->data_len > 7) { |
| 1586 |
/* ERROR */
|
| 1587 |
fdctrl->fifo[0] = 0x80 | |
| 1588 |
(cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
|
| 1589 |
fdctrl_set_fifo(fdctrl, 1, 1); |
| 1590 |
} |
| 1591 |
} |
| 1592 |
|
| 1593 |
static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction) |
| 1594 |
{
|
| 1595 |
FDrive *cur_drv; |
| 1596 |
|
| 1597 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
| 1598 |
cur_drv = get_cur_drv(fdctrl); |
| 1599 |
if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) { |
| 1600 |
cur_drv->track = cur_drv->max_track - 1;
|
| 1601 |
} else {
|
| 1602 |
cur_drv->track += fdctrl->fifo[2];
|
| 1603 |
} |
| 1604 |
fdctrl_reset_fifo(fdctrl); |
| 1605 |
/* Raise Interrupt */
|
| 1606 |
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
| 1607 |
} |
| 1608 |
|
| 1609 |
static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction) |
| 1610 |
{
|
| 1611 |
FDrive *cur_drv; |
| 1612 |
|
| 1613 |
SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
|
| 1614 |
cur_drv = get_cur_drv(fdctrl); |
| 1615 |
if (fdctrl->fifo[2] > cur_drv->track) { |
| 1616 |
cur_drv->track = 0;
|
| 1617 |
} else {
|
| 1618 |
cur_drv->track -= fdctrl->fifo[2];
|
| 1619 |
} |
| 1620 |
fdctrl_reset_fifo(fdctrl); |
| 1621 |
/* Raise Interrupt */
|
| 1622 |
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK); |
| 1623 |
} |
| 1624 |
|
| 1625 |
static const struct { |
| 1626 |
uint8_t value; |
| 1627 |
uint8_t mask; |
| 1628 |
const char* name; |
| 1629 |
int parameters;
|
| 1630 |
void (*handler)(FDCtrl *fdctrl, int direction); |
| 1631 |
int direction;
|
| 1632 |
} handlers[] = {
|
| 1633 |
{ FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
|
| 1634 |
{ FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
|
| 1635 |
{ FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
|
| 1636 |
{ FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
|
| 1637 |
{ FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
|
| 1638 |
{ FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
|
| 1639 |
{ FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
|
| 1640 |
{ FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
|
| 1641 |
{ FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
|
| 1642 |
{ FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
|
| 1643 |
{ FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
|
| 1644 |
{ FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
|
| 1645 |
{ FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
|
| 1646 |
{ FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
|
| 1647 |
{ FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
|
| 1648 |
{ FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
|
| 1649 |
{ FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
|
| 1650 |
{ FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
|
| 1651 |
{ FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
|
| 1652 |
{ FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
|
| 1653 |
{ FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
|
| 1654 |
{ FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
|
| 1655 |
{ FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
|
| 1656 |
{ FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
|
| 1657 |
{ FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
|
| 1658 |
{ FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
|
| 1659 |
{ FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
|
| 1660 |
{ FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
|
| 1661 |
{ FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
|
| 1662 |
{ FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
|
| 1663 |
{ FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
|
| 1664 |
{ 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
|
| 1665 |
}; |
| 1666 |
/* Associate command to an index in the 'handlers' array */
|
| 1667 |
static uint8_t command_to_handler[256]; |
| 1668 |
|
| 1669 |
static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value) |
| 1670 |
{
|
| 1671 |
FDrive *cur_drv; |
| 1672 |
int pos;
|
| 1673 |
|
| 1674 |
/* Reset mode */
|
| 1675 |
if (!(fdctrl->dor & FD_DOR_nRESET)) {
|
| 1676 |
FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
|
| 1677 |
return;
|
| 1678 |
} |
| 1679 |
if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
|
| 1680 |
FLOPPY_ERROR("controller not ready for writing\n");
|
| 1681 |
return;
|
| 1682 |
} |
| 1683 |
fdctrl->dsr &= ~FD_DSR_PWRDOWN; |
| 1684 |
/* Is it write command time ? */
|
| 1685 |
if (fdctrl->msr & FD_MSR_NONDMA) {
|
| 1686 |
/* FIFO data write */
|
| 1687 |
pos = fdctrl->data_pos++; |
| 1688 |
pos %= FD_SECTOR_LEN; |
| 1689 |
fdctrl->fifo[pos] = value; |
| 1690 |
if (pos == FD_SECTOR_LEN - 1 || |
| 1691 |
fdctrl->data_pos == fdctrl->data_len) {
|
| 1692 |
cur_drv = get_cur_drv(fdctrl); |
| 1693 |
if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { |
| 1694 |
FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
|
| 1695 |
return;
|
| 1696 |
} |
| 1697 |
if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
|
| 1698 |
FLOPPY_DPRINTF("error seeking to next sector %d\n",
|
| 1699 |
fd_sector(cur_drv)); |
| 1700 |
return;
|
| 1701 |
} |
| 1702 |
} |
| 1703 |
/* Switch from transfer mode to status mode
|
| 1704 |
* then from status mode to command mode
|
| 1705 |
*/
|
| 1706 |
if (fdctrl->data_pos == fdctrl->data_len)
|
| 1707 |
fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00); |
| 1708 |
return;
|
| 1709 |
} |
| 1710 |
if (fdctrl->data_pos == 0) { |
| 1711 |
/* Command */
|
| 1712 |
pos = command_to_handler[value & 0xff];
|
| 1713 |
FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
|
| 1714 |
fdctrl->data_len = handlers[pos].parameters + 1;
|
| 1715 |
} |
| 1716 |
|
| 1717 |
FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
|
| 1718 |
fdctrl->fifo[fdctrl->data_pos++] = value; |
| 1719 |
if (fdctrl->data_pos == fdctrl->data_len) {
|
| 1720 |
/* We now have all parameters
|
| 1721 |
* and will be able to treat the command
|
| 1722 |
*/
|
| 1723 |
if (fdctrl->data_state & FD_STATE_FORMAT) {
|
| 1724 |
fdctrl_format_sector(fdctrl); |
| 1725 |
return;
|
| 1726 |
} |
| 1727 |
|
| 1728 |
pos = command_to_handler[fdctrl->fifo[0] & 0xff]; |
| 1729 |
FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
|
| 1730 |
(*handlers[pos].handler)(fdctrl, handlers[pos].direction); |
| 1731 |
} |
| 1732 |
} |
| 1733 |
|
| 1734 |
static void fdctrl_result_timer(void *opaque) |
| 1735 |
{
|
| 1736 |
FDCtrl *fdctrl = opaque; |
| 1737 |
FDrive *cur_drv = get_cur_drv(fdctrl); |
| 1738 |
|
| 1739 |
/* Pretend we are spinning.
|
| 1740 |
* This is needed for Coherent, which uses READ ID to check for
|
| 1741 |
* sector interleaving.
|
| 1742 |
*/
|
| 1743 |
if (cur_drv->last_sect != 0) { |
| 1744 |
cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
|
| 1745 |
} |
| 1746 |
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00); |
| 1747 |
} |
| 1748 |
|
| 1749 |
/* Init functions */
|
| 1750 |
static int fdctrl_connect_drives(FDCtrl *fdctrl) |
| 1751 |
{
|
| 1752 |
unsigned int i; |
| 1753 |
FDrive *drive; |
| 1754 |
|
| 1755 |
for (i = 0; i < MAX_FD; i++) { |
| 1756 |
drive = &fdctrl->drives[i]; |
| 1757 |
|
| 1758 |
if (drive->bs) {
|
| 1759 |
if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) { |
| 1760 |
error_report("fdc doesn't support drive option werror");
|
| 1761 |
return -1; |
| 1762 |
} |
| 1763 |
if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) { |
| 1764 |
error_report("fdc doesn't support drive option rerror");
|
| 1765 |
return -1; |
| 1766 |
} |
| 1767 |
} |
| 1768 |
|
| 1769 |
fd_init(drive); |
| 1770 |
fd_revalidate(drive); |
| 1771 |
if (drive->bs) {
|
| 1772 |
bdrv_set_removable(drive->bs, 1);
|
| 1773 |
} |
| 1774 |
} |
| 1775 |
return 0; |
| 1776 |
} |
| 1777 |
|
| 1778 |
FDCtrl *fdctrl_init_isa(DriveInfo **fds) |
| 1779 |
{
|
| 1780 |
ISADevice *dev; |
| 1781 |
|
| 1782 |
dev = isa_create("isa-fdc");
|
| 1783 |
if (fds[0]) { |
| 1784 |
qdev_prop_set_drive_nofail(&dev->qdev, "driveA", fds[0]->bdrv); |
| 1785 |
} |
| 1786 |
if (fds[1]) { |
| 1787 |
qdev_prop_set_drive_nofail(&dev->qdev, "driveB", fds[1]->bdrv); |
| 1788 |
} |
| 1789 |
qdev_init_nofail(&dev->qdev); |
| 1790 |
return &(DO_UPCAST(FDCtrlISABus, busdev, dev)->state);
|
| 1791 |
} |
| 1792 |
|
| 1793 |
FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
|
| 1794 |
target_phys_addr_t mmio_base, DriveInfo **fds) |
| 1795 |
{
|
| 1796 |
FDCtrl *fdctrl; |
| 1797 |
DeviceState *dev; |
| 1798 |
FDCtrlSysBus *sys; |
| 1799 |
|
| 1800 |
dev = qdev_create(NULL, "sysbus-fdc"); |
| 1801 |
sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev); |
| 1802 |
fdctrl = &sys->state; |
| 1803 |
fdctrl->dma_chann = dma_chann; /* FIXME */
|
| 1804 |
if (fds[0]) { |
| 1805 |
qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv); |
| 1806 |
} |
| 1807 |
if (fds[1]) { |
| 1808 |
qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv); |
| 1809 |
} |
| 1810 |
qdev_init_nofail(dev); |
| 1811 |
sysbus_connect_irq(&sys->busdev, 0, irq);
|
| 1812 |
sysbus_mmio_map(&sys->busdev, 0, mmio_base);
|
| 1813 |
|
| 1814 |
return fdctrl;
|
| 1815 |
} |
| 1816 |
|
| 1817 |
FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base, |
| 1818 |
DriveInfo **fds, qemu_irq *fdc_tc) |
| 1819 |
{
|
| 1820 |
DeviceState *dev; |
| 1821 |
FDCtrlSysBus *sys; |
| 1822 |
FDCtrl *fdctrl; |
| 1823 |
|
| 1824 |
dev = qdev_create(NULL, "SUNW,fdtwo"); |
| 1825 |
if (fds[0]) { |
| 1826 |
qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv); |
| 1827 |
} |
| 1828 |
qdev_init_nofail(dev); |
| 1829 |
sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev); |
| 1830 |
fdctrl = &sys->state; |
| 1831 |
sysbus_connect_irq(&sys->busdev, 0, irq);
|
| 1832 |
sysbus_mmio_map(&sys->busdev, 0, io_base);
|
| 1833 |
*fdc_tc = qdev_get_gpio_in(dev, 0);
|
| 1834 |
|
| 1835 |
return fdctrl;
|
| 1836 |
} |
| 1837 |
|
| 1838 |
static int fdctrl_init_common(FDCtrl *fdctrl) |
| 1839 |
{
|
| 1840 |
int i, j;
|
| 1841 |
static int command_tables_inited = 0; |
| 1842 |
|
| 1843 |
/* Fill 'command_to_handler' lookup table */
|
| 1844 |
if (!command_tables_inited) {
|
| 1845 |
command_tables_inited = 1;
|
| 1846 |
for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) { |
| 1847 |
for (j = 0; j < sizeof(command_to_handler); j++) { |
| 1848 |
if ((j & handlers[i].mask) == handlers[i].value) {
|
| 1849 |
command_to_handler[j] = i; |
| 1850 |
} |
| 1851 |
} |
| 1852 |
} |
| 1853 |
} |
| 1854 |
|
| 1855 |
FLOPPY_DPRINTF("init controller\n");
|
| 1856 |
fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
|
| 1857 |
fdctrl->fifo_size = 512;
|
| 1858 |
fdctrl->result_timer = qemu_new_timer(vm_clock, |
| 1859 |
fdctrl_result_timer, fdctrl); |
| 1860 |
|
| 1861 |
fdctrl->version = 0x90; /* Intel 82078 controller */ |
| 1862 |
fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
|
| 1863 |
fdctrl->num_floppies = MAX_FD; |
| 1864 |
|
| 1865 |
if (fdctrl->dma_chann != -1) |
| 1866 |
DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl); |
| 1867 |
return fdctrl_connect_drives(fdctrl);
|
| 1868 |
} |
| 1869 |
|
| 1870 |
static int isabus_fdc_init1(ISADevice *dev) |
| 1871 |
{
|
| 1872 |
FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev); |
| 1873 |
FDCtrl *fdctrl = &isa->state; |
| 1874 |
int iobase = 0x3f0; |
| 1875 |
int isairq = 6; |
| 1876 |
int dma_chann = 2; |
| 1877 |
int ret;
|
| 1878 |
|
| 1879 |
register_ioport_read(iobase + 0x01, 5, 1, |
| 1880 |
&fdctrl_read_port, fdctrl); |
| 1881 |
register_ioport_read(iobase + 0x07, 1, 1, |
| 1882 |
&fdctrl_read_port, fdctrl); |
| 1883 |
register_ioport_write(iobase + 0x01, 5, 1, |
| 1884 |
&fdctrl_write_port, fdctrl); |
| 1885 |
register_ioport_write(iobase + 0x07, 1, 1, |
| 1886 |
&fdctrl_write_port, fdctrl); |
| 1887 |
isa_init_ioport_range(dev, iobase, 6);
|
| 1888 |
isa_init_ioport(dev, iobase + 7);
|
| 1889 |
|
| 1890 |
isa_init_irq(&isa->busdev, &fdctrl->irq, isairq); |
| 1891 |
fdctrl->dma_chann = dma_chann; |
| 1892 |
|
| 1893 |
qdev_set_legacy_instance_id(&dev->qdev, iobase, 2);
|
| 1894 |
ret = fdctrl_init_common(fdctrl); |
| 1895 |
|
| 1896 |
add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
|
| 1897 |
add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
|
| 1898 |
|
| 1899 |
return ret;
|
| 1900 |
} |
| 1901 |
|
| 1902 |
static int sysbus_fdc_init1(SysBusDevice *dev) |
| 1903 |
{
|
| 1904 |
FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev); |
| 1905 |
FDCtrl *fdctrl = &sys->state; |
| 1906 |
int io;
|
| 1907 |
int ret;
|
| 1908 |
|
| 1909 |
io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl, |
| 1910 |
DEVICE_NATIVE_ENDIAN); |
| 1911 |
sysbus_init_mmio(dev, 0x08, io);
|
| 1912 |
sysbus_init_irq(dev, &fdctrl->irq); |
| 1913 |
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
|
| 1914 |
fdctrl->dma_chann = -1;
|
| 1915 |
|
| 1916 |
qdev_set_legacy_instance_id(&dev->qdev, io, 2);
|
| 1917 |
ret = fdctrl_init_common(fdctrl); |
| 1918 |
|
| 1919 |
return ret;
|
| 1920 |
} |
| 1921 |
|
| 1922 |
static int sun4m_fdc_init1(SysBusDevice *dev) |
| 1923 |
{
|
| 1924 |
FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state); |
| 1925 |
int io;
|
| 1926 |
|
| 1927 |
io = cpu_register_io_memory(fdctrl_mem_read_strict, |
| 1928 |
fdctrl_mem_write_strict, fdctrl, |
| 1929 |
DEVICE_NATIVE_ENDIAN); |
| 1930 |
sysbus_init_mmio(dev, 0x08, io);
|
| 1931 |
sysbus_init_irq(dev, &fdctrl->irq); |
| 1932 |
qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
|
| 1933 |
|
| 1934 |
fdctrl->sun4m = 1;
|
| 1935 |
qdev_set_legacy_instance_id(&dev->qdev, io, 2);
|
| 1936 |
return fdctrl_init_common(fdctrl);
|
| 1937 |
} |
| 1938 |
|
| 1939 |
static const VMStateDescription vmstate_isa_fdc ={ |
| 1940 |
.name = "fdc",
|
| 1941 |
.version_id = 2,
|
| 1942 |
.minimum_version_id = 2,
|
| 1943 |
.fields = (VMStateField []) {
|
| 1944 |
VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
|
| 1945 |
VMSTATE_END_OF_LIST() |
| 1946 |
} |
| 1947 |
}; |
| 1948 |
|
| 1949 |
static ISADeviceInfo isa_fdc_info = {
|
| 1950 |
.init = isabus_fdc_init1, |
| 1951 |
.qdev.name = "isa-fdc",
|
| 1952 |
.qdev.fw_name = "fdc",
|
| 1953 |
.qdev.size = sizeof(FDCtrlISABus),
|
| 1954 |
.qdev.no_user = 1,
|
| 1955 |
.qdev.vmsd = &vmstate_isa_fdc, |
| 1956 |
.qdev.reset = fdctrl_external_reset_isa, |
| 1957 |
.qdev.props = (Property[]) {
|
| 1958 |
DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs), |
| 1959 |
DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs), |
| 1960 |
DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1), |
| 1961 |
DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1), |
| 1962 |
DEFINE_PROP_END_OF_LIST(), |
| 1963 |
}, |
| 1964 |
}; |
| 1965 |
|
| 1966 |
static const VMStateDescription vmstate_sysbus_fdc ={ |
| 1967 |
.name = "fdc",
|
| 1968 |
.version_id = 2,
|
| 1969 |
.minimum_version_id = 2,
|
| 1970 |
.fields = (VMStateField []) {
|
| 1971 |
VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
|
| 1972 |
VMSTATE_END_OF_LIST() |
| 1973 |
} |
| 1974 |
}; |
| 1975 |
|
| 1976 |
static SysBusDeviceInfo sysbus_fdc_info = {
|
| 1977 |
.init = sysbus_fdc_init1, |
| 1978 |
.qdev.name = "sysbus-fdc",
|
| 1979 |
.qdev.size = sizeof(FDCtrlSysBus),
|
| 1980 |
.qdev.vmsd = &vmstate_sysbus_fdc, |
| 1981 |
.qdev.reset = fdctrl_external_reset_sysbus, |
| 1982 |
.qdev.props = (Property[]) {
|
| 1983 |
DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs), |
| 1984 |
DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs), |
| 1985 |
DEFINE_PROP_END_OF_LIST(), |
| 1986 |
}, |
| 1987 |
}; |
| 1988 |
|
| 1989 |
static SysBusDeviceInfo sun4m_fdc_info = {
|
| 1990 |
.init = sun4m_fdc_init1, |
| 1991 |
.qdev.name = "SUNW,fdtwo",
|
| 1992 |
.qdev.size = sizeof(FDCtrlSysBus),
|
| 1993 |
.qdev.vmsd = &vmstate_sysbus_fdc, |
| 1994 |
.qdev.reset = fdctrl_external_reset_sysbus, |
| 1995 |
.qdev.props = (Property[]) {
|
| 1996 |
DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs), |
| 1997 |
DEFINE_PROP_END_OF_LIST(), |
| 1998 |
}, |
| 1999 |
}; |
| 2000 |
|
| 2001 |
static void fdc_register_devices(void) |
| 2002 |
{
|
| 2003 |
isa_qdev_register(&isa_fdc_info); |
| 2004 |
sysbus_register_withprop(&sysbus_fdc_info); |
| 2005 |
sysbus_register_withprop(&sun4m_fdc_info); |
| 2006 |
} |
| 2007 |
|
| 2008 |
device_init(fdc_register_devices) |