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/*
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* QEMU PC System Emulator
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "apic.h" |
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#include "fdc.h" |
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#include "ide.h" |
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#include "pci.h" |
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#include "vmware_vga.h" |
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#include "monitor.h" |
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#include "fw_cfg.h" |
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#include "hpet_emul.h" |
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#include "smbios.h" |
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#include "loader.h" |
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#include "elf.h" |
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#include "multiboot.h" |
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#include "mc146818rtc.h" |
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#include "msix.h" |
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#include "sysbus.h" |
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#include "sysemu.h" |
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#include "blockdev.h" |
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#include "ui/qemu-spice.h" |
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/* output Bochs bios info messages */
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//#define DEBUG_BIOS
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/* debug PC/ISA interrupts */
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//#define DEBUG_IRQ
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#ifdef DEBUG_IRQ
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#define DPRINTF(fmt, ...) \
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do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define BIOS_FILENAME "bios.bin" |
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#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024) |
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/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
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#define ACPI_DATA_SIZE 0x10000 |
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#define BIOS_CFG_IOPORT 0x510 |
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#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) |
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#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1) |
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#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2) |
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#define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) |
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#define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) |
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#define MSI_ADDR_BASE 0xfee00000 |
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#define E820_NR_ENTRIES 16 |
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struct e820_entry {
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uint64_t address; |
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uint64_t length; |
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uint32_t type; |
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} __attribute((__packed__, __aligned__(4)));
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struct e820_table {
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uint32_t count; |
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struct e820_entry entry[E820_NR_ENTRIES];
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} __attribute((__packed__, __aligned__(4)));
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static struct e820_table e820_table; |
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struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
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void isa_irq_handler(void *opaque, int n, int level) |
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{ |
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IsaIrqState *isa = (IsaIrqState *)opaque; |
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DPRINTF("isa_irqs: %s irq %d\n", level? "raise" : "lower", n); |
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if (n < 16) { |
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qemu_set_irq(isa->i8259[n], level); |
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} |
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if (isa->ioapic)
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qemu_set_irq(isa->ioapic[n], level); |
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}; |
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static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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} |
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/* MSDOS compatibility mode FPU exception support */
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static qemu_irq ferr_irq;
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void pc_register_ferr_irq(qemu_irq irq)
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{ |
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ferr_irq = irq; |
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} |
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/* XXX: add IGNNE support */
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void cpu_set_ferr(CPUX86State *s)
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{ |
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qemu_irq_raise(ferr_irq); |
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} |
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static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) |
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{ |
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qemu_irq_lower(ferr_irq); |
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} |
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/* TSC handling */
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uint64_t cpu_get_tsc(CPUX86State *env) |
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{ |
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return cpu_get_ticks();
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} |
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/* SMM support */
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static cpu_set_smm_t smm_set;
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static void *smm_arg; |
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void cpu_smm_register(cpu_set_smm_t callback, void *arg) |
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{ |
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assert(smm_set == NULL);
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assert(smm_arg == NULL);
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smm_set = callback; |
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smm_arg = arg; |
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} |
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void cpu_smm_update(CPUState *env)
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{ |
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if (smm_set && smm_arg && env == first_cpu)
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smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg); |
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} |
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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{ |
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int intno;
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intno = apic_get_interrupt(env->apic_state); |
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if (intno >= 0) { |
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/* set irq request if a PIC irq is still pending */
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/* XXX: improve that */
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pic_update_irq(isa_pic); |
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return intno;
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} |
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/* read the irq from the PIC */
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if (!apic_accept_pic_intr(env->apic_state)) {
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return -1; |
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} |
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intno = pic_read_irq(isa_pic); |
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return intno;
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} |
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static void pic_irq_request(void *opaque, int irq, int level) |
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{ |
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CPUState *env = first_cpu; |
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DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq); |
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if (env->apic_state) {
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while (env) {
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if (apic_accept_pic_intr(env->apic_state)) {
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apic_deliver_pic_intr(env->apic_state, level); |
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} |
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env = env->next_cpu; |
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} |
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} else {
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if (level)
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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else
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} |
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE 0x14 |
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static int cmos_get_fd_drive_type(FDriveType fd0) |
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{ |
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int val;
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switch (fd0) {
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case FDRIVE_DRV_144:
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/* 1.44 Mb 3"5 drive */
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val = 4;
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break;
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case FDRIVE_DRV_288:
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/* 2.88 Mb 3"5 drive */
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val = 5;
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break;
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case FDRIVE_DRV_120:
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/* 1.2 Mb 5"5 drive */
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val = 2;
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break;
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case FDRIVE_DRV_NONE:
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default:
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val = 0;
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break;
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} |
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return val;
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} |
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static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd, |
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ISADevice *s) |
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{ |
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int cylinders, heads, sectors;
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bdrv_get_geometry_hint(hd, &cylinders, &heads, §ors); |
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rtc_set_memory(s, type_ofs, 47);
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rtc_set_memory(s, info_ofs, cylinders); |
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rtc_set_memory(s, info_ofs + 1, cylinders >> 8); |
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rtc_set_memory(s, info_ofs + 2, heads);
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rtc_set_memory(s, info_ofs + 3, 0xff); |
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rtc_set_memory(s, info_ofs + 4, 0xff); |
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rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3)); |
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rtc_set_memory(s, info_ofs + 6, cylinders);
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rtc_set_memory(s, info_ofs + 7, cylinders >> 8); |
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rtc_set_memory(s, info_ofs + 8, sectors);
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} |
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/* convert boot_device letter to something recognizable by the bios */
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static int boot_device2nibble(char boot_device) |
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{ |
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switch(boot_device) {
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case 'a': |
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case 'b': |
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return 0x01; /* floppy boot */ |
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case 'c': |
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return 0x02; /* hard drive boot */ |
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case 'd': |
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return 0x03; /* CD-ROM boot */ |
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case 'n': |
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return 0x04; /* Network boot */ |
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} |
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return 0; |
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} |
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static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk) |
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{ |
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#define PC_MAX_BOOT_DEVICES 3 |
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int nbds, bds[3] = { 0, }; |
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int i;
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nbds = strlen(boot_device); |
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if (nbds > PC_MAX_BOOT_DEVICES) {
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error_report("Too many boot devices for PC");
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return(1); |
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} |
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for (i = 0; i < nbds; i++) { |
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bds[i] = boot_device2nibble(boot_device[i]); |
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if (bds[i] == 0) { |
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error_report("Invalid boot device for PC: '%c'",
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boot_device[i]); |
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return(1); |
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} |
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} |
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rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]); |
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rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1)); |
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return(0); |
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} |
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static int pc_boot_set(void *opaque, const char *boot_device) |
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{ |
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return set_boot_dev(opaque, boot_device, 0); |
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} |
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typedef struct pc_cmos_init_late_arg { |
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ISADevice *rtc_state; |
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BusState *idebus0, *idebus1; |
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} pc_cmos_init_late_arg; |
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static void pc_cmos_init_late(void *opaque) |
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{ |
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pc_cmos_init_late_arg *arg = opaque; |
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ISADevice *s = arg->rtc_state; |
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int val;
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BlockDriverState *hd_table[4];
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int i;
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ide_get_bs(hd_table, arg->idebus0); |
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ide_get_bs(hd_table + 2, arg->idebus1);
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rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0)); |
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if (hd_table[0]) |
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cmos_init_hd(0x19, 0x1b, hd_table[0], s); |
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if (hd_table[1]) |
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cmos_init_hd(0x1a, 0x24, hd_table[1], s); |
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val = 0;
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for (i = 0; i < 4; i++) { |
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if (hd_table[i]) {
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int cylinders, heads, sectors, translation;
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/* NOTE: bdrv_get_geometry_hint() returns the physical
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geometry. It is always such that: 1 <= sects <= 63, 1
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<= heads <= 16, 1 <= cylinders <= 16383. The BIOS
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geometry can be different if a translation is done. */
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translation = bdrv_get_translation_hint(hd_table[i]); |
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if (translation == BIOS_ATA_TRANSLATION_AUTO) {
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bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, §ors); |
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if (cylinders <= 1024 && heads <= 16 && sectors <= 63) { |
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/* No translation. */
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translation = 0;
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} else {
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/* LBA translation. */
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translation = 1;
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} |
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} else {
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translation--; |
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} |
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val |= translation << (i * 2);
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} |
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} |
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rtc_set_memory(s, 0x39, val);
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qemu_unregister_reset(pc_cmos_init_late, opaque); |
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} |
333 |
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void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
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const char *boot_device, |
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BusState *idebus0, BusState *idebus1, |
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FDCtrl *floppy_controller, ISADevice *s) |
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{ |
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int val, nb;
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FDriveType fd0, fd1; |
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static pc_cmos_init_late_arg arg;
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/* various important CMOS locations needed by PC/Bochs bios */
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/* memory size */
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val = 640; /* base memory in K */ |
347 |
rtc_set_memory(s, 0x15, val);
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rtc_set_memory(s, 0x16, val >> 8); |
349 |
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val = (ram_size / 1024) - 1024; |
351 |
if (val > 65535) |
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val = 65535;
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rtc_set_memory(s, 0x17, val);
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rtc_set_memory(s, 0x18, val >> 8); |
355 |
rtc_set_memory(s, 0x30, val);
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rtc_set_memory(s, 0x31, val >> 8); |
357 |
|
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if (above_4g_mem_size) {
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rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16); |
360 |
rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24); |
361 |
rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32); |
362 |
} |
363 |
|
364 |
if (ram_size > (16 * 1024 * 1024)) |
365 |
val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536); |
366 |
else
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val = 0;
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if (val > 65535) |
369 |
val = 65535;
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rtc_set_memory(s, 0x34, val);
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rtc_set_memory(s, 0x35, val >> 8); |
372 |
|
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/* set the number of CPU */
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rtc_set_memory(s, 0x5f, smp_cpus - 1); |
375 |
|
376 |
/* set boot devices, and disable floppy signature check if requested */
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if (set_boot_dev(s, boot_device, fd_bootchk)) {
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exit(1);
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379 |
} |
380 |
|
381 |
/* floppy type */
|
382 |
|
383 |
fd0 = fdctrl_get_drive_type(floppy_controller, 0);
|
384 |
fd1 = fdctrl_get_drive_type(floppy_controller, 1);
|
385 |
|
386 |
val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
|
387 |
rtc_set_memory(s, 0x10, val);
|
388 |
|
389 |
val = 0;
|
390 |
nb = 0;
|
391 |
if (fd0 < FDRIVE_DRV_NONE) {
|
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nb++; |
393 |
} |
394 |
if (fd1 < FDRIVE_DRV_NONE) {
|
395 |
nb++; |
396 |
} |
397 |
switch (nb) {
|
398 |
case 0: |
399 |
break;
|
400 |
case 1: |
401 |
val |= 0x01; /* 1 drive, ready for boot */ |
402 |
break;
|
403 |
case 2: |
404 |
val |= 0x41; /* 2 drives, ready for boot */ |
405 |
break;
|
406 |
} |
407 |
val |= 0x02; /* FPU is there */ |
408 |
val |= 0x04; /* PS/2 mouse installed */ |
409 |
rtc_set_memory(s, REG_EQUIPMENT_BYTE, val); |
410 |
|
411 |
/* hard drives */
|
412 |
arg.rtc_state = s; |
413 |
arg.idebus0 = idebus0; |
414 |
arg.idebus1 = idebus1; |
415 |
qemu_register_reset(pc_cmos_init_late, &arg); |
416 |
} |
417 |
|
418 |
/* port 92 stuff: could be split off */
|
419 |
typedef struct Port92State { |
420 |
ISADevice dev; |
421 |
uint8_t outport; |
422 |
qemu_irq *a20_out; |
423 |
} Port92State; |
424 |
|
425 |
static void port92_write(void *opaque, uint32_t addr, uint32_t val) |
426 |
{ |
427 |
Port92State *s = opaque; |
428 |
|
429 |
DPRINTF("port92: write 0x%02x\n", val);
|
430 |
s->outport = val; |
431 |
qemu_set_irq(*s->a20_out, (val >> 1) & 1); |
432 |
if (val & 1) { |
433 |
qemu_system_reset_request(); |
434 |
} |
435 |
} |
436 |
|
437 |
static uint32_t port92_read(void *opaque, uint32_t addr) |
438 |
{ |
439 |
Port92State *s = opaque; |
440 |
uint32_t ret; |
441 |
|
442 |
ret = s->outport; |
443 |
DPRINTF("port92: read 0x%02x\n", ret);
|
444 |
return ret;
|
445 |
} |
446 |
|
447 |
static void port92_init(ISADevice *dev, qemu_irq *a20_out) |
448 |
{ |
449 |
Port92State *s = DO_UPCAST(Port92State, dev, dev); |
450 |
|
451 |
s->a20_out = a20_out; |
452 |
} |
453 |
|
454 |
static const VMStateDescription vmstate_port92_isa = { |
455 |
.name = "port92",
|
456 |
.version_id = 1,
|
457 |
.minimum_version_id = 1,
|
458 |
.minimum_version_id_old = 1,
|
459 |
.fields = (VMStateField []) { |
460 |
VMSTATE_UINT8(outport, Port92State), |
461 |
VMSTATE_END_OF_LIST() |
462 |
} |
463 |
}; |
464 |
|
465 |
static void port92_reset(DeviceState *d) |
466 |
{ |
467 |
Port92State *s = container_of(d, Port92State, dev.qdev); |
468 |
|
469 |
s->outport &= ~1;
|
470 |
} |
471 |
|
472 |
static int port92_initfn(ISADevice *dev) |
473 |
{ |
474 |
Port92State *s = DO_UPCAST(Port92State, dev, dev); |
475 |
|
476 |
register_ioport_read(0x92, 1, 1, port92_read, s); |
477 |
register_ioport_write(0x92, 1, 1, port92_write, s); |
478 |
isa_init_ioport(dev, 0x92);
|
479 |
s->outport = 0;
|
480 |
return 0; |
481 |
} |
482 |
|
483 |
static ISADeviceInfo port92_info = {
|
484 |
.qdev.name = "port92",
|
485 |
.qdev.size = sizeof(Port92State),
|
486 |
.qdev.vmsd = &vmstate_port92_isa, |
487 |
.qdev.no_user = 1,
|
488 |
.qdev.reset = port92_reset, |
489 |
.init = port92_initfn, |
490 |
}; |
491 |
|
492 |
static void port92_register(void) |
493 |
{ |
494 |
isa_qdev_register(&port92_info); |
495 |
} |
496 |
device_init(port92_register) |
497 |
|
498 |
static void handle_a20_line_change(void *opaque, int irq, int level) |
499 |
{ |
500 |
CPUState *cpu = opaque; |
501 |
|
502 |
/* XXX: send to all CPUs ? */
|
503 |
/* XXX: add logic to handle multiple A20 line sources */
|
504 |
cpu_x86_set_a20(cpu, level); |
505 |
} |
506 |
|
507 |
/***********************************************************/
|
508 |
/* Bochs BIOS debug ports */
|
509 |
|
510 |
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) |
511 |
{ |
512 |
static const char shutdown_str[8] = "Shutdown"; |
513 |
static int shutdown_index = 0; |
514 |
|
515 |
switch(addr) {
|
516 |
/* Bochs BIOS messages */
|
517 |
case 0x400: |
518 |
case 0x401: |
519 |
/* used to be panic, now unused */
|
520 |
break;
|
521 |
case 0x402: |
522 |
case 0x403: |
523 |
#ifdef DEBUG_BIOS
|
524 |
fprintf(stderr, "%c", val);
|
525 |
#endif
|
526 |
break;
|
527 |
case 0x8900: |
528 |
/* same as Bochs power off */
|
529 |
if (val == shutdown_str[shutdown_index]) {
|
530 |
shutdown_index++; |
531 |
if (shutdown_index == 8) { |
532 |
shutdown_index = 0;
|
533 |
qemu_system_shutdown_request(); |
534 |
} |
535 |
} else {
|
536 |
shutdown_index = 0;
|
537 |
} |
538 |
break;
|
539 |
|
540 |
/* LGPL'ed VGA BIOS messages */
|
541 |
case 0x501: |
542 |
case 0x502: |
543 |
fprintf(stderr, "VGA BIOS panic, line %d\n", val);
|
544 |
exit(1);
|
545 |
case 0x500: |
546 |
case 0x503: |
547 |
#ifdef DEBUG_BIOS
|
548 |
fprintf(stderr, "%c", val);
|
549 |
#endif
|
550 |
break;
|
551 |
} |
552 |
} |
553 |
|
554 |
int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
|
555 |
{ |
556 |
int index = le32_to_cpu(e820_table.count);
|
557 |
struct e820_entry *entry;
|
558 |
|
559 |
if (index >= E820_NR_ENTRIES)
|
560 |
return -EBUSY;
|
561 |
entry = &e820_table.entry[index++]; |
562 |
|
563 |
entry->address = cpu_to_le64(address); |
564 |
entry->length = cpu_to_le64(length); |
565 |
entry->type = cpu_to_le32(type); |
566 |
|
567 |
e820_table.count = cpu_to_le32(index); |
568 |
return index;
|
569 |
} |
570 |
|
571 |
static void *bochs_bios_init(void) |
572 |
{ |
573 |
void *fw_cfg;
|
574 |
uint8_t *smbios_table; |
575 |
size_t smbios_len; |
576 |
uint64_t *numa_fw_cfg; |
577 |
int i, j;
|
578 |
|
579 |
register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL); |
580 |
register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL); |
581 |
register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL); |
582 |
register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL); |
583 |
register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); |
584 |
|
585 |
register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); |
586 |
register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); |
587 |
register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL); |
588 |
register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL); |
589 |
|
590 |
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
591 |
|
592 |
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
593 |
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
594 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables, |
595 |
acpi_tables_len); |
596 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
|
597 |
|
598 |
smbios_table = smbios_get_table(&smbios_len); |
599 |
if (smbios_table)
|
600 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, |
601 |
smbios_table, smbios_len); |
602 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table, |
603 |
sizeof(struct e820_table)); |
604 |
|
605 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg, |
606 |
sizeof(struct hpet_fw_config)); |
607 |
/* allocate memory for the NUMA channel: one (64bit) word for the number
|
608 |
* of nodes, one word for each VCPU->node and one word for each node to
|
609 |
* hold the amount of memory.
|
610 |
*/
|
611 |
numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8); |
612 |
numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
|
613 |
for (i = 0; i < smp_cpus; i++) { |
614 |
for (j = 0; j < nb_numa_nodes; j++) { |
615 |
if (node_cpumask[j] & (1 << i)) { |
616 |
numa_fw_cfg[i + 1] = cpu_to_le64(j);
|
617 |
break;
|
618 |
} |
619 |
} |
620 |
} |
621 |
for (i = 0; i < nb_numa_nodes; i++) { |
622 |
numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
|
623 |
} |
624 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg, |
625 |
(1 + smp_cpus + nb_numa_nodes) * 8); |
626 |
|
627 |
return fw_cfg;
|
628 |
} |
629 |
|
630 |
static long get_file_size(FILE *f) |
631 |
{ |
632 |
long where, size;
|
633 |
|
634 |
/* XXX: on Unix systems, using fstat() probably makes more sense */
|
635 |
|
636 |
where = ftell(f); |
637 |
fseek(f, 0, SEEK_END);
|
638 |
size = ftell(f); |
639 |
fseek(f, where, SEEK_SET); |
640 |
|
641 |
return size;
|
642 |
} |
643 |
|
644 |
static void load_linux(void *fw_cfg, |
645 |
const char *kernel_filename, |
646 |
const char *initrd_filename, |
647 |
const char *kernel_cmdline, |
648 |
target_phys_addr_t max_ram_size) |
649 |
{ |
650 |
uint16_t protocol; |
651 |
int setup_size, kernel_size, initrd_size = 0, cmdline_size; |
652 |
uint32_t initrd_max; |
653 |
uint8_t header[8192], *setup, *kernel, *initrd_data;
|
654 |
target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
|
655 |
FILE *f; |
656 |
char *vmode;
|
657 |
|
658 |
/* Align to 16 bytes as a paranoia measure */
|
659 |
cmdline_size = (strlen(kernel_cmdline)+16) & ~15; |
660 |
|
661 |
/* load the kernel header */
|
662 |
f = fopen(kernel_filename, "rb");
|
663 |
if (!f || !(kernel_size = get_file_size(f)) ||
|
664 |
fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
|
665 |
MIN(ARRAY_SIZE(header), kernel_size)) { |
666 |
fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
|
667 |
kernel_filename, strerror(errno)); |
668 |
exit(1);
|
669 |
} |
670 |
|
671 |
/* kernel protocol version */
|
672 |
#if 0
|
673 |
fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
|
674 |
#endif
|
675 |
if (ldl_p(header+0x202) == 0x53726448) |
676 |
protocol = lduw_p(header+0x206);
|
677 |
else {
|
678 |
/* This looks like a multiboot kernel. If it is, let's stop
|
679 |
treating it like a Linux kernel. */
|
680 |
if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
|
681 |
kernel_cmdline, kernel_size, header)) |
682 |
return;
|
683 |
protocol = 0;
|
684 |
} |
685 |
|
686 |
if (protocol < 0x200 || !(header[0x211] & 0x01)) { |
687 |
/* Low kernel */
|
688 |
real_addr = 0x90000;
|
689 |
cmdline_addr = 0x9a000 - cmdline_size;
|
690 |
prot_addr = 0x10000;
|
691 |
} else if (protocol < 0x202) { |
692 |
/* High but ancient kernel */
|
693 |
real_addr = 0x90000;
|
694 |
cmdline_addr = 0x9a000 - cmdline_size;
|
695 |
prot_addr = 0x100000;
|
696 |
} else {
|
697 |
/* High and recent kernel */
|
698 |
real_addr = 0x10000;
|
699 |
cmdline_addr = 0x20000;
|
700 |
prot_addr = 0x100000;
|
701 |
} |
702 |
|
703 |
#if 0
|
704 |
fprintf(stderr,
|
705 |
"qemu: real_addr = 0x" TARGET_FMT_plx "\n"
|
706 |
"qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
|
707 |
"qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
|
708 |
real_addr,
|
709 |
cmdline_addr,
|
710 |
prot_addr);
|
711 |
#endif
|
712 |
|
713 |
/* highest address for loading the initrd */
|
714 |
if (protocol >= 0x203) |
715 |
initrd_max = ldl_p(header+0x22c);
|
716 |
else
|
717 |
initrd_max = 0x37ffffff;
|
718 |
|
719 |
if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
|
720 |
initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
|
721 |
|
722 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr); |
723 |
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
|
724 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
725 |
(uint8_t*)strdup(kernel_cmdline), |
726 |
strlen(kernel_cmdline)+1);
|
727 |
|
728 |
if (protocol >= 0x202) { |
729 |
stl_p(header+0x228, cmdline_addr);
|
730 |
} else {
|
731 |
stw_p(header+0x20, 0xA33F); |
732 |
stw_p(header+0x22, cmdline_addr-real_addr);
|
733 |
} |
734 |
|
735 |
/* handle vga= parameter */
|
736 |
vmode = strstr(kernel_cmdline, "vga=");
|
737 |
if (vmode) {
|
738 |
unsigned int video_mode; |
739 |
/* skip "vga=" */
|
740 |
vmode += 4;
|
741 |
if (!strncmp(vmode, "normal", 6)) { |
742 |
video_mode = 0xffff;
|
743 |
} else if (!strncmp(vmode, "ext", 3)) { |
744 |
video_mode = 0xfffe;
|
745 |
} else if (!strncmp(vmode, "ask", 3)) { |
746 |
video_mode = 0xfffd;
|
747 |
} else {
|
748 |
video_mode = strtol(vmode, NULL, 0); |
749 |
} |
750 |
stw_p(header+0x1fa, video_mode);
|
751 |
} |
752 |
|
753 |
/* loader type */
|
754 |
/* High nybble = B reserved for Qemu; low nybble is revision number.
|
755 |
If this code is substantially changed, you may want to consider
|
756 |
incrementing the revision. */
|
757 |
if (protocol >= 0x200) |
758 |
header[0x210] = 0xB0; |
759 |
|
760 |
/* heap */
|
761 |
if (protocol >= 0x201) { |
762 |
header[0x211] |= 0x80; /* CAN_USE_HEAP */ |
763 |
stw_p(header+0x224, cmdline_addr-real_addr-0x200); |
764 |
} |
765 |
|
766 |
/* load initrd */
|
767 |
if (initrd_filename) {
|
768 |
if (protocol < 0x200) { |
769 |
fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
|
770 |
exit(1);
|
771 |
} |
772 |
|
773 |
initrd_size = get_image_size(initrd_filename); |
774 |
if (initrd_size < 0) { |
775 |
fprintf(stderr, "qemu: error reading initrd %s\n",
|
776 |
initrd_filename); |
777 |
exit(1);
|
778 |
} |
779 |
|
780 |
initrd_addr = (initrd_max-initrd_size) & ~4095;
|
781 |
|
782 |
initrd_data = qemu_malloc(initrd_size); |
783 |
load_image(initrd_filename, initrd_data); |
784 |
|
785 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
786 |
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
787 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size); |
788 |
|
789 |
stl_p(header+0x218, initrd_addr);
|
790 |
stl_p(header+0x21c, initrd_size);
|
791 |
} |
792 |
|
793 |
/* load kernel and setup */
|
794 |
setup_size = header[0x1f1];
|
795 |
if (setup_size == 0) |
796 |
setup_size = 4;
|
797 |
setup_size = (setup_size+1)*512; |
798 |
kernel_size -= setup_size; |
799 |
|
800 |
setup = qemu_malloc(setup_size); |
801 |
kernel = qemu_malloc(kernel_size); |
802 |
fseek(f, 0, SEEK_SET);
|
803 |
if (fread(setup, 1, setup_size, f) != setup_size) { |
804 |
fprintf(stderr, "fread() failed\n");
|
805 |
exit(1);
|
806 |
} |
807 |
if (fread(kernel, 1, kernel_size, f) != kernel_size) { |
808 |
fprintf(stderr, "fread() failed\n");
|
809 |
exit(1);
|
810 |
} |
811 |
fclose(f); |
812 |
memcpy(setup, header, MIN(sizeof(header), setup_size));
|
813 |
|
814 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr); |
815 |
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
816 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size); |
817 |
|
818 |
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr); |
819 |
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size); |
820 |
fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size); |
821 |
|
822 |
option_rom[nb_option_roms].name = "linuxboot.bin";
|
823 |
option_rom[nb_option_roms].bootindex = 0;
|
824 |
nb_option_roms++; |
825 |
} |
826 |
|
827 |
#define NE2000_NB_MAX 6 |
828 |
|
829 |
static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, |
830 |
0x280, 0x380 }; |
831 |
static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
832 |
|
833 |
static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
834 |
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
835 |
|
836 |
void pc_init_ne2k_isa(NICInfo *nd)
|
837 |
{ |
838 |
static int nb_ne2k = 0; |
839 |
|
840 |
if (nb_ne2k == NE2000_NB_MAX)
|
841 |
return;
|
842 |
isa_ne2000_init(ne2000_io[nb_ne2k], |
843 |
ne2000_irq[nb_ne2k], nd); |
844 |
nb_ne2k++; |
845 |
} |
846 |
|
847 |
int cpu_is_bsp(CPUState *env)
|
848 |
{ |
849 |
/* We hard-wire the BSP to the first CPU. */
|
850 |
return env->cpu_index == 0; |
851 |
} |
852 |
|
853 |
DeviceState *cpu_get_current_apic(void)
|
854 |
{ |
855 |
if (cpu_single_env) {
|
856 |
return cpu_single_env->apic_state;
|
857 |
} else {
|
858 |
return NULL; |
859 |
} |
860 |
} |
861 |
|
862 |
static DeviceState *apic_init(void *env, uint8_t apic_id) |
863 |
{ |
864 |
DeviceState *dev; |
865 |
SysBusDevice *d; |
866 |
static int apic_mapped; |
867 |
|
868 |
dev = qdev_create(NULL, "apic"); |
869 |
qdev_prop_set_uint8(dev, "id", apic_id);
|
870 |
qdev_prop_set_ptr(dev, "cpu_env", env);
|
871 |
qdev_init_nofail(dev); |
872 |
d = sysbus_from_qdev(dev); |
873 |
|
874 |
/* XXX: mapping more APICs at the same memory location */
|
875 |
if (apic_mapped == 0) { |
876 |
/* NOTE: the APIC is directly connected to the CPU - it is not
|
877 |
on the global memory bus. */
|
878 |
/* XXX: what if the base changes? */
|
879 |
sysbus_mmio_map(d, 0, MSI_ADDR_BASE);
|
880 |
apic_mapped = 1;
|
881 |
} |
882 |
|
883 |
msix_supported = 1;
|
884 |
|
885 |
return dev;
|
886 |
} |
887 |
|
888 |
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
889 |
BIOS will read it and start S3 resume at POST Entry */
|
890 |
void pc_cmos_set_s3_resume(void *opaque, int irq, int level) |
891 |
{ |
892 |
ISADevice *s = opaque; |
893 |
|
894 |
if (level) {
|
895 |
rtc_set_memory(s, 0xF, 0xFE); |
896 |
} |
897 |
} |
898 |
|
899 |
void pc_acpi_smi_interrupt(void *opaque, int irq, int level) |
900 |
{ |
901 |
CPUState *s = opaque; |
902 |
|
903 |
if (level) {
|
904 |
cpu_interrupt(s, CPU_INTERRUPT_SMI); |
905 |
} |
906 |
} |
907 |
|
908 |
static void pc_cpu_reset(void *opaque) |
909 |
{ |
910 |
CPUState *env = opaque; |
911 |
|
912 |
cpu_reset(env); |
913 |
env->halted = !cpu_is_bsp(env); |
914 |
} |
915 |
|
916 |
static CPUState *pc_new_cpu(const char *cpu_model) |
917 |
{ |
918 |
CPUState *env; |
919 |
|
920 |
env = cpu_init(cpu_model); |
921 |
if (!env) {
|
922 |
fprintf(stderr, "Unable to find x86 CPU definition\n");
|
923 |
exit(1);
|
924 |
} |
925 |
if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { |
926 |
env->cpuid_apic_id = env->cpu_index; |
927 |
env->apic_state = apic_init(env, env->cpuid_apic_id); |
928 |
} |
929 |
qemu_register_reset(pc_cpu_reset, env); |
930 |
pc_cpu_reset(env); |
931 |
return env;
|
932 |
} |
933 |
|
934 |
void pc_cpus_init(const char *cpu_model) |
935 |
{ |
936 |
int i;
|
937 |
|
938 |
/* init CPUs */
|
939 |
if (cpu_model == NULL) { |
940 |
#ifdef TARGET_X86_64
|
941 |
cpu_model = "qemu64";
|
942 |
#else
|
943 |
cpu_model = "qemu32";
|
944 |
#endif
|
945 |
} |
946 |
|
947 |
for(i = 0; i < smp_cpus; i++) { |
948 |
pc_new_cpu(cpu_model); |
949 |
} |
950 |
} |
951 |
|
952 |
void pc_memory_init(ram_addr_t ram_size,
|
953 |
const char *kernel_filename, |
954 |
const char *kernel_cmdline, |
955 |
const char *initrd_filename, |
956 |
ram_addr_t *below_4g_mem_size_p, |
957 |
ram_addr_t *above_4g_mem_size_p) |
958 |
{ |
959 |
char *filename;
|
960 |
int ret, linux_boot, i;
|
961 |
ram_addr_t ram_addr, bios_offset, option_rom_offset; |
962 |
ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
|
963 |
int bios_size, isa_bios_size;
|
964 |
void *fw_cfg;
|
965 |
|
966 |
if (ram_size >= 0xe0000000 ) { |
967 |
above_4g_mem_size = ram_size - 0xe0000000;
|
968 |
below_4g_mem_size = 0xe0000000;
|
969 |
} else {
|
970 |
below_4g_mem_size = ram_size; |
971 |
} |
972 |
*above_4g_mem_size_p = above_4g_mem_size; |
973 |
*below_4g_mem_size_p = below_4g_mem_size; |
974 |
|
975 |
#if TARGET_PHYS_ADDR_BITS == 32 |
976 |
if (above_4g_mem_size > 0) { |
977 |
hw_error("To much RAM for 32-bit physical address");
|
978 |
} |
979 |
#endif
|
980 |
linux_boot = (kernel_filename != NULL);
|
981 |
|
982 |
/* allocate RAM */
|
983 |
ram_addr = qemu_ram_alloc(NULL, "pc.ram", |
984 |
below_4g_mem_size + above_4g_mem_size); |
985 |
cpu_register_physical_memory(0, 0xa0000, ram_addr); |
986 |
cpu_register_physical_memory(0x100000,
|
987 |
below_4g_mem_size - 0x100000,
|
988 |
ram_addr + 0x100000);
|
989 |
#if TARGET_PHYS_ADDR_BITS > 32 |
990 |
if (above_4g_mem_size > 0) { |
991 |
cpu_register_physical_memory(0x100000000ULL, above_4g_mem_size,
|
992 |
ram_addr + below_4g_mem_size); |
993 |
} |
994 |
#endif
|
995 |
|
996 |
/* BIOS load */
|
997 |
if (bios_name == NULL) |
998 |
bios_name = BIOS_FILENAME; |
999 |
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
1000 |
if (filename) {
|
1001 |
bios_size = get_image_size(filename); |
1002 |
} else {
|
1003 |
bios_size = -1;
|
1004 |
} |
1005 |
if (bios_size <= 0 || |
1006 |
(bios_size % 65536) != 0) { |
1007 |
goto bios_error;
|
1008 |
} |
1009 |
bios_offset = qemu_ram_alloc(NULL, "pc.bios", bios_size); |
1010 |
ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
|
1011 |
if (ret != 0) { |
1012 |
bios_error:
|
1013 |
fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
|
1014 |
exit(1);
|
1015 |
} |
1016 |
if (filename) {
|
1017 |
qemu_free(filename); |
1018 |
} |
1019 |
/* map the last 128KB of the BIOS in ISA space */
|
1020 |
isa_bios_size = bios_size; |
1021 |
if (isa_bios_size > (128 * 1024)) |
1022 |
isa_bios_size = 128 * 1024; |
1023 |
cpu_register_physical_memory(0x100000 - isa_bios_size,
|
1024 |
isa_bios_size, |
1025 |
(bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM); |
1026 |
|
1027 |
option_rom_offset = qemu_ram_alloc(NULL, "pc.rom", PC_ROM_SIZE); |
1028 |
cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset); |
1029 |
|
1030 |
/* map all the bios at the top of memory */
|
1031 |
cpu_register_physical_memory((uint32_t)(-bios_size), |
1032 |
bios_size, bios_offset | IO_MEM_ROM); |
1033 |
|
1034 |
fw_cfg = bochs_bios_init(); |
1035 |
rom_set_fw(fw_cfg); |
1036 |
|
1037 |
if (linux_boot) {
|
1038 |
load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size); |
1039 |
} |
1040 |
|
1041 |
for (i = 0; i < nb_option_roms; i++) { |
1042 |
rom_add_option(option_rom[i].name, option_rom[i].bootindex); |
1043 |
} |
1044 |
} |
1045 |
|
1046 |
qemu_irq *pc_allocate_cpu_irq(void)
|
1047 |
{ |
1048 |
return qemu_allocate_irqs(pic_irq_request, NULL, 1); |
1049 |
} |
1050 |
|
1051 |
void pc_vga_init(PCIBus *pci_bus)
|
1052 |
{ |
1053 |
if (cirrus_vga_enabled) {
|
1054 |
if (pci_bus) {
|
1055 |
pci_cirrus_vga_init(pci_bus); |
1056 |
} else {
|
1057 |
isa_cirrus_vga_init(); |
1058 |
} |
1059 |
} else if (vmsvga_enabled) { |
1060 |
if (pci_bus) {
|
1061 |
if (!pci_vmsvga_init(pci_bus)) {
|
1062 |
fprintf(stderr, "Warning: vmware_vga not available,"
|
1063 |
" using standard VGA instead\n");
|
1064 |
pci_vga_init(pci_bus); |
1065 |
} |
1066 |
} else {
|
1067 |
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
|
1068 |
} |
1069 |
#ifdef CONFIG_SPICE
|
1070 |
} else if (qxl_enabled) { |
1071 |
if (pci_bus)
|
1072 |
pci_create_simple(pci_bus, -1, "qxl-vga"); |
1073 |
else
|
1074 |
fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
|
1075 |
#endif
|
1076 |
} else if (std_vga_enabled) { |
1077 |
if (pci_bus) {
|
1078 |
pci_vga_init(pci_bus); |
1079 |
} else {
|
1080 |
isa_vga_init(); |
1081 |
} |
1082 |
} |
1083 |
} |
1084 |
|
1085 |
static void cpu_request_exit(void *opaque, int irq, int level) |
1086 |
{ |
1087 |
CPUState *env = cpu_single_env; |
1088 |
|
1089 |
if (env && level) {
|
1090 |
cpu_exit(env); |
1091 |
} |
1092 |
} |
1093 |
|
1094 |
void pc_basic_device_init(qemu_irq *isa_irq,
|
1095 |
FDCtrl **floppy_controller, |
1096 |
ISADevice **rtc_state) |
1097 |
{ |
1098 |
int i;
|
1099 |
DriveInfo *fd[MAX_FD]; |
1100 |
PITState *pit; |
1101 |
qemu_irq rtc_irq = NULL;
|
1102 |
qemu_irq *a20_line; |
1103 |
ISADevice *i8042, *port92, *vmmouse; |
1104 |
qemu_irq *cpu_exit_irq; |
1105 |
|
1106 |
register_ioport_write(0x80, 1, 1, ioport80_write, NULL); |
1107 |
|
1108 |
register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); |
1109 |
|
1110 |
if (!no_hpet) {
|
1111 |
DeviceState *hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); |
1112 |
|
1113 |
if (hpet) {
|
1114 |
for (i = 0; i < 24; i++) { |
1115 |
sysbus_connect_irq(sysbus_from_qdev(hpet), i, isa_irq[i]); |
1116 |
} |
1117 |
rtc_irq = qdev_get_gpio_in(hpet, 0);
|
1118 |
} |
1119 |
} |
1120 |
*rtc_state = rtc_init(2000, rtc_irq);
|
1121 |
|
1122 |
qemu_register_boot_set(pc_boot_set, *rtc_state); |
1123 |
|
1124 |
pit = pit_init(0x40, isa_reserve_irq(0)); |
1125 |
pcspk_init(pit); |
1126 |
|
1127 |
for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
1128 |
if (serial_hds[i]) {
|
1129 |
serial_isa_init(i, serial_hds[i]); |
1130 |
} |
1131 |
} |
1132 |
|
1133 |
for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
1134 |
if (parallel_hds[i]) {
|
1135 |
parallel_init(i, parallel_hds[i]); |
1136 |
} |
1137 |
} |
1138 |
|
1139 |
a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
|
1140 |
i8042 = isa_create_simple("i8042");
|
1141 |
i8042_setup_a20_line(i8042, &a20_line[0]);
|
1142 |
vmport_init(); |
1143 |
vmmouse = isa_try_create("vmmouse");
|
1144 |
if (vmmouse) {
|
1145 |
qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
|
1146 |
} |
1147 |
port92 = isa_create_simple("port92");
|
1148 |
port92_init(port92, &a20_line[1]);
|
1149 |
|
1150 |
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1); |
1151 |
DMA_init(0, cpu_exit_irq);
|
1152 |
|
1153 |
for(i = 0; i < MAX_FD; i++) { |
1154 |
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
1155 |
} |
1156 |
*floppy_controller = fdctrl_init_isa(fd); |
1157 |
} |
1158 |
|
1159 |
void pc_pci_device_init(PCIBus *pci_bus)
|
1160 |
{ |
1161 |
int max_bus;
|
1162 |
int bus;
|
1163 |
|
1164 |
max_bus = drive_get_max_bus(IF_SCSI); |
1165 |
for (bus = 0; bus <= max_bus; bus++) { |
1166 |
pci_create_simple(pci_bus, -1, "lsi53c895a"); |
1167 |
} |
1168 |
} |