Revision d353eb43 hw/pxa2xx_timer.c
b/hw/pxa2xx_timer.c | ||
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89 | 89 |
uint32_t irq_enabled; |
90 | 90 |
uint32_t reset3; |
91 | 91 |
uint32_t snapshot; |
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} pxa2xx_timer_info;
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} PXA2xxTimerInfo;
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static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu) |
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{ |
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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97 | 97 |
int i; |
98 | 98 |
uint32_t now_vm; |
99 | 99 |
uint64_t new_qemu; |
... | ... | |
110 | 110 |
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111 | 111 |
static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) |
112 | 112 |
{ |
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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uint32_t now_vm; |
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uint64_t new_qemu; |
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static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 }; |
... | ... | |
137 | 137 |
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static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset) |
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{ |
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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int tm = 0; |
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switch (offset) { |
... | ... | |
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uint32_t value) |
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{ |
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int i, tm = 0; |
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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220 | 220 |
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switch (offset) { |
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case OSMR3: tm ++; |
... | ... | |
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static void pxa2xx_timer_tick(void *opaque) |
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{ |
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PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque; |
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pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;
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PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->info;
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338 | 338 |
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if (i->irq_enabled & (1 << t->num)) { |
340 | 340 |
t->level = 1; |
... | ... | |
352 | 352 |
static void pxa2xx_timer_tick4(void *opaque) |
353 | 353 |
{ |
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PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque; |
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pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->tm.info;
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PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;
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356 | 356 |
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pxa2xx_timer_tick(&t->tm); |
358 | 358 |
if (t->control & (1 << 3)) |
... | ... | |
363 | 363 |
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364 | 364 |
static void pxa2xx_timer_save(QEMUFile *f, void *opaque) |
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{ |
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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367 | 367 |
int i; |
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qemu_put_be32s(f, (uint32_t *) &s->clock); |
... | ... | |
393 | 393 |
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static int pxa2xx_timer_load(QEMUFile *f, void *opaque, int version_id) |
395 | 395 |
{ |
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
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397 | 397 |
int64_t now; |
398 | 398 |
int i; |
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... | ... | |
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return 0; |
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} |
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static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
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static PXA2xxTimerInfo *pxa2xx_timer_init(target_phys_addr_t base,
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DeviceState *pic) |
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{ |
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int i; |
435 | 435 |
int iomemtype; |
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pxa2xx_timer_info *s;
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PXA2xxTimerInfo *s;
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s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
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s = (PXA2xxTimerInfo *) qemu_mallocz(sizeof(PXA2xxTimerInfo));
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s->irq_enabled = 0; |
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s->oldclock = 0; |
441 | 441 |
s->clock = 0; |
... | ... | |
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void pxa25x_timer_init(target_phys_addr_t base, DeviceState *pic) |
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{ |
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pxa2xx_timer_info *s = pxa2xx_timer_init(base, pic);
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PXA2xxTimerInfo *s = pxa2xx_timer_init(base, pic);
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468 | 468 |
s->freq = PXA25X_FREQ; |
469 | 469 |
s->tm4 = NULL; |
470 | 470 |
} |
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void pxa27x_timer_init(target_phys_addr_t base, DeviceState *pic) |
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{ |
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pxa2xx_timer_info *s = pxa2xx_timer_init(base, pic);
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PXA2xxTimerInfo *s = pxa2xx_timer_init(base, pic);
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475 | 475 |
int i; |
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s->freq = PXA27X_FREQ; |
477 | 477 |
s->tm4 = (PXA2xxTimer4 *) qemu_mallocz(8 * |
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