root / target-sparc / op_helper.c @ d35527d9
History | View | Annotate | Download (59.8 kB)
1 |
#include "exec.h" |
---|---|
2 |
#include "host-utils.h" |
3 |
#include "helper.h" |
4 |
|
5 |
//#define DEBUG_PCALL
|
6 |
//#define DEBUG_MMU
|
7 |
//#define DEBUG_MXCC
|
8 |
//#define DEBUG_UNALIGNED
|
9 |
//#define DEBUG_UNASSIGNED
|
10 |
//#define DEBUG_ASI
|
11 |
|
12 |
#ifdef DEBUG_MMU
|
13 |
#define DPRINTF_MMU(fmt, args...) \
|
14 |
do { printf("MMU: " fmt , ##args); } while (0) |
15 |
#else
|
16 |
#define DPRINTF_MMU(fmt, args...)
|
17 |
#endif
|
18 |
|
19 |
#ifdef DEBUG_MXCC
|
20 |
#define DPRINTF_MXCC(fmt, args...) \
|
21 |
do { printf("MXCC: " fmt , ##args); } while (0) |
22 |
#else
|
23 |
#define DPRINTF_MXCC(fmt, args...)
|
24 |
#endif
|
25 |
|
26 |
#ifdef DEBUG_ASI
|
27 |
#define DPRINTF_ASI(fmt, args...) \
|
28 |
do { printf("ASI: " fmt , ##args); } while (0) |
29 |
#else
|
30 |
#define DPRINTF_ASI(fmt, args...)
|
31 |
#endif
|
32 |
|
33 |
void raise_exception(int tt) |
34 |
{ |
35 |
env->exception_index = tt; |
36 |
cpu_loop_exit(); |
37 |
} |
38 |
|
39 |
void helper_trap(target_ulong nb_trap)
|
40 |
{ |
41 |
env->exception_index = TT_TRAP + (nb_trap & 0x7f);
|
42 |
cpu_loop_exit(); |
43 |
} |
44 |
|
45 |
void helper_trapcc(target_ulong nb_trap, target_ulong do_trap)
|
46 |
{ |
47 |
if (do_trap) {
|
48 |
env->exception_index = TT_TRAP + (nb_trap & 0x7f);
|
49 |
cpu_loop_exit(); |
50 |
} |
51 |
} |
52 |
|
53 |
void helper_check_ieee_exceptions(void) |
54 |
{ |
55 |
target_ulong status; |
56 |
|
57 |
status = get_float_exception_flags(&env->fp_status); |
58 |
if (status) {
|
59 |
/* Copy IEEE 754 flags into FSR */
|
60 |
if (status & float_flag_invalid)
|
61 |
env->fsr |= FSR_NVC; |
62 |
if (status & float_flag_overflow)
|
63 |
env->fsr |= FSR_OFC; |
64 |
if (status & float_flag_underflow)
|
65 |
env->fsr |= FSR_UFC; |
66 |
if (status & float_flag_divbyzero)
|
67 |
env->fsr |= FSR_DZC; |
68 |
if (status & float_flag_inexact)
|
69 |
env->fsr |= FSR_NXC; |
70 |
|
71 |
if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) { |
72 |
/* Unmasked exception, generate a trap */
|
73 |
env->fsr |= FSR_FTT_IEEE_EXCP; |
74 |
raise_exception(TT_FP_EXCP); |
75 |
} else {
|
76 |
/* Accumulate exceptions */
|
77 |
env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
|
78 |
} |
79 |
} |
80 |
} |
81 |
|
82 |
void helper_clear_float_exceptions(void) |
83 |
{ |
84 |
set_float_exception_flags(0, &env->fp_status);
|
85 |
} |
86 |
|
87 |
#ifdef USE_INT_TO_FLOAT_HELPERS
|
88 |
void do_fitos(void) |
89 |
{ |
90 |
FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status); |
91 |
} |
92 |
|
93 |
void do_fitod(void) |
94 |
{ |
95 |
DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status); |
96 |
} |
97 |
|
98 |
#if defined(CONFIG_USER_ONLY)
|
99 |
void do_fitoq(void) |
100 |
{ |
101 |
QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status); |
102 |
} |
103 |
#endif
|
104 |
|
105 |
#ifdef TARGET_SPARC64
|
106 |
void do_fxtos(void) |
107 |
{ |
108 |
FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status); |
109 |
} |
110 |
|
111 |
void do_fxtod(void) |
112 |
{ |
113 |
DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status); |
114 |
} |
115 |
|
116 |
#if defined(CONFIG_USER_ONLY)
|
117 |
void do_fxtoq(void) |
118 |
{ |
119 |
QT0 = int64_to_float128(*((int32_t *)&DT1), &env->fp_status); |
120 |
} |
121 |
#endif
|
122 |
#endif
|
123 |
#endif
|
124 |
|
125 |
void helper_fabss(void) |
126 |
{ |
127 |
FT0 = float32_abs(FT1); |
128 |
} |
129 |
|
130 |
#ifdef TARGET_SPARC64
|
131 |
void helper_fabsd(void) |
132 |
{ |
133 |
DT0 = float64_abs(DT1); |
134 |
} |
135 |
|
136 |
#if defined(CONFIG_USER_ONLY)
|
137 |
void helper_fabsq(void) |
138 |
{ |
139 |
QT0 = float128_abs(QT1); |
140 |
} |
141 |
#endif
|
142 |
#endif
|
143 |
|
144 |
void helper_fsqrts(void) |
145 |
{ |
146 |
FT0 = float32_sqrt(FT1, &env->fp_status); |
147 |
} |
148 |
|
149 |
void helper_fsqrtd(void) |
150 |
{ |
151 |
DT0 = float64_sqrt(DT1, &env->fp_status); |
152 |
} |
153 |
|
154 |
#if defined(CONFIG_USER_ONLY)
|
155 |
void helper_fsqrtq(void) |
156 |
{ |
157 |
QT0 = float128_sqrt(QT1, &env->fp_status); |
158 |
} |
159 |
#endif
|
160 |
|
161 |
#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
|
162 |
void glue(helper_, name) (void) \ |
163 |
{ \ |
164 |
target_ulong new_fsr; \ |
165 |
\ |
166 |
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \ |
167 |
switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
|
168 |
case float_relation_unordered: \
|
169 |
new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \ |
170 |
if ((env->fsr & FSR_NVM) || TRAP) { \
|
171 |
env->fsr |= new_fsr; \ |
172 |
env->fsr |= FSR_NVC; \ |
173 |
env->fsr |= FSR_FTT_IEEE_EXCP; \ |
174 |
raise_exception(TT_FP_EXCP); \ |
175 |
} else { \
|
176 |
env->fsr |= FSR_NVA; \ |
177 |
} \ |
178 |
break; \
|
179 |
case float_relation_less: \
|
180 |
new_fsr = FSR_FCC0 << FS; \ |
181 |
break; \
|
182 |
case float_relation_greater: \
|
183 |
new_fsr = FSR_FCC1 << FS; \ |
184 |
break; \
|
185 |
default: \
|
186 |
new_fsr = 0; \
|
187 |
break; \
|
188 |
} \ |
189 |
env->fsr |= new_fsr; \ |
190 |
} |
191 |
|
192 |
GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0); |
193 |
GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0); |
194 |
|
195 |
GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1); |
196 |
GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1); |
197 |
|
198 |
#ifdef CONFIG_USER_ONLY
|
199 |
GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0); |
200 |
GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1); |
201 |
#endif
|
202 |
|
203 |
#ifdef TARGET_SPARC64
|
204 |
GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0); |
205 |
GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0); |
206 |
|
207 |
GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0); |
208 |
GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0); |
209 |
|
210 |
GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0); |
211 |
GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0); |
212 |
|
213 |
GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1); |
214 |
GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1); |
215 |
|
216 |
GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1); |
217 |
GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1); |
218 |
|
219 |
GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1); |
220 |
GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1); |
221 |
#ifdef CONFIG_USER_ONLY
|
222 |
GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0); |
223 |
GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0); |
224 |
GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0); |
225 |
GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1); |
226 |
GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1); |
227 |
GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1); |
228 |
#endif
|
229 |
#endif
|
230 |
|
231 |
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && defined(DEBUG_MXCC)
|
232 |
static void dump_mxcc(CPUState *env) |
233 |
{ |
234 |
printf("mxccdata: %016llx %016llx %016llx %016llx\n",
|
235 |
env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]); |
236 |
printf("mxccregs: %016llx %016llx %016llx %016llx\n"
|
237 |
" %016llx %016llx %016llx %016llx\n",
|
238 |
env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3], |
239 |
env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]); |
240 |
} |
241 |
#endif
|
242 |
|
243 |
#if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
|
244 |
&& defined(DEBUG_ASI) |
245 |
static void dump_asi(const char *txt, target_ulong addr, int asi, int size, |
246 |
uint64_t r1) |
247 |
{ |
248 |
switch (size)
|
249 |
{ |
250 |
case 1: |
251 |
DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, |
252 |
addr, asi, r1 & 0xff);
|
253 |
break;
|
254 |
case 2: |
255 |
DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, |
256 |
addr, asi, r1 & 0xffff);
|
257 |
break;
|
258 |
case 4: |
259 |
DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, |
260 |
addr, asi, r1 & 0xffffffff);
|
261 |
break;
|
262 |
case 8: |
263 |
DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, |
264 |
addr, asi, r1); |
265 |
break;
|
266 |
} |
267 |
} |
268 |
#endif
|
269 |
|
270 |
#ifndef TARGET_SPARC64
|
271 |
#ifndef CONFIG_USER_ONLY
|
272 |
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
273 |
{ |
274 |
uint64_t ret = 0;
|
275 |
#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
|
276 |
uint32_t last_addr = addr; |
277 |
#endif
|
278 |
|
279 |
switch (asi) {
|
280 |
case 2: /* SuperSparc MXCC registers */ |
281 |
switch (addr) {
|
282 |
case 0x01c00a00: /* MXCC control register */ |
283 |
if (size == 8) |
284 |
ret = env->mxccregs[3];
|
285 |
else
|
286 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
287 |
break;
|
288 |
case 0x01c00a04: /* MXCC control register */ |
289 |
if (size == 4) |
290 |
ret = env->mxccregs[3];
|
291 |
else
|
292 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
293 |
break;
|
294 |
case 0x01c00c00: /* Module reset register */ |
295 |
if (size == 8) { |
296 |
ret = env->mxccregs[5];
|
297 |
// should we do something here?
|
298 |
} else
|
299 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
300 |
break;
|
301 |
case 0x01c00f00: /* MBus port address register */ |
302 |
if (size == 8) |
303 |
ret = env->mxccregs[7];
|
304 |
else
|
305 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
306 |
break;
|
307 |
default:
|
308 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
|
309 |
break;
|
310 |
} |
311 |
DPRINTF_MXCC("asi = %d, size = %d, sign = %d, addr = %08x -> ret = %08x,"
|
312 |
"addr = %08x\n", asi, size, sign, last_addr, ret, addr);
|
313 |
#ifdef DEBUG_MXCC
|
314 |
dump_mxcc(env); |
315 |
#endif
|
316 |
break;
|
317 |
case 3: /* MMU probe */ |
318 |
{ |
319 |
int mmulev;
|
320 |
|
321 |
mmulev = (addr >> 8) & 15; |
322 |
if (mmulev > 4) |
323 |
ret = 0;
|
324 |
else
|
325 |
ret = mmu_probe(env, addr, mmulev); |
326 |
DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", |
327 |
addr, mmulev, ret); |
328 |
} |
329 |
break;
|
330 |
case 4: /* read MMU regs */ |
331 |
{ |
332 |
int reg = (addr >> 8) & 0x1f; |
333 |
|
334 |
ret = env->mmuregs[reg]; |
335 |
if (reg == 3) /* Fault status cleared on read */ |
336 |
env->mmuregs[3] = 0; |
337 |
else if (reg == 0x13) /* Fault status read */ |
338 |
ret = env->mmuregs[3];
|
339 |
else if (reg == 0x14) /* Fault address read */ |
340 |
ret = env->mmuregs[4];
|
341 |
DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret); |
342 |
} |
343 |
break;
|
344 |
case 5: // Turbosparc ITLB Diagnostic |
345 |
case 6: // Turbosparc DTLB Diagnostic |
346 |
case 7: // Turbosparc IOTLB Diagnostic |
347 |
break;
|
348 |
case 9: /* Supervisor code access */ |
349 |
switch(size) {
|
350 |
case 1: |
351 |
ret = ldub_code(addr); |
352 |
break;
|
353 |
case 2: |
354 |
ret = lduw_code(addr & ~1);
|
355 |
break;
|
356 |
default:
|
357 |
case 4: |
358 |
ret = ldl_code(addr & ~3);
|
359 |
break;
|
360 |
case 8: |
361 |
ret = ldq_code(addr & ~7);
|
362 |
break;
|
363 |
} |
364 |
break;
|
365 |
case 0xa: /* User data access */ |
366 |
switch(size) {
|
367 |
case 1: |
368 |
ret = ldub_user(addr); |
369 |
break;
|
370 |
case 2: |
371 |
ret = lduw_user(addr & ~1);
|
372 |
break;
|
373 |
default:
|
374 |
case 4: |
375 |
ret = ldl_user(addr & ~3);
|
376 |
break;
|
377 |
case 8: |
378 |
ret = ldq_user(addr & ~7);
|
379 |
break;
|
380 |
} |
381 |
break;
|
382 |
case 0xb: /* Supervisor data access */ |
383 |
switch(size) {
|
384 |
case 1: |
385 |
ret = ldub_kernel(addr); |
386 |
break;
|
387 |
case 2: |
388 |
ret = lduw_kernel(addr & ~1);
|
389 |
break;
|
390 |
default:
|
391 |
case 4: |
392 |
ret = ldl_kernel(addr & ~3);
|
393 |
break;
|
394 |
case 8: |
395 |
ret = ldq_kernel(addr & ~7);
|
396 |
break;
|
397 |
} |
398 |
break;
|
399 |
case 0xc: /* I-cache tag */ |
400 |
case 0xd: /* I-cache data */ |
401 |
case 0xe: /* D-cache tag */ |
402 |
case 0xf: /* D-cache data */ |
403 |
break;
|
404 |
case 0x20: /* MMU passthrough */ |
405 |
switch(size) {
|
406 |
case 1: |
407 |
ret = ldub_phys(addr); |
408 |
break;
|
409 |
case 2: |
410 |
ret = lduw_phys(addr & ~1);
|
411 |
break;
|
412 |
default:
|
413 |
case 4: |
414 |
ret = ldl_phys(addr & ~3);
|
415 |
break;
|
416 |
case 8: |
417 |
ret = ldq_phys(addr & ~7);
|
418 |
break;
|
419 |
} |
420 |
break;
|
421 |
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
422 |
switch(size) {
|
423 |
case 1: |
424 |
ret = ldub_phys((target_phys_addr_t)addr |
425 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
426 |
break;
|
427 |
case 2: |
428 |
ret = lduw_phys((target_phys_addr_t)(addr & ~1)
|
429 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
430 |
break;
|
431 |
default:
|
432 |
case 4: |
433 |
ret = ldl_phys((target_phys_addr_t)(addr & ~3)
|
434 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
435 |
break;
|
436 |
case 8: |
437 |
ret = ldq_phys((target_phys_addr_t)(addr & ~7)
|
438 |
| ((target_phys_addr_t)(asi & 0xf) << 32)); |
439 |
break;
|
440 |
} |
441 |
break;
|
442 |
case 0x30: // Turbosparc secondary cache diagnostic |
443 |
case 0x31: // Turbosparc RAM snoop |
444 |
case 0x32: // Turbosparc page table descriptor diagnostic |
445 |
case 0x39: /* data cache diagnostic register */ |
446 |
ret = 0;
|
447 |
break;
|
448 |
case 8: /* User code access, XXX */ |
449 |
default:
|
450 |
do_unassigned_access(addr, 0, 0, asi); |
451 |
ret = 0;
|
452 |
break;
|
453 |
} |
454 |
if (sign) {
|
455 |
switch(size) {
|
456 |
case 1: |
457 |
ret = (int8_t) ret; |
458 |
break;
|
459 |
case 2: |
460 |
ret = (int16_t) ret; |
461 |
break;
|
462 |
case 4: |
463 |
ret = (int32_t) ret; |
464 |
break;
|
465 |
default:
|
466 |
break;
|
467 |
} |
468 |
} |
469 |
#ifdef DEBUG_ASI
|
470 |
dump_asi("read ", last_addr, asi, size, ret);
|
471 |
#endif
|
472 |
return ret;
|
473 |
} |
474 |
|
475 |
void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) |
476 |
{ |
477 |
switch(asi) {
|
478 |
case 2: /* SuperSparc MXCC registers */ |
479 |
switch (addr) {
|
480 |
case 0x01c00000: /* MXCC stream data register 0 */ |
481 |
if (size == 8) |
482 |
env->mxccdata[0] = val;
|
483 |
else
|
484 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
485 |
break;
|
486 |
case 0x01c00008: /* MXCC stream data register 1 */ |
487 |
if (size == 8) |
488 |
env->mxccdata[1] = val;
|
489 |
else
|
490 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
491 |
break;
|
492 |
case 0x01c00010: /* MXCC stream data register 2 */ |
493 |
if (size == 8) |
494 |
env->mxccdata[2] = val;
|
495 |
else
|
496 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
497 |
break;
|
498 |
case 0x01c00018: /* MXCC stream data register 3 */ |
499 |
if (size == 8) |
500 |
env->mxccdata[3] = val;
|
501 |
else
|
502 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
503 |
break;
|
504 |
case 0x01c00100: /* MXCC stream source */ |
505 |
if (size == 8) |
506 |
env->mxccregs[0] = val;
|
507 |
else
|
508 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
509 |
env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 0); |
510 |
env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 8); |
511 |
env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 16); |
512 |
env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) + 24); |
513 |
break;
|
514 |
case 0x01c00200: /* MXCC stream destination */ |
515 |
if (size == 8) |
516 |
env->mxccregs[1] = val;
|
517 |
else
|
518 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
519 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0, env->mxccdata[0]); |
520 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8, env->mxccdata[1]); |
521 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16, env->mxccdata[2]); |
522 |
stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24, env->mxccdata[3]); |
523 |
break;
|
524 |
case 0x01c00a00: /* MXCC control register */ |
525 |
if (size == 8) |
526 |
env->mxccregs[3] = val;
|
527 |
else
|
528 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
529 |
break;
|
530 |
case 0x01c00a04: /* MXCC control register */ |
531 |
if (size == 4) |
532 |
env->mxccregs[3] = (env->mxccregs[0xa] & 0xffffffff00000000ULL) | val; |
533 |
else
|
534 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
535 |
break;
|
536 |
case 0x01c00e00: /* MXCC error register */ |
537 |
// writing a 1 bit clears the error
|
538 |
if (size == 8) |
539 |
env->mxccregs[6] &= ~val;
|
540 |
else
|
541 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
542 |
break;
|
543 |
case 0x01c00f00: /* MBus port address register */ |
544 |
if (size == 8) |
545 |
env->mxccregs[7] = val;
|
546 |
else
|
547 |
DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr, size);
|
548 |
break;
|
549 |
default:
|
550 |
DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr, size);
|
551 |
break;
|
552 |
} |
553 |
DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %08x\n", asi, size, addr, val);
|
554 |
#ifdef DEBUG_MXCC
|
555 |
dump_mxcc(env); |
556 |
#endif
|
557 |
break;
|
558 |
case 3: /* MMU flush */ |
559 |
{ |
560 |
int mmulev;
|
561 |
|
562 |
mmulev = (addr >> 8) & 15; |
563 |
DPRINTF_MMU("mmu flush level %d\n", mmulev);
|
564 |
switch (mmulev) {
|
565 |
case 0: // flush page |
566 |
tlb_flush_page(env, addr & 0xfffff000);
|
567 |
break;
|
568 |
case 1: // flush segment (256k) |
569 |
case 2: // flush region (16M) |
570 |
case 3: // flush context (4G) |
571 |
case 4: // flush entire |
572 |
tlb_flush(env, 1);
|
573 |
break;
|
574 |
default:
|
575 |
break;
|
576 |
} |
577 |
#ifdef DEBUG_MMU
|
578 |
dump_mmu(env); |
579 |
#endif
|
580 |
} |
581 |
break;
|
582 |
case 4: /* write MMU regs */ |
583 |
{ |
584 |
int reg = (addr >> 8) & 0x1f; |
585 |
uint32_t oldreg; |
586 |
|
587 |
oldreg = env->mmuregs[reg]; |
588 |
switch(reg) {
|
589 |
case 0: // Control Register |
590 |
env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
|
591 |
(val & 0x00ffffff);
|
592 |
// Mappings generated during no-fault mode or MMU
|
593 |
// disabled mode are invalid in normal mode
|
594 |
if ((oldreg & (MMU_E | MMU_NF | env->mmu_bm)) !=
|
595 |
(env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm))) |
596 |
tlb_flush(env, 1);
|
597 |
break;
|
598 |
case 1: // Context Table Pointer Register |
599 |
env->mmuregs[reg] = val & env->mmu_ctpr_mask; |
600 |
break;
|
601 |
case 2: // Context Register |
602 |
env->mmuregs[reg] = val & env->mmu_cxr_mask; |
603 |
if (oldreg != env->mmuregs[reg]) {
|
604 |
/* we flush when the MMU context changes because
|
605 |
QEMU has no MMU context support */
|
606 |
tlb_flush(env, 1);
|
607 |
} |
608 |
break;
|
609 |
case 3: // Synchronous Fault Status Register with Clear |
610 |
case 4: // Synchronous Fault Address Register |
611 |
break;
|
612 |
case 0x10: // TLB Replacement Control Register |
613 |
env->mmuregs[reg] = val & env->mmu_trcr_mask; |
614 |
break;
|
615 |
case 0x13: // Synchronous Fault Status Register with Read and Clear |
616 |
env->mmuregs[3] = val & env->mmu_sfsr_mask;
|
617 |
break;
|
618 |
case 0x14: // Synchronous Fault Address Register |
619 |
env->mmuregs[4] = val;
|
620 |
break;
|
621 |
default:
|
622 |
env->mmuregs[reg] = val; |
623 |
break;
|
624 |
} |
625 |
if (oldreg != env->mmuregs[reg]) {
|
626 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
|
627 |
} |
628 |
#ifdef DEBUG_MMU
|
629 |
dump_mmu(env); |
630 |
#endif
|
631 |
} |
632 |
break;
|
633 |
case 5: // Turbosparc ITLB Diagnostic |
634 |
case 6: // Turbosparc DTLB Diagnostic |
635 |
case 7: // Turbosparc IOTLB Diagnostic |
636 |
break;
|
637 |
case 0xa: /* User data access */ |
638 |
switch(size) {
|
639 |
case 1: |
640 |
stb_user(addr, val); |
641 |
break;
|
642 |
case 2: |
643 |
stw_user(addr & ~1, val);
|
644 |
break;
|
645 |
default:
|
646 |
case 4: |
647 |
stl_user(addr & ~3, val);
|
648 |
break;
|
649 |
case 8: |
650 |
stq_user(addr & ~7, val);
|
651 |
break;
|
652 |
} |
653 |
break;
|
654 |
case 0xb: /* Supervisor data access */ |
655 |
switch(size) {
|
656 |
case 1: |
657 |
stb_kernel(addr, val); |
658 |
break;
|
659 |
case 2: |
660 |
stw_kernel(addr & ~1, val);
|
661 |
break;
|
662 |
default:
|
663 |
case 4: |
664 |
stl_kernel(addr & ~3, val);
|
665 |
break;
|
666 |
case 8: |
667 |
stq_kernel(addr & ~7, val);
|
668 |
break;
|
669 |
} |
670 |
break;
|
671 |
case 0xc: /* I-cache tag */ |
672 |
case 0xd: /* I-cache data */ |
673 |
case 0xe: /* D-cache tag */ |
674 |
case 0xf: /* D-cache data */ |
675 |
case 0x10: /* I/D-cache flush page */ |
676 |
case 0x11: /* I/D-cache flush segment */ |
677 |
case 0x12: /* I/D-cache flush region */ |
678 |
case 0x13: /* I/D-cache flush context */ |
679 |
case 0x14: /* I/D-cache flush user */ |
680 |
break;
|
681 |
case 0x17: /* Block copy, sta access */ |
682 |
{ |
683 |
// val = src
|
684 |
// addr = dst
|
685 |
// copy 32 bytes
|
686 |
unsigned int i; |
687 |
uint32_t src = val & ~3, dst = addr & ~3, temp; |
688 |
|
689 |
for (i = 0; i < 32; i += 4, src += 4, dst += 4) { |
690 |
temp = ldl_kernel(src); |
691 |
stl_kernel(dst, temp); |
692 |
} |
693 |
} |
694 |
break;
|
695 |
case 0x1f: /* Block fill, stda access */ |
696 |
{ |
697 |
// addr = dst
|
698 |
// fill 32 bytes with val
|
699 |
unsigned int i; |
700 |
uint32_t dst = addr & 7;
|
701 |
|
702 |
for (i = 0; i < 32; i += 8, dst += 8) |
703 |
stq_kernel(dst, val); |
704 |
} |
705 |
break;
|
706 |
case 0x20: /* MMU passthrough */ |
707 |
{ |
708 |
switch(size) {
|
709 |
case 1: |
710 |
stb_phys(addr, val); |
711 |
break;
|
712 |
case 2: |
713 |
stw_phys(addr & ~1, val);
|
714 |
break;
|
715 |
case 4: |
716 |
default:
|
717 |
stl_phys(addr & ~3, val);
|
718 |
break;
|
719 |
case 8: |
720 |
stq_phys(addr & ~7, val);
|
721 |
break;
|
722 |
} |
723 |
} |
724 |
break;
|
725 |
case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ |
726 |
{ |
727 |
switch(size) {
|
728 |
case 1: |
729 |
stb_phys((target_phys_addr_t)addr |
730 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val); |
731 |
break;
|
732 |
case 2: |
733 |
stw_phys((target_phys_addr_t)(addr & ~1)
|
734 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val); |
735 |
break;
|
736 |
case 4: |
737 |
default:
|
738 |
stl_phys((target_phys_addr_t)(addr & ~3)
|
739 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val); |
740 |
break;
|
741 |
case 8: |
742 |
stq_phys((target_phys_addr_t)(addr & ~7)
|
743 |
| ((target_phys_addr_t)(asi & 0xf) << 32), val); |
744 |
break;
|
745 |
} |
746 |
} |
747 |
break;
|
748 |
case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic |
749 |
case 0x31: // store buffer data, Ross RT620 I-cache flush or |
750 |
// Turbosparc snoop RAM
|
751 |
case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic |
752 |
case 0x36: /* I-cache flash clear */ |
753 |
case 0x37: /* D-cache flash clear */ |
754 |
case 0x38: /* breakpoint diagnostics */ |
755 |
case 0x4c: /* breakpoint action */ |
756 |
break;
|
757 |
case 8: /* User code access, XXX */ |
758 |
case 9: /* Supervisor code access, XXX */ |
759 |
default:
|
760 |
do_unassigned_access(addr, 1, 0, asi); |
761 |
break;
|
762 |
} |
763 |
#ifdef DEBUG_ASI
|
764 |
dump_asi("write", addr, asi, size, val);
|
765 |
#endif
|
766 |
} |
767 |
|
768 |
#endif /* CONFIG_USER_ONLY */ |
769 |
#else /* TARGET_SPARC64 */ |
770 |
|
771 |
#ifdef CONFIG_USER_ONLY
|
772 |
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
773 |
{ |
774 |
uint64_t ret = 0;
|
775 |
#if defined(DEBUG_ASI)
|
776 |
target_ulong last_addr = addr; |
777 |
#endif
|
778 |
|
779 |
if (asi < 0x80) |
780 |
raise_exception(TT_PRIV_ACT); |
781 |
|
782 |
switch (asi) {
|
783 |
case 0x80: // Primary |
784 |
case 0x82: // Primary no-fault |
785 |
case 0x88: // Primary LE |
786 |
case 0x8a: // Primary no-fault LE |
787 |
{ |
788 |
switch(size) {
|
789 |
case 1: |
790 |
ret = ldub_raw(addr); |
791 |
break;
|
792 |
case 2: |
793 |
ret = lduw_raw(addr & ~1);
|
794 |
break;
|
795 |
case 4: |
796 |
ret = ldl_raw(addr & ~3);
|
797 |
break;
|
798 |
default:
|
799 |
case 8: |
800 |
ret = ldq_raw(addr & ~7);
|
801 |
break;
|
802 |
} |
803 |
} |
804 |
break;
|
805 |
case 0x81: // Secondary |
806 |
case 0x83: // Secondary no-fault |
807 |
case 0x89: // Secondary LE |
808 |
case 0x8b: // Secondary no-fault LE |
809 |
// XXX
|
810 |
break;
|
811 |
default:
|
812 |
break;
|
813 |
} |
814 |
|
815 |
/* Convert from little endian */
|
816 |
switch (asi) {
|
817 |
case 0x88: // Primary LE |
818 |
case 0x89: // Secondary LE |
819 |
case 0x8a: // Primary no-fault LE |
820 |
case 0x8b: // Secondary no-fault LE |
821 |
switch(size) {
|
822 |
case 2: |
823 |
ret = bswap16(ret); |
824 |
break;
|
825 |
case 4: |
826 |
ret = bswap32(ret); |
827 |
break;
|
828 |
case 8: |
829 |
ret = bswap64(ret); |
830 |
break;
|
831 |
default:
|
832 |
break;
|
833 |
} |
834 |
default:
|
835 |
break;
|
836 |
} |
837 |
|
838 |
/* Convert to signed number */
|
839 |
if (sign) {
|
840 |
switch(size) {
|
841 |
case 1: |
842 |
ret = (int8_t) ret; |
843 |
break;
|
844 |
case 2: |
845 |
ret = (int16_t) ret; |
846 |
break;
|
847 |
case 4: |
848 |
ret = (int32_t) ret; |
849 |
break;
|
850 |
default:
|
851 |
break;
|
852 |
} |
853 |
} |
854 |
#ifdef DEBUG_ASI
|
855 |
dump_asi("read ", last_addr, asi, size, ret);
|
856 |
#endif
|
857 |
return ret;
|
858 |
} |
859 |
|
860 |
void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
861 |
{ |
862 |
#ifdef DEBUG_ASI
|
863 |
dump_asi("write", addr, asi, size, val);
|
864 |
#endif
|
865 |
if (asi < 0x80) |
866 |
raise_exception(TT_PRIV_ACT); |
867 |
|
868 |
/* Convert to little endian */
|
869 |
switch (asi) {
|
870 |
case 0x88: // Primary LE |
871 |
case 0x89: // Secondary LE |
872 |
switch(size) {
|
873 |
case 2: |
874 |
addr = bswap16(addr); |
875 |
break;
|
876 |
case 4: |
877 |
addr = bswap32(addr); |
878 |
break;
|
879 |
case 8: |
880 |
addr = bswap64(addr); |
881 |
break;
|
882 |
default:
|
883 |
break;
|
884 |
} |
885 |
default:
|
886 |
break;
|
887 |
} |
888 |
|
889 |
switch(asi) {
|
890 |
case 0x80: // Primary |
891 |
case 0x88: // Primary LE |
892 |
{ |
893 |
switch(size) {
|
894 |
case 1: |
895 |
stb_raw(addr, val); |
896 |
break;
|
897 |
case 2: |
898 |
stw_raw(addr & ~1, val);
|
899 |
break;
|
900 |
case 4: |
901 |
stl_raw(addr & ~3, val);
|
902 |
break;
|
903 |
case 8: |
904 |
default:
|
905 |
stq_raw(addr & ~7, val);
|
906 |
break;
|
907 |
} |
908 |
} |
909 |
break;
|
910 |
case 0x81: // Secondary |
911 |
case 0x89: // Secondary LE |
912 |
// XXX
|
913 |
return;
|
914 |
|
915 |
case 0x82: // Primary no-fault, RO |
916 |
case 0x83: // Secondary no-fault, RO |
917 |
case 0x8a: // Primary no-fault LE, RO |
918 |
case 0x8b: // Secondary no-fault LE, RO |
919 |
default:
|
920 |
do_unassigned_access(addr, 1, 0, 1); |
921 |
return;
|
922 |
} |
923 |
} |
924 |
|
925 |
#else /* CONFIG_USER_ONLY */ |
926 |
|
927 |
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) |
928 |
{ |
929 |
uint64_t ret = 0;
|
930 |
#if defined(DEBUG_ASI)
|
931 |
target_ulong last_addr = addr; |
932 |
#endif
|
933 |
|
934 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
935 |
|| (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) |
936 |
raise_exception(TT_PRIV_ACT); |
937 |
|
938 |
switch (asi) {
|
939 |
case 0x10: // As if user primary |
940 |
case 0x18: // As if user primary LE |
941 |
case 0x80: // Primary |
942 |
case 0x82: // Primary no-fault |
943 |
case 0x88: // Primary LE |
944 |
case 0x8a: // Primary no-fault LE |
945 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
946 |
if (env->hpstate & HS_PRIV) {
|
947 |
switch(size) {
|
948 |
case 1: |
949 |
ret = ldub_hypv(addr); |
950 |
break;
|
951 |
case 2: |
952 |
ret = lduw_hypv(addr & ~1);
|
953 |
break;
|
954 |
case 4: |
955 |
ret = ldl_hypv(addr & ~3);
|
956 |
break;
|
957 |
default:
|
958 |
case 8: |
959 |
ret = ldq_hypv(addr & ~7);
|
960 |
break;
|
961 |
} |
962 |
} else {
|
963 |
switch(size) {
|
964 |
case 1: |
965 |
ret = ldub_kernel(addr); |
966 |
break;
|
967 |
case 2: |
968 |
ret = lduw_kernel(addr & ~1);
|
969 |
break;
|
970 |
case 4: |
971 |
ret = ldl_kernel(addr & ~3);
|
972 |
break;
|
973 |
default:
|
974 |
case 8: |
975 |
ret = ldq_kernel(addr & ~7);
|
976 |
break;
|
977 |
} |
978 |
} |
979 |
} else {
|
980 |
switch(size) {
|
981 |
case 1: |
982 |
ret = ldub_user(addr); |
983 |
break;
|
984 |
case 2: |
985 |
ret = lduw_user(addr & ~1);
|
986 |
break;
|
987 |
case 4: |
988 |
ret = ldl_user(addr & ~3);
|
989 |
break;
|
990 |
default:
|
991 |
case 8: |
992 |
ret = ldq_user(addr & ~7);
|
993 |
break;
|
994 |
} |
995 |
} |
996 |
break;
|
997 |
case 0x14: // Bypass |
998 |
case 0x15: // Bypass, non-cacheable |
999 |
case 0x1c: // Bypass LE |
1000 |
case 0x1d: // Bypass, non-cacheable LE |
1001 |
{ |
1002 |
switch(size) {
|
1003 |
case 1: |
1004 |
ret = ldub_phys(addr); |
1005 |
break;
|
1006 |
case 2: |
1007 |
ret = lduw_phys(addr & ~1);
|
1008 |
break;
|
1009 |
case 4: |
1010 |
ret = ldl_phys(addr & ~3);
|
1011 |
break;
|
1012 |
default:
|
1013 |
case 8: |
1014 |
ret = ldq_phys(addr & ~7);
|
1015 |
break;
|
1016 |
} |
1017 |
break;
|
1018 |
} |
1019 |
case 0x04: // Nucleus |
1020 |
case 0x0c: // Nucleus Little Endian (LE) |
1021 |
case 0x11: // As if user secondary |
1022 |
case 0x19: // As if user secondary LE |
1023 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
1024 |
case 0x2c: // Nucleus quad LDD 128 bit atomic |
1025 |
case 0x4a: // UPA config |
1026 |
case 0x81: // Secondary |
1027 |
case 0x83: // Secondary no-fault |
1028 |
case 0x89: // Secondary LE |
1029 |
case 0x8b: // Secondary no-fault LE |
1030 |
// XXX
|
1031 |
break;
|
1032 |
case 0x45: // LSU |
1033 |
ret = env->lsu; |
1034 |
break;
|
1035 |
case 0x50: // I-MMU regs |
1036 |
{ |
1037 |
int reg = (addr >> 3) & 0xf; |
1038 |
|
1039 |
ret = env->immuregs[reg]; |
1040 |
break;
|
1041 |
} |
1042 |
case 0x51: // I-MMU 8k TSB pointer |
1043 |
case 0x52: // I-MMU 64k TSB pointer |
1044 |
case 0x55: // I-MMU data access |
1045 |
// XXX
|
1046 |
break;
|
1047 |
case 0x56: // I-MMU tag read |
1048 |
{ |
1049 |
unsigned int i; |
1050 |
|
1051 |
for (i = 0; i < 64; i++) { |
1052 |
// Valid, ctx match, vaddr match
|
1053 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 && |
1054 |
env->itlb_tag[i] == addr) { |
1055 |
ret = env->itlb_tag[i]; |
1056 |
break;
|
1057 |
} |
1058 |
} |
1059 |
break;
|
1060 |
} |
1061 |
case 0x58: // D-MMU regs |
1062 |
{ |
1063 |
int reg = (addr >> 3) & 0xf; |
1064 |
|
1065 |
ret = env->dmmuregs[reg]; |
1066 |
break;
|
1067 |
} |
1068 |
case 0x5e: // D-MMU tag read |
1069 |
{ |
1070 |
unsigned int i; |
1071 |
|
1072 |
for (i = 0; i < 64; i++) { |
1073 |
// Valid, ctx match, vaddr match
|
1074 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 && |
1075 |
env->dtlb_tag[i] == addr) { |
1076 |
ret = env->dtlb_tag[i]; |
1077 |
break;
|
1078 |
} |
1079 |
} |
1080 |
break;
|
1081 |
} |
1082 |
case 0x59: // D-MMU 8k TSB pointer |
1083 |
case 0x5a: // D-MMU 64k TSB pointer |
1084 |
case 0x5b: // D-MMU data pointer |
1085 |
case 0x5d: // D-MMU data access |
1086 |
case 0x48: // Interrupt dispatch, RO |
1087 |
case 0x49: // Interrupt data receive |
1088 |
case 0x7f: // Incoming interrupt vector, RO |
1089 |
// XXX
|
1090 |
break;
|
1091 |
case 0x54: // I-MMU data in, WO |
1092 |
case 0x57: // I-MMU demap, WO |
1093 |
case 0x5c: // D-MMU data in, WO |
1094 |
case 0x5f: // D-MMU demap, WO |
1095 |
case 0x77: // Interrupt vector, WO |
1096 |
default:
|
1097 |
do_unassigned_access(addr, 0, 0, 1); |
1098 |
ret = 0;
|
1099 |
break;
|
1100 |
} |
1101 |
|
1102 |
/* Convert from little endian */
|
1103 |
switch (asi) {
|
1104 |
case 0x0c: // Nucleus Little Endian (LE) |
1105 |
case 0x18: // As if user primary LE |
1106 |
case 0x19: // As if user secondary LE |
1107 |
case 0x1c: // Bypass LE |
1108 |
case 0x1d: // Bypass, non-cacheable LE |
1109 |
case 0x88: // Primary LE |
1110 |
case 0x89: // Secondary LE |
1111 |
case 0x8a: // Primary no-fault LE |
1112 |
case 0x8b: // Secondary no-fault LE |
1113 |
switch(size) {
|
1114 |
case 2: |
1115 |
ret = bswap16(ret); |
1116 |
break;
|
1117 |
case 4: |
1118 |
ret = bswap32(ret); |
1119 |
break;
|
1120 |
case 8: |
1121 |
ret = bswap64(ret); |
1122 |
break;
|
1123 |
default:
|
1124 |
break;
|
1125 |
} |
1126 |
default:
|
1127 |
break;
|
1128 |
} |
1129 |
|
1130 |
/* Convert to signed number */
|
1131 |
if (sign) {
|
1132 |
switch(size) {
|
1133 |
case 1: |
1134 |
ret = (int8_t) ret; |
1135 |
break;
|
1136 |
case 2: |
1137 |
ret = (int16_t) ret; |
1138 |
break;
|
1139 |
case 4: |
1140 |
ret = (int32_t) ret; |
1141 |
break;
|
1142 |
default:
|
1143 |
break;
|
1144 |
} |
1145 |
} |
1146 |
#ifdef DEBUG_ASI
|
1147 |
dump_asi("read ", last_addr, asi, size, ret);
|
1148 |
#endif
|
1149 |
return ret;
|
1150 |
} |
1151 |
|
1152 |
void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) |
1153 |
{ |
1154 |
#ifdef DEBUG_ASI
|
1155 |
dump_asi("write", addr, asi, size, val);
|
1156 |
#endif
|
1157 |
if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
1158 |
|| (asi >= 0x30 && asi < 0x80 && !(env->hpstate & HS_PRIV))) |
1159 |
raise_exception(TT_PRIV_ACT); |
1160 |
|
1161 |
/* Convert to little endian */
|
1162 |
switch (asi) {
|
1163 |
case 0x0c: // Nucleus Little Endian (LE) |
1164 |
case 0x18: // As if user primary LE |
1165 |
case 0x19: // As if user secondary LE |
1166 |
case 0x1c: // Bypass LE |
1167 |
case 0x1d: // Bypass, non-cacheable LE |
1168 |
case 0x88: // Primary LE |
1169 |
case 0x89: // Secondary LE |
1170 |
switch(size) {
|
1171 |
case 2: |
1172 |
addr = bswap16(addr); |
1173 |
break;
|
1174 |
case 4: |
1175 |
addr = bswap32(addr); |
1176 |
break;
|
1177 |
case 8: |
1178 |
addr = bswap64(addr); |
1179 |
break;
|
1180 |
default:
|
1181 |
break;
|
1182 |
} |
1183 |
default:
|
1184 |
break;
|
1185 |
} |
1186 |
|
1187 |
switch(asi) {
|
1188 |
case 0x10: // As if user primary |
1189 |
case 0x18: // As if user primary LE |
1190 |
case 0x80: // Primary |
1191 |
case 0x88: // Primary LE |
1192 |
if ((asi & 0x80) && (env->pstate & PS_PRIV)) { |
1193 |
if (env->hpstate & HS_PRIV) {
|
1194 |
switch(size) {
|
1195 |
case 1: |
1196 |
stb_hypv(addr, val); |
1197 |
break;
|
1198 |
case 2: |
1199 |
stw_hypv(addr & ~1, val);
|
1200 |
break;
|
1201 |
case 4: |
1202 |
stl_hypv(addr & ~3, val);
|
1203 |
break;
|
1204 |
case 8: |
1205 |
default:
|
1206 |
stq_hypv(addr & ~7, val);
|
1207 |
break;
|
1208 |
} |
1209 |
} else {
|
1210 |
switch(size) {
|
1211 |
case 1: |
1212 |
stb_kernel(addr, val); |
1213 |
break;
|
1214 |
case 2: |
1215 |
stw_kernel(addr & ~1, val);
|
1216 |
break;
|
1217 |
case 4: |
1218 |
stl_kernel(addr & ~3, val);
|
1219 |
break;
|
1220 |
case 8: |
1221 |
default:
|
1222 |
stq_kernel(addr & ~7, val);
|
1223 |
break;
|
1224 |
} |
1225 |
} |
1226 |
} else {
|
1227 |
switch(size) {
|
1228 |
case 1: |
1229 |
stb_user(addr, val); |
1230 |
break;
|
1231 |
case 2: |
1232 |
stw_user(addr & ~1, val);
|
1233 |
break;
|
1234 |
case 4: |
1235 |
stl_user(addr & ~3, val);
|
1236 |
break;
|
1237 |
case 8: |
1238 |
default:
|
1239 |
stq_user(addr & ~7, val);
|
1240 |
break;
|
1241 |
} |
1242 |
} |
1243 |
break;
|
1244 |
case 0x14: // Bypass |
1245 |
case 0x15: // Bypass, non-cacheable |
1246 |
case 0x1c: // Bypass LE |
1247 |
case 0x1d: // Bypass, non-cacheable LE |
1248 |
{ |
1249 |
switch(size) {
|
1250 |
case 1: |
1251 |
stb_phys(addr, val); |
1252 |
break;
|
1253 |
case 2: |
1254 |
stw_phys(addr & ~1, val);
|
1255 |
break;
|
1256 |
case 4: |
1257 |
stl_phys(addr & ~3, val);
|
1258 |
break;
|
1259 |
case 8: |
1260 |
default:
|
1261 |
stq_phys(addr & ~7, val);
|
1262 |
break;
|
1263 |
} |
1264 |
} |
1265 |
return;
|
1266 |
case 0x04: // Nucleus |
1267 |
case 0x0c: // Nucleus Little Endian (LE) |
1268 |
case 0x11: // As if user secondary |
1269 |
case 0x19: // As if user secondary LE |
1270 |
case 0x24: // Nucleus quad LDD 128 bit atomic |
1271 |
case 0x2c: // Nucleus quad LDD 128 bit atomic |
1272 |
case 0x4a: // UPA config |
1273 |
case 0x81: // Secondary |
1274 |
case 0x89: // Secondary LE |
1275 |
// XXX
|
1276 |
return;
|
1277 |
case 0x45: // LSU |
1278 |
{ |
1279 |
uint64_t oldreg; |
1280 |
|
1281 |
oldreg = env->lsu; |
1282 |
env->lsu = val & (DMMU_E | IMMU_E); |
1283 |
// Mappings generated during D/I MMU disabled mode are
|
1284 |
// invalid in normal mode
|
1285 |
if (oldreg != env->lsu) {
|
1286 |
DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n", oldreg, env->lsu); |
1287 |
#ifdef DEBUG_MMU
|
1288 |
dump_mmu(env); |
1289 |
#endif
|
1290 |
tlb_flush(env, 1);
|
1291 |
} |
1292 |
return;
|
1293 |
} |
1294 |
case 0x50: // I-MMU regs |
1295 |
{ |
1296 |
int reg = (addr >> 3) & 0xf; |
1297 |
uint64_t oldreg; |
1298 |
|
1299 |
oldreg = env->immuregs[reg]; |
1300 |
switch(reg) {
|
1301 |
case 0: // RO |
1302 |
case 4: |
1303 |
return;
|
1304 |
case 1: // Not in I-MMU |
1305 |
case 2: |
1306 |
case 7: |
1307 |
case 8: |
1308 |
return;
|
1309 |
case 3: // SFSR |
1310 |
if ((val & 1) == 0) |
1311 |
val = 0; // Clear SFSR |
1312 |
break;
|
1313 |
case 5: // TSB access |
1314 |
case 6: // Tag access |
1315 |
default:
|
1316 |
break;
|
1317 |
} |
1318 |
env->immuregs[reg] = val; |
1319 |
if (oldreg != env->immuregs[reg]) {
|
1320 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->immuregs[reg]); |
1321 |
} |
1322 |
#ifdef DEBUG_MMU
|
1323 |
dump_mmu(env); |
1324 |
#endif
|
1325 |
return;
|
1326 |
} |
1327 |
case 0x54: // I-MMU data in |
1328 |
{ |
1329 |
unsigned int i; |
1330 |
|
1331 |
// Try finding an invalid entry
|
1332 |
for (i = 0; i < 64; i++) { |
1333 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) { |
1334 |
env->itlb_tag[i] = env->immuregs[6];
|
1335 |
env->itlb_tte[i] = val; |
1336 |
return;
|
1337 |
} |
1338 |
} |
1339 |
// Try finding an unlocked entry
|
1340 |
for (i = 0; i < 64; i++) { |
1341 |
if ((env->itlb_tte[i] & 0x40) == 0) { |
1342 |
env->itlb_tag[i] = env->immuregs[6];
|
1343 |
env->itlb_tte[i] = val; |
1344 |
return;
|
1345 |
} |
1346 |
} |
1347 |
// error state?
|
1348 |
return;
|
1349 |
} |
1350 |
case 0x55: // I-MMU data access |
1351 |
{ |
1352 |
unsigned int i = (addr >> 3) & 0x3f; |
1353 |
|
1354 |
env->itlb_tag[i] = env->immuregs[6];
|
1355 |
env->itlb_tte[i] = val; |
1356 |
return;
|
1357 |
} |
1358 |
case 0x57: // I-MMU demap |
1359 |
// XXX
|
1360 |
return;
|
1361 |
case 0x58: // D-MMU regs |
1362 |
{ |
1363 |
int reg = (addr >> 3) & 0xf; |
1364 |
uint64_t oldreg; |
1365 |
|
1366 |
oldreg = env->dmmuregs[reg]; |
1367 |
switch(reg) {
|
1368 |
case 0: // RO |
1369 |
case 4: |
1370 |
return;
|
1371 |
case 3: // SFSR |
1372 |
if ((val & 1) == 0) { |
1373 |
val = 0; // Clear SFSR, Fault address |
1374 |
env->dmmuregs[4] = 0; |
1375 |
} |
1376 |
env->dmmuregs[reg] = val; |
1377 |
break;
|
1378 |
case 1: // Primary context |
1379 |
case 2: // Secondary context |
1380 |
case 5: // TSB access |
1381 |
case 6: // Tag access |
1382 |
case 7: // Virtual Watchpoint |
1383 |
case 8: // Physical Watchpoint |
1384 |
default:
|
1385 |
break;
|
1386 |
} |
1387 |
env->dmmuregs[reg] = val; |
1388 |
if (oldreg != env->dmmuregs[reg]) {
|
1389 |
DPRINTF_MMU("mmu change reg[%d]: 0x%08" PRIx64 " -> 0x%08" PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); |
1390 |
} |
1391 |
#ifdef DEBUG_MMU
|
1392 |
dump_mmu(env); |
1393 |
#endif
|
1394 |
return;
|
1395 |
} |
1396 |
case 0x5c: // D-MMU data in |
1397 |
{ |
1398 |
unsigned int i; |
1399 |
|
1400 |
// Try finding an invalid entry
|
1401 |
for (i = 0; i < 64; i++) { |
1402 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) { |
1403 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
1404 |
env->dtlb_tte[i] = val; |
1405 |
return;
|
1406 |
} |
1407 |
} |
1408 |
// Try finding an unlocked entry
|
1409 |
for (i = 0; i < 64; i++) { |
1410 |
if ((env->dtlb_tte[i] & 0x40) == 0) { |
1411 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
1412 |
env->dtlb_tte[i] = val; |
1413 |
return;
|
1414 |
} |
1415 |
} |
1416 |
// error state?
|
1417 |
return;
|
1418 |
} |
1419 |
case 0x5d: // D-MMU data access |
1420 |
{ |
1421 |
unsigned int i = (addr >> 3) & 0x3f; |
1422 |
|
1423 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
1424 |
env->dtlb_tte[i] = val; |
1425 |
return;
|
1426 |
} |
1427 |
case 0x5f: // D-MMU demap |
1428 |
case 0x49: // Interrupt data receive |
1429 |
// XXX
|
1430 |
return;
|
1431 |
case 0x51: // I-MMU 8k TSB pointer, RO |
1432 |
case 0x52: // I-MMU 64k TSB pointer, RO |
1433 |
case 0x56: // I-MMU tag read, RO |
1434 |
case 0x59: // D-MMU 8k TSB pointer, RO |
1435 |
case 0x5a: // D-MMU 64k TSB pointer, RO |
1436 |
case 0x5b: // D-MMU data pointer, RO |
1437 |
case 0x5e: // D-MMU tag read, RO |
1438 |
case 0x48: // Interrupt dispatch, RO |
1439 |
case 0x7f: // Incoming interrupt vector, RO |
1440 |
case 0x82: // Primary no-fault, RO |
1441 |
case 0x83: // Secondary no-fault, RO |
1442 |
case 0x8a: // Primary no-fault LE, RO |
1443 |
case 0x8b: // Secondary no-fault LE, RO |
1444 |
default:
|
1445 |
do_unassigned_access(addr, 1, 0, 1); |
1446 |
return;
|
1447 |
} |
1448 |
} |
1449 |
#endif /* CONFIG_USER_ONLY */ |
1450 |
|
1451 |
void helper_ldf_asi(target_ulong addr, int asi, int size, int rd) |
1452 |
{ |
1453 |
unsigned int i; |
1454 |
target_ulong val; |
1455 |
|
1456 |
switch (asi) {
|
1457 |
case 0xf0: // Block load primary |
1458 |
case 0xf1: // Block load secondary |
1459 |
case 0xf8: // Block load primary LE |
1460 |
case 0xf9: // Block load secondary LE |
1461 |
if (rd & 7) { |
1462 |
raise_exception(TT_ILL_INSN); |
1463 |
return;
|
1464 |
} |
1465 |
if (addr & 0x3f) { |
1466 |
raise_exception(TT_UNALIGNED); |
1467 |
return;
|
1468 |
} |
1469 |
for (i = 0; i < 16; i++) { |
1470 |
*(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4, 0); |
1471 |
addr += 4;
|
1472 |
} |
1473 |
|
1474 |
return;
|
1475 |
default:
|
1476 |
break;
|
1477 |
} |
1478 |
|
1479 |
val = helper_ld_asi(addr, asi, size, 0);
|
1480 |
switch(size) {
|
1481 |
default:
|
1482 |
case 4: |
1483 |
*((uint32_t *)&FT0) = val; |
1484 |
break;
|
1485 |
case 8: |
1486 |
*((int64_t *)&DT0) = val; |
1487 |
break;
|
1488 |
#if defined(CONFIG_USER_ONLY)
|
1489 |
case 16: |
1490 |
// XXX
|
1491 |
break;
|
1492 |
#endif
|
1493 |
} |
1494 |
} |
1495 |
|
1496 |
void helper_stf_asi(target_ulong addr, int asi, int size, int rd) |
1497 |
{ |
1498 |
unsigned int i; |
1499 |
target_ulong val = 0;
|
1500 |
|
1501 |
switch (asi) {
|
1502 |
case 0xf0: // Block store primary |
1503 |
case 0xf1: // Block store secondary |
1504 |
case 0xf8: // Block store primary LE |
1505 |
case 0xf9: // Block store secondary LE |
1506 |
if (rd & 7) { |
1507 |
raise_exception(TT_ILL_INSN); |
1508 |
return;
|
1509 |
} |
1510 |
if (addr & 0x3f) { |
1511 |
raise_exception(TT_UNALIGNED); |
1512 |
return;
|
1513 |
} |
1514 |
for (i = 0; i < 16; i++) { |
1515 |
val = *(uint32_t *)&env->fpr[rd++]; |
1516 |
helper_st_asi(addr, val, asi & 0x8f, 4); |
1517 |
addr += 4;
|
1518 |
} |
1519 |
|
1520 |
return;
|
1521 |
default:
|
1522 |
break;
|
1523 |
} |
1524 |
|
1525 |
switch(size) {
|
1526 |
default:
|
1527 |
case 4: |
1528 |
val = *((uint32_t *)&FT0); |
1529 |
break;
|
1530 |
case 8: |
1531 |
val = *((int64_t *)&DT0); |
1532 |
break;
|
1533 |
#if defined(CONFIG_USER_ONLY)
|
1534 |
case 16: |
1535 |
// XXX
|
1536 |
break;
|
1537 |
#endif
|
1538 |
} |
1539 |
helper_st_asi(addr, val, asi, size); |
1540 |
} |
1541 |
|
1542 |
target_ulong helper_cas_asi(target_ulong addr, target_ulong val1, |
1543 |
target_ulong val2, uint32_t asi) |
1544 |
{ |
1545 |
target_ulong ret; |
1546 |
|
1547 |
val1 &= 0xffffffffUL;
|
1548 |
ret = helper_ld_asi(addr, asi, 4, 0); |
1549 |
ret &= 0xffffffffUL;
|
1550 |
if (val1 == ret)
|
1551 |
helper_st_asi(addr, val2 & 0xffffffffUL, asi, 4); |
1552 |
return ret;
|
1553 |
} |
1554 |
|
1555 |
target_ulong helper_casx_asi(target_ulong addr, target_ulong val1, |
1556 |
target_ulong val2, uint32_t asi) |
1557 |
{ |
1558 |
target_ulong ret; |
1559 |
|
1560 |
ret = helper_ld_asi(addr, asi, 8, 0); |
1561 |
if (val1 == ret)
|
1562 |
helper_st_asi(addr, val2, asi, 8);
|
1563 |
return ret;
|
1564 |
} |
1565 |
#endif /* TARGET_SPARC64 */ |
1566 |
|
1567 |
#ifndef TARGET_SPARC64
|
1568 |
void helper_rett(void) |
1569 |
{ |
1570 |
unsigned int cwp; |
1571 |
|
1572 |
if (env->psret == 1) |
1573 |
raise_exception(TT_ILL_INSN); |
1574 |
|
1575 |
env->psret = 1;
|
1576 |
cwp = (env->cwp + 1) & (NWINDOWS - 1); |
1577 |
if (env->wim & (1 << cwp)) { |
1578 |
raise_exception(TT_WIN_UNF); |
1579 |
} |
1580 |
set_cwp(cwp); |
1581 |
env->psrs = env->psrps; |
1582 |
} |
1583 |
#endif
|
1584 |
|
1585 |
uint64_t helper_pack64(target_ulong high, target_ulong low) |
1586 |
{ |
1587 |
return ((uint64_t)high << 32) | (uint64_t)(low & 0xffffffff); |
1588 |
} |
1589 |
|
1590 |
void helper_ldfsr(void) |
1591 |
{ |
1592 |
int rnd_mode;
|
1593 |
|
1594 |
PUT_FSR32(env, *((uint32_t *) &FT0)); |
1595 |
switch (env->fsr & FSR_RD_MASK) {
|
1596 |
case FSR_RD_NEAREST:
|
1597 |
rnd_mode = float_round_nearest_even; |
1598 |
break;
|
1599 |
default:
|
1600 |
case FSR_RD_ZERO:
|
1601 |
rnd_mode = float_round_to_zero; |
1602 |
break;
|
1603 |
case FSR_RD_POS:
|
1604 |
rnd_mode = float_round_up; |
1605 |
break;
|
1606 |
case FSR_RD_NEG:
|
1607 |
rnd_mode = float_round_down; |
1608 |
break;
|
1609 |
} |
1610 |
set_float_rounding_mode(rnd_mode, &env->fp_status); |
1611 |
} |
1612 |
|
1613 |
void helper_stfsr(void) |
1614 |
{ |
1615 |
*((uint32_t *) &FT0) = GET_FSR32(env); |
1616 |
} |
1617 |
|
1618 |
void helper_debug(void) |
1619 |
{ |
1620 |
env->exception_index = EXCP_DEBUG; |
1621 |
cpu_loop_exit(); |
1622 |
} |
1623 |
|
1624 |
#ifndef TARGET_SPARC64
|
1625 |
void helper_wrpsr(target_ulong new_psr)
|
1626 |
{ |
1627 |
if ((new_psr & PSR_CWP) >= NWINDOWS)
|
1628 |
raise_exception(TT_ILL_INSN); |
1629 |
else
|
1630 |
PUT_PSR(env, new_psr); |
1631 |
} |
1632 |
|
1633 |
target_ulong helper_rdpsr(void)
|
1634 |
{ |
1635 |
return GET_PSR(env);
|
1636 |
} |
1637 |
|
1638 |
#else
|
1639 |
target_ulong helper_rdccr(void)
|
1640 |
{ |
1641 |
return GET_CCR(env);
|
1642 |
} |
1643 |
|
1644 |
void helper_wrccr(target_ulong new_ccr)
|
1645 |
{ |
1646 |
PUT_CCR(env, new_ccr); |
1647 |
} |
1648 |
|
1649 |
// CWP handling is reversed in V9, but we still use the V8 register
|
1650 |
// order.
|
1651 |
target_ulong helper_rdcwp(void)
|
1652 |
{ |
1653 |
return GET_CWP64(env);
|
1654 |
} |
1655 |
|
1656 |
void helper_wrcwp(target_ulong new_cwp)
|
1657 |
{ |
1658 |
PUT_CWP64(env, new_cwp); |
1659 |
} |
1660 |
|
1661 |
// This function uses non-native bit order
|
1662 |
#define GET_FIELD(X, FROM, TO) \
|
1663 |
((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1)) |
1664 |
|
1665 |
// This function uses the order in the manuals, i.e. bit 0 is 2^0
|
1666 |
#define GET_FIELD_SP(X, FROM, TO) \
|
1667 |
GET_FIELD(X, 63 - (TO), 63 - (FROM)) |
1668 |
|
1669 |
target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) |
1670 |
{ |
1671 |
return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) | |
1672 |
(GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) | |
1673 |
(GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) | |
1674 |
(GET_FIELD_SP(pixel_addr, 56, 59) << 13) | |
1675 |
(GET_FIELD_SP(pixel_addr, 35, 38) << 9) | |
1676 |
(GET_FIELD_SP(pixel_addr, 13, 16) << 5) | |
1677 |
(((pixel_addr >> 55) & 1) << 4) | |
1678 |
(GET_FIELD_SP(pixel_addr, 33, 34) << 2) | |
1679 |
GET_FIELD_SP(pixel_addr, 11, 12); |
1680 |
} |
1681 |
|
1682 |
target_ulong helper_alignaddr(target_ulong addr, target_ulong offset) |
1683 |
{ |
1684 |
uint64_t tmp; |
1685 |
|
1686 |
tmp = addr + offset; |
1687 |
env->gsr &= ~7ULL;
|
1688 |
env->gsr |= tmp & 7ULL;
|
1689 |
return tmp & ~7ULL; |
1690 |
} |
1691 |
|
1692 |
target_ulong helper_popc(target_ulong val) |
1693 |
{ |
1694 |
return ctpop64(val);
|
1695 |
} |
1696 |
|
1697 |
static inline uint64_t *get_gregset(uint64_t pstate) |
1698 |
{ |
1699 |
switch (pstate) {
|
1700 |
default:
|
1701 |
case 0: |
1702 |
return env->bgregs;
|
1703 |
case PS_AG:
|
1704 |
return env->agregs;
|
1705 |
case PS_MG:
|
1706 |
return env->mgregs;
|
1707 |
case PS_IG:
|
1708 |
return env->igregs;
|
1709 |
} |
1710 |
} |
1711 |
|
1712 |
static inline void change_pstate(uint64_t new_pstate) |
1713 |
{ |
1714 |
uint64_t pstate_regs, new_pstate_regs; |
1715 |
uint64_t *src, *dst; |
1716 |
|
1717 |
pstate_regs = env->pstate & 0xc01;
|
1718 |
new_pstate_regs = new_pstate & 0xc01;
|
1719 |
if (new_pstate_regs != pstate_regs) {
|
1720 |
// Switch global register bank
|
1721 |
src = get_gregset(new_pstate_regs); |
1722 |
dst = get_gregset(pstate_regs); |
1723 |
memcpy32(dst, env->gregs); |
1724 |
memcpy32(env->gregs, src); |
1725 |
} |
1726 |
env->pstate = new_pstate; |
1727 |
} |
1728 |
|
1729 |
void helper_wrpstate(target_ulong new_state)
|
1730 |
{ |
1731 |
change_pstate(new_state & 0xf3f);
|
1732 |
} |
1733 |
|
1734 |
void helper_done(void) |
1735 |
{ |
1736 |
env->tl--; |
1737 |
env->tsptr = &env->ts[env->tl]; |
1738 |
env->pc = env->tsptr->tpc; |
1739 |
env->npc = env->tsptr->tnpc + 4;
|
1740 |
PUT_CCR(env, env->tsptr->tstate >> 32);
|
1741 |
env->asi = (env->tsptr->tstate >> 24) & 0xff; |
1742 |
change_pstate((env->tsptr->tstate >> 8) & 0xf3f); |
1743 |
PUT_CWP64(env, env->tsptr->tstate & 0xff);
|
1744 |
} |
1745 |
|
1746 |
void helper_retry(void) |
1747 |
{ |
1748 |
env->tl--; |
1749 |
env->tsptr = &env->ts[env->tl]; |
1750 |
env->pc = env->tsptr->tpc; |
1751 |
env->npc = env->tsptr->tnpc; |
1752 |
PUT_CCR(env, env->tsptr->tstate >> 32);
|
1753 |
env->asi = (env->tsptr->tstate >> 24) & 0xff; |
1754 |
change_pstate((env->tsptr->tstate >> 8) & 0xf3f); |
1755 |
PUT_CWP64(env, env->tsptr->tstate & 0xff);
|
1756 |
} |
1757 |
#endif
|
1758 |
|
1759 |
void set_cwp(int new_cwp) |
1760 |
{ |
1761 |
/* put the modified wrap registers at their proper location */
|
1762 |
if (env->cwp == (NWINDOWS - 1)) |
1763 |
memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
|
1764 |
env->cwp = new_cwp; |
1765 |
/* put the wrap registers at their temporary location */
|
1766 |
if (new_cwp == (NWINDOWS - 1)) |
1767 |
memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
|
1768 |
env->regwptr = env->regbase + (new_cwp * 16);
|
1769 |
REGWPTR = env->regwptr; |
1770 |
} |
1771 |
|
1772 |
void cpu_set_cwp(CPUState *env1, int new_cwp) |
1773 |
{ |
1774 |
CPUState *saved_env; |
1775 |
#ifdef reg_REGWPTR
|
1776 |
target_ulong *saved_regwptr; |
1777 |
#endif
|
1778 |
|
1779 |
saved_env = env; |
1780 |
#ifdef reg_REGWPTR
|
1781 |
saved_regwptr = REGWPTR; |
1782 |
#endif
|
1783 |
env = env1; |
1784 |
set_cwp(new_cwp); |
1785 |
env = saved_env; |
1786 |
#ifdef reg_REGWPTR
|
1787 |
REGWPTR = saved_regwptr; |
1788 |
#endif
|
1789 |
} |
1790 |
|
1791 |
#ifdef TARGET_SPARC64
|
1792 |
#ifdef DEBUG_PCALL
|
1793 |
static const char * const excp_names[0x50] = { |
1794 |
[TT_TFAULT] = "Instruction Access Fault",
|
1795 |
[TT_TMISS] = "Instruction Access MMU Miss",
|
1796 |
[TT_CODE_ACCESS] = "Instruction Access Error",
|
1797 |
[TT_ILL_INSN] = "Illegal Instruction",
|
1798 |
[TT_PRIV_INSN] = "Privileged Instruction",
|
1799 |
[TT_NFPU_INSN] = "FPU Disabled",
|
1800 |
[TT_FP_EXCP] = "FPU Exception",
|
1801 |
[TT_TOVF] = "Tag Overflow",
|
1802 |
[TT_CLRWIN] = "Clean Windows",
|
1803 |
[TT_DIV_ZERO] = "Division By Zero",
|
1804 |
[TT_DFAULT] = "Data Access Fault",
|
1805 |
[TT_DMISS] = "Data Access MMU Miss",
|
1806 |
[TT_DATA_ACCESS] = "Data Access Error",
|
1807 |
[TT_DPROT] = "Data Protection Error",
|
1808 |
[TT_UNALIGNED] = "Unaligned Memory Access",
|
1809 |
[TT_PRIV_ACT] = "Privileged Action",
|
1810 |
[TT_EXTINT | 0x1] = "External Interrupt 1", |
1811 |
[TT_EXTINT | 0x2] = "External Interrupt 2", |
1812 |
[TT_EXTINT | 0x3] = "External Interrupt 3", |
1813 |
[TT_EXTINT | 0x4] = "External Interrupt 4", |
1814 |
[TT_EXTINT | 0x5] = "External Interrupt 5", |
1815 |
[TT_EXTINT | 0x6] = "External Interrupt 6", |
1816 |
[TT_EXTINT | 0x7] = "External Interrupt 7", |
1817 |
[TT_EXTINT | 0x8] = "External Interrupt 8", |
1818 |
[TT_EXTINT | 0x9] = "External Interrupt 9", |
1819 |
[TT_EXTINT | 0xa] = "External Interrupt 10", |
1820 |
[TT_EXTINT | 0xb] = "External Interrupt 11", |
1821 |
[TT_EXTINT | 0xc] = "External Interrupt 12", |
1822 |
[TT_EXTINT | 0xd] = "External Interrupt 13", |
1823 |
[TT_EXTINT | 0xe] = "External Interrupt 14", |
1824 |
[TT_EXTINT | 0xf] = "External Interrupt 15", |
1825 |
}; |
1826 |
#endif
|
1827 |
|
1828 |
void do_interrupt(int intno) |
1829 |
{ |
1830 |
#ifdef DEBUG_PCALL
|
1831 |
if (loglevel & CPU_LOG_INT) {
|
1832 |
static int count; |
1833 |
const char *name; |
1834 |
|
1835 |
if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80)) |
1836 |
name = "Unknown";
|
1837 |
else if (intno >= 0x100) |
1838 |
name = "Trap Instruction";
|
1839 |
else if (intno >= 0xc0) |
1840 |
name = "Window Fill";
|
1841 |
else if (intno >= 0x80) |
1842 |
name = "Window Spill";
|
1843 |
else {
|
1844 |
name = excp_names[intno]; |
1845 |
if (!name)
|
1846 |
name = "Unknown";
|
1847 |
} |
1848 |
|
1849 |
fprintf(logfile, "%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64 |
1850 |
" SP=%016" PRIx64 "\n", |
1851 |
count, name, intno, |
1852 |
env->pc, |
1853 |
env->npc, env->regwptr[6]);
|
1854 |
cpu_dump_state(env, logfile, fprintf, 0);
|
1855 |
#if 0
|
1856 |
{
|
1857 |
int i;
|
1858 |
uint8_t *ptr;
|
1859 |
|
1860 |
fprintf(logfile, " code=");
|
1861 |
ptr = (uint8_t *)env->pc;
|
1862 |
for(i = 0; i < 16; i++) {
|
1863 |
fprintf(logfile, " %02x", ldub(ptr + i));
|
1864 |
}
|
1865 |
fprintf(logfile, "\n");
|
1866 |
}
|
1867 |
#endif
|
1868 |
count++; |
1869 |
} |
1870 |
#endif
|
1871 |
#if !defined(CONFIG_USER_ONLY)
|
1872 |
if (env->tl == MAXTL) {
|
1873 |
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
|
1874 |
return;
|
1875 |
} |
1876 |
#endif
|
1877 |
env->tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
|
1878 |
((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | |
1879 |
GET_CWP64(env); |
1880 |
env->tsptr->tpc = env->pc; |
1881 |
env->tsptr->tnpc = env->npc; |
1882 |
env->tsptr->tt = intno; |
1883 |
change_pstate(PS_PEF | PS_PRIV | PS_AG); |
1884 |
|
1885 |
if (intno == TT_CLRWIN)
|
1886 |
set_cwp((env->cwp - 1) & (NWINDOWS - 1)); |
1887 |
else if ((intno & 0x1c0) == TT_SPILL) |
1888 |
set_cwp((env->cwp - env->cansave - 2) & (NWINDOWS - 1)); |
1889 |
else if ((intno & 0x1c0) == TT_FILL) |
1890 |
set_cwp((env->cwp + 1) & (NWINDOWS - 1)); |
1891 |
env->tbr &= ~0x7fffULL;
|
1892 |
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); |
1893 |
if (env->tl < MAXTL - 1) { |
1894 |
env->tl++; |
1895 |
} else {
|
1896 |
env->pstate |= PS_RED; |
1897 |
if (env->tl != MAXTL)
|
1898 |
env->tl++; |
1899 |
} |
1900 |
env->tsptr = &env->ts[env->tl]; |
1901 |
env->pc = env->tbr; |
1902 |
env->npc = env->pc + 4;
|
1903 |
env->exception_index = 0;
|
1904 |
} |
1905 |
#else
|
1906 |
#ifdef DEBUG_PCALL
|
1907 |
static const char * const excp_names[0x80] = { |
1908 |
[TT_TFAULT] = "Instruction Access Fault",
|
1909 |
[TT_ILL_INSN] = "Illegal Instruction",
|
1910 |
[TT_PRIV_INSN] = "Privileged Instruction",
|
1911 |
[TT_NFPU_INSN] = "FPU Disabled",
|
1912 |
[TT_WIN_OVF] = "Window Overflow",
|
1913 |
[TT_WIN_UNF] = "Window Underflow",
|
1914 |
[TT_UNALIGNED] = "Unaligned Memory Access",
|
1915 |
[TT_FP_EXCP] = "FPU Exception",
|
1916 |
[TT_DFAULT] = "Data Access Fault",
|
1917 |
[TT_TOVF] = "Tag Overflow",
|
1918 |
[TT_EXTINT | 0x1] = "External Interrupt 1", |
1919 |
[TT_EXTINT | 0x2] = "External Interrupt 2", |
1920 |
[TT_EXTINT | 0x3] = "External Interrupt 3", |
1921 |
[TT_EXTINT | 0x4] = "External Interrupt 4", |
1922 |
[TT_EXTINT | 0x5] = "External Interrupt 5", |
1923 |
[TT_EXTINT | 0x6] = "External Interrupt 6", |
1924 |
[TT_EXTINT | 0x7] = "External Interrupt 7", |
1925 |
[TT_EXTINT | 0x8] = "External Interrupt 8", |
1926 |
[TT_EXTINT | 0x9] = "External Interrupt 9", |
1927 |
[TT_EXTINT | 0xa] = "External Interrupt 10", |
1928 |
[TT_EXTINT | 0xb] = "External Interrupt 11", |
1929 |
[TT_EXTINT | 0xc] = "External Interrupt 12", |
1930 |
[TT_EXTINT | 0xd] = "External Interrupt 13", |
1931 |
[TT_EXTINT | 0xe] = "External Interrupt 14", |
1932 |
[TT_EXTINT | 0xf] = "External Interrupt 15", |
1933 |
[TT_TOVF] = "Tag Overflow",
|
1934 |
[TT_CODE_ACCESS] = "Instruction Access Error",
|
1935 |
[TT_DATA_ACCESS] = "Data Access Error",
|
1936 |
[TT_DIV_ZERO] = "Division By Zero",
|
1937 |
[TT_NCP_INSN] = "Coprocessor Disabled",
|
1938 |
}; |
1939 |
#endif
|
1940 |
|
1941 |
void do_interrupt(int intno) |
1942 |
{ |
1943 |
int cwp;
|
1944 |
|
1945 |
#ifdef DEBUG_PCALL
|
1946 |
if (loglevel & CPU_LOG_INT) {
|
1947 |
static int count; |
1948 |
const char *name; |
1949 |
|
1950 |
if (intno < 0 || intno >= 0x100) |
1951 |
name = "Unknown";
|
1952 |
else if (intno >= 0x80) |
1953 |
name = "Trap Instruction";
|
1954 |
else {
|
1955 |
name = excp_names[intno]; |
1956 |
if (!name)
|
1957 |
name = "Unknown";
|
1958 |
} |
1959 |
|
1960 |
fprintf(logfile, "%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
|
1961 |
count, name, intno, |
1962 |
env->pc, |
1963 |
env->npc, env->regwptr[6]);
|
1964 |
cpu_dump_state(env, logfile, fprintf, 0);
|
1965 |
#if 0
|
1966 |
{
|
1967 |
int i;
|
1968 |
uint8_t *ptr;
|
1969 |
|
1970 |
fprintf(logfile, " code=");
|
1971 |
ptr = (uint8_t *)env->pc;
|
1972 |
for(i = 0; i < 16; i++) {
|
1973 |
fprintf(logfile, " %02x", ldub(ptr + i));
|
1974 |
}
|
1975 |
fprintf(logfile, "\n");
|
1976 |
}
|
1977 |
#endif
|
1978 |
count++; |
1979 |
} |
1980 |
#endif
|
1981 |
#if !defined(CONFIG_USER_ONLY)
|
1982 |
if (env->psret == 0) { |
1983 |
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
|
1984 |
return;
|
1985 |
} |
1986 |
#endif
|
1987 |
env->psret = 0;
|
1988 |
cwp = (env->cwp - 1) & (NWINDOWS - 1); |
1989 |
set_cwp(cwp); |
1990 |
env->regwptr[9] = env->pc;
|
1991 |
env->regwptr[10] = env->npc;
|
1992 |
env->psrps = env->psrs; |
1993 |
env->psrs = 1;
|
1994 |
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
1995 |
env->pc = env->tbr; |
1996 |
env->npc = env->pc + 4;
|
1997 |
env->exception_index = 0;
|
1998 |
} |
1999 |
#endif
|
2000 |
|
2001 |
#if !defined(CONFIG_USER_ONLY)
|
2002 |
|
2003 |
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
2004 |
void *retaddr);
|
2005 |
|
2006 |
#define MMUSUFFIX _mmu
|
2007 |
#define ALIGNED_ONLY
|
2008 |
#ifdef __s390__
|
2009 |
# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL)) |
2010 |
#else
|
2011 |
# define GETPC() (__builtin_return_address(0)) |
2012 |
#endif
|
2013 |
|
2014 |
#define SHIFT 0 |
2015 |
#include "softmmu_template.h" |
2016 |
|
2017 |
#define SHIFT 1 |
2018 |
#include "softmmu_template.h" |
2019 |
|
2020 |
#define SHIFT 2 |
2021 |
#include "softmmu_template.h" |
2022 |
|
2023 |
#define SHIFT 3 |
2024 |
#include "softmmu_template.h" |
2025 |
|
2026 |
static void do_unaligned_access(target_ulong addr, int is_write, int is_user, |
2027 |
void *retaddr)
|
2028 |
{ |
2029 |
#ifdef DEBUG_UNALIGNED
|
2030 |
printf("Unaligned access to 0x%x from 0x%x\n", addr, env->pc);
|
2031 |
#endif
|
2032 |
raise_exception(TT_UNALIGNED); |
2033 |
} |
2034 |
|
2035 |
/* try to fill the TLB and return an exception if error. If retaddr is
|
2036 |
NULL, it means that the function was called in C code (i.e. not
|
2037 |
from generated code or from helper.c) */
|
2038 |
/* XXX: fix it to restore all registers */
|
2039 |
void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
2040 |
{ |
2041 |
TranslationBlock *tb; |
2042 |
int ret;
|
2043 |
unsigned long pc; |
2044 |
CPUState *saved_env; |
2045 |
|
2046 |
/* XXX: hack to restore env in all cases, even if not called from
|
2047 |
generated code */
|
2048 |
saved_env = env; |
2049 |
env = cpu_single_env; |
2050 |
|
2051 |
ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
|
2052 |
if (ret) {
|
2053 |
if (retaddr) {
|
2054 |
/* now we have a real cpu fault */
|
2055 |
pc = (unsigned long)retaddr; |
2056 |
tb = tb_find_pc(pc); |
2057 |
if (tb) {
|
2058 |
/* the PC is inside the translated code. It means that we have
|
2059 |
a virtual CPU fault */
|
2060 |
cpu_restore_state(tb, env, pc, (void *)T2);
|
2061 |
} |
2062 |
} |
2063 |
cpu_loop_exit(); |
2064 |
} |
2065 |
env = saved_env; |
2066 |
} |
2067 |
|
2068 |
#endif
|
2069 |
|
2070 |
#ifndef TARGET_SPARC64
|
2071 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
2072 |
int is_asi)
|
2073 |
{ |
2074 |
CPUState *saved_env; |
2075 |
|
2076 |
/* XXX: hack to restore env in all cases, even if not called from
|
2077 |
generated code */
|
2078 |
saved_env = env; |
2079 |
env = cpu_single_env; |
2080 |
#ifdef DEBUG_UNASSIGNED
|
2081 |
if (is_asi)
|
2082 |
printf("Unassigned mem %s access to " TARGET_FMT_plx " asi 0x%02x from " |
2083 |
TARGET_FMT_lx "\n",
|
2084 |
is_exec ? "exec" : is_write ? "write" : "read", addr, is_asi, |
2085 |
env->pc); |
2086 |
else
|
2087 |
printf("Unassigned mem %s access to " TARGET_FMT_plx " from " |
2088 |
TARGET_FMT_lx "\n",
|
2089 |
is_exec ? "exec" : is_write ? "write" : "read", addr, env->pc); |
2090 |
#endif
|
2091 |
if (env->mmuregs[3]) /* Fault status register */ |
2092 |
env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
2093 |
if (is_asi)
|
2094 |
env->mmuregs[3] |= 1 << 16; |
2095 |
if (env->psrs)
|
2096 |
env->mmuregs[3] |= 1 << 5; |
2097 |
if (is_exec)
|
2098 |
env->mmuregs[3] |= 1 << 6; |
2099 |
if (is_write)
|
2100 |
env->mmuregs[3] |= 1 << 7; |
2101 |
env->mmuregs[3] |= (5 << 2) | 2; |
2102 |
env->mmuregs[4] = addr; /* Fault address register */ |
2103 |
if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { |
2104 |
if (is_exec)
|
2105 |
raise_exception(TT_CODE_ACCESS); |
2106 |
else
|
2107 |
raise_exception(TT_DATA_ACCESS); |
2108 |
} |
2109 |
env = saved_env; |
2110 |
} |
2111 |
#else
|
2112 |
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
2113 |
int is_asi)
|
2114 |
{ |
2115 |
#ifdef DEBUG_UNASSIGNED
|
2116 |
CPUState *saved_env; |
2117 |
|
2118 |
/* XXX: hack to restore env in all cases, even if not called from
|
2119 |
generated code */
|
2120 |
saved_env = env; |
2121 |
env = cpu_single_env; |
2122 |
printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n", |
2123 |
addr, env->pc); |
2124 |
env = saved_env; |
2125 |
#endif
|
2126 |
if (is_exec)
|
2127 |
raise_exception(TT_CODE_ACCESS); |
2128 |
else
|
2129 |
raise_exception(TT_DATA_ACCESS); |
2130 |
} |
2131 |
#endif
|
2132 |
|