Revision d362e757 target-i386/cpu.h
b/target-i386/cpu.h | ||
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482 | 482 |
#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0 |
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#define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1 |
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#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2 |
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#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_3 |
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enum { |
... | ... | |
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#define NB_MMU_MODES 2 |
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typedef enum TPRAccess { |
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TPR_ACCESS_READ, |
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TPR_ACCESS_WRITE, |
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} TPRAccess; |
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typedef struct CPUX86State { |
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/* standard registers */ |
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target_ulong regs[CPU_NB_REGS]; |
... | ... | |
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XMMReg ymmh_regs[CPU_NB_REGS]; |
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uint64_t xcr0; |
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TPRAccess tpr_access_type; |
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} CPUX86State; |
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CPUX86State *cpu_x86_init(const char *cpu_model); |
... | ... | |
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uint32_t cpu_cc_compute_all(CPUState *env1, int op); |
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void cpu_report_tpr_access(CPUState *env, TPRAccess access); |
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#endif /* CPU_I386_H */ |
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