Statistics
| Branch: | Revision:

root / hw / ds1225y.c @ d43ed9ec

History | View | Annotate | Download (3.9 kB)

1
/*
2
 * QEMU NVRAM emulation for DS1225Y chip
3
 *
4
 * Copyright (c) 2007-2008 Herv? Poussineau
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24

    
25
#include "hw.h"
26
#include "mips.h"
27
#include "trace.h"
28

    
29
typedef struct ds1225y_t
30
{
31
    uint32_t chip_size;
32
    QEMUFile *file;
33
    uint8_t *contents;
34
} ds1225y_t;
35

    
36

    
37
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
38
{
39
    ds1225y_t *s = opaque;
40
    uint32_t val;
41

    
42
    val = s->contents[addr];
43
    trace_nvram_read(addr, val);
44
    return val;
45
}
46

    
47
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
48
{
49
    uint32_t v;
50
    v = nvram_readb(opaque, addr);
51
    v |= nvram_readb(opaque, addr + 1) << 8;
52
    return v;
53
}
54

    
55
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
56
{
57
    uint32_t v;
58
    v = nvram_readb(opaque, addr);
59
    v |= nvram_readb(opaque, addr + 1) << 8;
60
    v |= nvram_readb(opaque, addr + 2) << 16;
61
    v |= nvram_readb(opaque, addr + 3) << 24;
62
    return v;
63
}
64

    
65
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
66
{
67
    ds1225y_t *s = opaque;
68

    
69
    val &= 0xff;
70
    trace_nvram_write(addr, s->contents[addr], val);
71

    
72
    s->contents[addr] = val;
73
    if (s->file) {
74
        qemu_fseek(s->file, addr, SEEK_SET);
75
        qemu_put_byte(s->file, (int)val);
76
        qemu_fflush(s->file);
77
    }
78
}
79

    
80
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
81
{
82
    nvram_writeb(opaque, addr, val & 0xff);
83
    nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
84
}
85

    
86
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
87
{
88
    nvram_writeb(opaque, addr, val & 0xff);
89
    nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
90
    nvram_writeb(opaque, addr + 2, (val >> 16) & 0xff);
91
    nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff);
92
}
93

    
94
static CPUReadMemoryFunc * const nvram_read[] = {
95
    &nvram_readb,
96
    &nvram_readw,
97
    &nvram_readl,
98
};
99

    
100
static CPUWriteMemoryFunc * const nvram_write[] = {
101
    &nvram_writeb,
102
    &nvram_writew,
103
    &nvram_writel,
104
};
105

    
106
/* Initialisation routine */
107
void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
108
{
109
    ds1225y_t *s;
110
    int mem_indexRW;
111
    QEMUFile *file;
112

    
113
    s = qemu_mallocz(sizeof(ds1225y_t));
114
    s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */
115
    s->contents = qemu_mallocz(s->chip_size);
116

    
117
    /* Read current file */
118
    file = qemu_fopen(filename, "rb");
119
    if (file) {
120
        /* Read nvram contents */
121
        qemu_get_buffer(file, s->contents, s->chip_size);
122
        qemu_fclose(file);
123
    }
124
    s->file = qemu_fopen(filename, "wb");
125
    if (s->file) {
126
        /* Write back contents, as 'wb' mode cleaned the file */
127
        qemu_put_buffer(s->file, s->contents, s->chip_size);
128
        qemu_fflush(s->file);
129
    }
130

    
131
    /* Read/write memory */
132
    mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s,
133
                                         DEVICE_NATIVE_ENDIAN);
134
    cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW);
135
    return s;
136
}