root / hw / ppce500_mpc8544ds.c @ d461e3b9
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1 | 1db09b84 | aurel32 | /*
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2 | 1db09b84 | aurel32 | * Qemu PowerPC MPC8544DS board emualtion
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3 | 1db09b84 | aurel32 | *
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4 | 1db09b84 | aurel32 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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5 | 1db09b84 | aurel32 | *
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6 | 1db09b84 | aurel32 | * Author: Yu Liu, <yu.liu@freescale.com>
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7 | 1db09b84 | aurel32 | *
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8 | 1db09b84 | aurel32 | * This file is derived from hw/ppc440_bamboo.c,
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9 | 1db09b84 | aurel32 | * the copyright for that material belongs to the original owners.
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10 | 1db09b84 | aurel32 | *
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11 | 1db09b84 | aurel32 | * This is free software; you can redistribute it and/or modify
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12 | 1db09b84 | aurel32 | * it under the terms of the GNU General Public License as published by
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13 | 1db09b84 | aurel32 | * the Free Software Foundation; either version 2 of the License, or
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14 | 1db09b84 | aurel32 | * (at your option) any later version.
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15 | 1db09b84 | aurel32 | */
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16 | 1db09b84 | aurel32 | |
17 | 1db09b84 | aurel32 | #include <dirent.h> |
18 | 1db09b84 | aurel32 | |
19 | 1db09b84 | aurel32 | #include "config.h" |
20 | 1db09b84 | aurel32 | #include "qemu-common.h" |
21 | 1db09b84 | aurel32 | #include "net.h" |
22 | 1db09b84 | aurel32 | #include "hw.h" |
23 | 1db09b84 | aurel32 | #include "pc.h" |
24 | 1db09b84 | aurel32 | #include "pci.h" |
25 | 1db09b84 | aurel32 | #include "boards.h" |
26 | 1db09b84 | aurel32 | #include "sysemu.h" |
27 | 1db09b84 | aurel32 | #include "kvm.h" |
28 | 1db09b84 | aurel32 | #include "kvm_ppc.h" |
29 | 1db09b84 | aurel32 | #include "device_tree.h" |
30 | 1db09b84 | aurel32 | #include "openpic.h" |
31 | 3b989d49 | Alexander Graf | #include "ppc.h" |
32 | ca20cf32 | Blue Swirl | #include "loader.h" |
33 | ca20cf32 | Blue Swirl | #include "elf.h" |
34 | be13cc7a | Alexander Graf | #include "sysbus.h" |
35 | 1db09b84 | aurel32 | |
36 | 1db09b84 | aurel32 | #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" |
37 | 1db09b84 | aurel32 | #define UIMAGE_LOAD_BASE 0 |
38 | 75bb6589 | Liu Yu | #define DTC_LOAD_PAD 0x500000 |
39 | 75bb6589 | Liu Yu | #define DTC_PAD_MASK 0xFFFFF |
40 | 75bb6589 | Liu Yu | #define INITRD_LOAD_PAD 0x2000000 |
41 | 75bb6589 | Liu Yu | #define INITRD_PAD_MASK 0xFFFFFF |
42 | 1db09b84 | aurel32 | |
43 | 1db09b84 | aurel32 | #define RAM_SIZES_ALIGN (64UL << 20) |
44 | 1db09b84 | aurel32 | |
45 | 1db09b84 | aurel32 | #define MPC8544_CCSRBAR_BASE 0xE0000000 |
46 | 1db09b84 | aurel32 | #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000) |
47 | 1db09b84 | aurel32 | #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500) |
48 | 1db09b84 | aurel32 | #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600) |
49 | 1db09b84 | aurel32 | #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000) |
50 | 1db09b84 | aurel32 | #define MPC8544_PCI_REGS_SIZE 0x1000 |
51 | 1db09b84 | aurel32 | #define MPC8544_PCI_IO 0xE1000000 |
52 | 1db09b84 | aurel32 | #define MPC8544_PCI_IOLEN 0x10000 |
53 | 1db09b84 | aurel32 | |
54 | 3b989d49 | Alexander Graf | struct boot_info
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55 | 3b989d49 | Alexander Graf | { |
56 | 3b989d49 | Alexander Graf | uint32_t dt_base; |
57 | 3b989d49 | Alexander Graf | uint32_t entry; |
58 | 3b989d49 | Alexander Graf | }; |
59 | 3b989d49 | Alexander Graf | |
60 | 3f0855b1 | Juan Quintela | #ifdef CONFIG_FDT
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61 | 1db09b84 | aurel32 | static int mpc8544_copy_soc_cell(void *fdt, const char *node, const char *prop) |
62 | 1db09b84 | aurel32 | { |
63 | 1db09b84 | aurel32 | uint32_t cell; |
64 | 1db09b84 | aurel32 | int ret;
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65 | 1db09b84 | aurel32 | |
66 | 1db09b84 | aurel32 | ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell));
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67 | 1db09b84 | aurel32 | if (ret < 0) { |
68 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't read host %s/%s\n", node, prop);
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69 | 1db09b84 | aurel32 | goto out;
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70 | 1db09b84 | aurel32 | } |
71 | 1db09b84 | aurel32 | |
72 | 1db09b84 | aurel32 | ret = qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0",
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73 | 1db09b84 | aurel32 | prop, cell); |
74 | 1db09b84 | aurel32 | if (ret < 0) { |
75 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't set guest /cpus/PowerPC,8544@0/%s\n", prop);
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76 | 1db09b84 | aurel32 | goto out;
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77 | 1db09b84 | aurel32 | } |
78 | 1db09b84 | aurel32 | |
79 | 1db09b84 | aurel32 | out:
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80 | 1db09b84 | aurel32 | return ret;
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81 | 1db09b84 | aurel32 | } |
82 | 511d2b14 | blueswir1 | #endif
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83 | 1db09b84 | aurel32 | |
84 | 04088adb | Liu Yu | static int mpc8544_load_device_tree(target_phys_addr_t addr, |
85 | 1db09b84 | aurel32 | uint32_t ramsize, |
86 | c227f099 | Anthony Liguori | target_phys_addr_t initrd_base, |
87 | c227f099 | Anthony Liguori | target_phys_addr_t initrd_size, |
88 | 1db09b84 | aurel32 | const char *kernel_cmdline) |
89 | 1db09b84 | aurel32 | { |
90 | dbf916d8 | Aurelien Jarno | int ret = -1; |
91 | 3f0855b1 | Juan Quintela | #ifdef CONFIG_FDT
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92 | 3b989d49 | Alexander Graf | uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)};
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93 | 5cea8590 | Paul Brook | char *filename;
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94 | 7ec632b4 | pbrook | int fdt_size;
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95 | dbf916d8 | Aurelien Jarno | void *fdt;
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96 | 1db09b84 | aurel32 | |
97 | 5cea8590 | Paul Brook | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); |
98 | 5cea8590 | Paul Brook | if (!filename) {
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99 | 1db09b84 | aurel32 | goto out;
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100 | 5cea8590 | Paul Brook | } |
101 | 5cea8590 | Paul Brook | fdt = load_device_tree(filename, &fdt_size); |
102 | 5cea8590 | Paul Brook | qemu_free(filename); |
103 | 5cea8590 | Paul Brook | if (fdt == NULL) { |
104 | 5cea8590 | Paul Brook | goto out;
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105 | 5cea8590 | Paul Brook | } |
106 | 1db09b84 | aurel32 | |
107 | 1db09b84 | aurel32 | /* Manipulate device tree in memory. */
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108 | 1db09b84 | aurel32 | ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, |
109 | 1db09b84 | aurel32 | sizeof(mem_reg_property));
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110 | 1db09b84 | aurel32 | if (ret < 0) |
111 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't set /memory/reg\n");
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112 | 1db09b84 | aurel32 | |
113 | 3b989d49 | Alexander Graf | if (initrd_size) {
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114 | 3b989d49 | Alexander Graf | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", |
115 | 3b989d49 | Alexander Graf | initrd_base); |
116 | 3b989d49 | Alexander Graf | if (ret < 0) { |
117 | 3b989d49 | Alexander Graf | fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
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118 | 3b989d49 | Alexander Graf | } |
119 | 1db09b84 | aurel32 | |
120 | 3b989d49 | Alexander Graf | ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", |
121 | 3b989d49 | Alexander Graf | (initrd_base + initrd_size)); |
122 | 3b989d49 | Alexander Graf | if (ret < 0) { |
123 | 3b989d49 | Alexander Graf | fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
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124 | 3b989d49 | Alexander Graf | } |
125 | 3b989d49 | Alexander Graf | } |
126 | 1db09b84 | aurel32 | |
127 | 1db09b84 | aurel32 | ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", |
128 | 1db09b84 | aurel32 | kernel_cmdline); |
129 | 1db09b84 | aurel32 | if (ret < 0) |
130 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't set /chosen/bootargs\n");
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131 | 1db09b84 | aurel32 | |
132 | 1db09b84 | aurel32 | if (kvm_enabled()) {
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133 | 1db09b84 | aurel32 | struct dirent *dirp;
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134 | 1db09b84 | aurel32 | DIR *dp; |
135 | 1db09b84 | aurel32 | char buf[128]; |
136 | 1db09b84 | aurel32 | |
137 | 1db09b84 | aurel32 | if ((dp = opendir("/proc/device-tree/cpus/")) == NULL) { |
138 | 1db09b84 | aurel32 | printf("Can't open directory /proc/device-tree/cpus/\n");
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139 | 04088adb | Liu Yu | ret = -1;
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140 | 1db09b84 | aurel32 | goto out;
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141 | 1db09b84 | aurel32 | } |
142 | 1db09b84 | aurel32 | |
143 | 1db09b84 | aurel32 | buf[0] = '\0'; |
144 | 1db09b84 | aurel32 | while ((dirp = readdir(dp)) != NULL) { |
145 | 1db09b84 | aurel32 | if (strncmp(dirp->d_name, "PowerPC", 7) == 0) { |
146 | 1db09b84 | aurel32 | snprintf(buf, 128, "/cpus/%s", dirp->d_name); |
147 | 1db09b84 | aurel32 | break;
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148 | 1db09b84 | aurel32 | } |
149 | 1db09b84 | aurel32 | } |
150 | 1db09b84 | aurel32 | closedir(dp); |
151 | 1db09b84 | aurel32 | if (buf[0] == '\0') { |
152 | 1db09b84 | aurel32 | printf("Unknow host!\n");
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153 | 04088adb | Liu Yu | ret = -1;
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154 | 1db09b84 | aurel32 | goto out;
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155 | 1db09b84 | aurel32 | } |
156 | 1db09b84 | aurel32 | |
157 | 1db09b84 | aurel32 | mpc8544_copy_soc_cell(fdt, buf, "clock-frequency");
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158 | 1db09b84 | aurel32 | mpc8544_copy_soc_cell(fdt, buf, "timebase-frequency");
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159 | 3b989d49 | Alexander Graf | } else {
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160 | 3b989d49 | Alexander Graf | const uint32_t freq = 400000000; |
161 | 3b989d49 | Alexander Graf | |
162 | 3b989d49 | Alexander Graf | qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0",
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163 | 3b989d49 | Alexander Graf | "clock-frequency", freq);
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164 | 3b989d49 | Alexander Graf | qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0",
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165 | 3b989d49 | Alexander Graf | "timebase-frequency", freq);
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166 | 1db09b84 | aurel32 | } |
167 | 1db09b84 | aurel32 | |
168 | 04088adb | Liu Yu | ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); |
169 | 04088adb | Liu Yu | qemu_free(fdt); |
170 | 7ec632b4 | pbrook | |
171 | 1db09b84 | aurel32 | out:
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172 | 1db09b84 | aurel32 | #endif
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173 | 1db09b84 | aurel32 | |
174 | 04088adb | Liu Yu | return ret;
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175 | 1db09b84 | aurel32 | } |
176 | 1db09b84 | aurel32 | |
177 | 3b989d49 | Alexander Graf | /* Create -kernel TLB entries for BookE, linearly spanning 256MB. */
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178 | 3b989d49 | Alexander Graf | static void mmubooke_create_initial_mapping(CPUState *env, |
179 | 3b989d49 | Alexander Graf | target_ulong va, |
180 | 3b989d49 | Alexander Graf | target_phys_addr_t pa) |
181 | 3b989d49 | Alexander Graf | { |
182 | 5389055a | Alexander Graf | ppcemb_tlb_t *tlb = booke206_get_tlbe(env, 1, 0, 0); |
183 | 3b989d49 | Alexander Graf | |
184 | 3b989d49 | Alexander Graf | tlb->attr = 0;
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185 | 3b989d49 | Alexander Graf | tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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186 | 3b989d49 | Alexander Graf | tlb->size = 256 * 1024 * 1024; |
187 | 3b989d49 | Alexander Graf | tlb->EPN = va & TARGET_PAGE_MASK; |
188 | 3b989d49 | Alexander Graf | tlb->RPN = pa & TARGET_PAGE_MASK; |
189 | 3b989d49 | Alexander Graf | tlb->PID = 0;
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190 | 3b989d49 | Alexander Graf | } |
191 | 3b989d49 | Alexander Graf | |
192 | 3b989d49 | Alexander Graf | static void mpc8544ds_cpu_reset(void *opaque) |
193 | 3b989d49 | Alexander Graf | { |
194 | 3b989d49 | Alexander Graf | CPUState *env = opaque; |
195 | 3b989d49 | Alexander Graf | struct boot_info *bi = env->load_info;
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196 | 3b989d49 | Alexander Graf | |
197 | 3b989d49 | Alexander Graf | cpu_reset(env); |
198 | 3b989d49 | Alexander Graf | |
199 | 3b989d49 | Alexander Graf | /* Set initial guest state. */
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200 | 3b989d49 | Alexander Graf | env->gpr[1] = (16<<20) - 8; |
201 | 3b989d49 | Alexander Graf | env->gpr[3] = bi->dt_base;
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202 | 3b989d49 | Alexander Graf | env->nip = bi->entry; |
203 | 3b989d49 | Alexander Graf | mmubooke_create_initial_mapping(env, 0, 0); |
204 | 3b989d49 | Alexander Graf | } |
205 | 3b989d49 | Alexander Graf | |
206 | c227f099 | Anthony Liguori | static void mpc8544ds_init(ram_addr_t ram_size, |
207 | 1db09b84 | aurel32 | const char *boot_device, |
208 | 1db09b84 | aurel32 | const char *kernel_filename, |
209 | 1db09b84 | aurel32 | const char *kernel_cmdline, |
210 | 1db09b84 | aurel32 | const char *initrd_filename, |
211 | 1db09b84 | aurel32 | const char *cpu_model) |
212 | 1db09b84 | aurel32 | { |
213 | 1db09b84 | aurel32 | PCIBus *pci_bus; |
214 | 1db09b84 | aurel32 | CPUState *env; |
215 | 1db09b84 | aurel32 | uint64_t elf_entry; |
216 | 1db09b84 | aurel32 | uint64_t elf_lowaddr; |
217 | c227f099 | Anthony Liguori | target_phys_addr_t entry=0;
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218 | c227f099 | Anthony Liguori | target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE; |
219 | 1db09b84 | aurel32 | target_long kernel_size=0;
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220 | 75bb6589 | Liu Yu | target_ulong dt_base = 0;
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221 | 75bb6589 | Liu Yu | target_ulong initrd_base = 0;
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222 | 1db09b84 | aurel32 | target_long initrd_size=0;
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223 | 1db09b84 | aurel32 | int i=0; |
224 | 1db09b84 | aurel32 | unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; |
225 | be13cc7a | Alexander Graf | qemu_irq *irqs, *mpic; |
226 | be13cc7a | Alexander Graf | DeviceState *dev; |
227 | 3b989d49 | Alexander Graf | struct boot_info *boot_info;
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228 | 1db09b84 | aurel32 | |
229 | 1db09b84 | aurel32 | /* Setup CPU */
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230 | ef250db6 | Alexander Graf | if (cpu_model == NULL) { |
231 | ef250db6 | Alexander Graf | cpu_model = "e500v2_v30";
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232 | ef250db6 | Alexander Graf | } |
233 | ef250db6 | Alexander Graf | |
234 | ef250db6 | Alexander Graf | env = cpu_ppc_init(cpu_model); |
235 | 1db09b84 | aurel32 | if (!env) {
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236 | 1db09b84 | aurel32 | fprintf(stderr, "Unable to initialize CPU!\n");
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237 | 1db09b84 | aurel32 | exit(1);
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238 | 1db09b84 | aurel32 | } |
239 | 1db09b84 | aurel32 | |
240 | 3b989d49 | Alexander Graf | /* XXX register timer? */
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241 | 3b989d49 | Alexander Graf | ppc_emb_timers_init(env, 400000000, PPC_INTERRUPT_DECR);
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242 | 3b989d49 | Alexander Graf | ppc_dcr_init(env, NULL, NULL); |
243 | 3b989d49 | Alexander Graf | |
244 | 3b989d49 | Alexander Graf | /* Register reset handler */
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245 | 3b989d49 | Alexander Graf | qemu_register_reset(mpc8544ds_cpu_reset, env); |
246 | 3b989d49 | Alexander Graf | |
247 | 1db09b84 | aurel32 | /* Fixup Memory size on a alignment boundary */
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248 | 1db09b84 | aurel32 | ram_size &= ~(RAM_SIZES_ALIGN - 1);
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249 | 1db09b84 | aurel32 | |
250 | 1db09b84 | aurel32 | /* Register Memory */
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251 | 1724f049 | Alex Williamson | cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(NULL, |
252 | 1724f049 | Alex Williamson | "mpc8544ds.ram", ram_size));
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253 | 1db09b84 | aurel32 | |
254 | 1db09b84 | aurel32 | /* MPIC */
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255 | 1db09b84 | aurel32 | irqs = qemu_mallocz(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
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256 | 1db09b84 | aurel32 | irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT]; |
257 | 1db09b84 | aurel32 | irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT]; |
258 | 1db09b84 | aurel32 | mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL); |
259 | 1db09b84 | aurel32 | |
260 | 1db09b84 | aurel32 | /* Serial */
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261 | 2d48377a | Blue Swirl | if (serial_hds[0]) { |
262 | 49a2942d | Blue Swirl | serial_mm_init(MPC8544_SERIAL0_REGS_BASE, |
263 | 49a2942d | Blue Swirl | 0, mpic[12+26], 399193, |
264 | 49a2942d | Blue Swirl | serial_hds[0], 1, 1); |
265 | 2d48377a | Blue Swirl | } |
266 | 1db09b84 | aurel32 | |
267 | 2d48377a | Blue Swirl | if (serial_hds[1]) { |
268 | 49a2942d | Blue Swirl | serial_mm_init(MPC8544_SERIAL1_REGS_BASE, |
269 | 49a2942d | Blue Swirl | 0, mpic[12+26], 399193, |
270 | 49a2942d | Blue Swirl | serial_hds[0], 1, 1); |
271 | 2d48377a | Blue Swirl | } |
272 | 1db09b84 | aurel32 | |
273 | 1db09b84 | aurel32 | /* PCI */
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274 | be13cc7a | Alexander Graf | dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
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275 | be13cc7a | Alexander Graf | mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]], |
276 | be13cc7a | Alexander Graf | mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]], |
277 | be13cc7a | Alexander Graf | NULL);
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278 | d461e3b9 | Alexander Graf | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
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279 | 1db09b84 | aurel32 | if (!pci_bus)
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280 | 1db09b84 | aurel32 | printf("couldn't create PCI controller!\n");
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281 | 1db09b84 | aurel32 | |
282 | 968d683c | Alexander Graf | isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); |
283 | 1db09b84 | aurel32 | |
284 | 1db09b84 | aurel32 | if (pci_bus) {
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285 | 1db09b84 | aurel32 | /* Register network interfaces. */
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286 | 1db09b84 | aurel32 | for (i = 0; i < nb_nics; i++) { |
287 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "virtio", NULL); |
288 | 1db09b84 | aurel32 | } |
289 | 1db09b84 | aurel32 | } |
290 | 1db09b84 | aurel32 | |
291 | 1db09b84 | aurel32 | /* Load kernel. */
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292 | 1db09b84 | aurel32 | if (kernel_filename) {
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293 | 1db09b84 | aurel32 | kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
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294 | 1db09b84 | aurel32 | if (kernel_size < 0) { |
295 | 409dbce5 | Aurelien Jarno | kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, |
296 | 409dbce5 | Aurelien Jarno | &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); |
297 | 1db09b84 | aurel32 | entry = elf_entry; |
298 | 1db09b84 | aurel32 | loadaddr = elf_lowaddr; |
299 | 1db09b84 | aurel32 | } |
300 | 1db09b84 | aurel32 | /* XXX try again as binary */
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301 | 1db09b84 | aurel32 | if (kernel_size < 0) { |
302 | 1db09b84 | aurel32 | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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303 | 1db09b84 | aurel32 | kernel_filename); |
304 | 1db09b84 | aurel32 | exit(1);
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305 | 1db09b84 | aurel32 | } |
306 | 1db09b84 | aurel32 | } |
307 | 1db09b84 | aurel32 | |
308 | 1db09b84 | aurel32 | /* Load initrd. */
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309 | 1db09b84 | aurel32 | if (initrd_filename) {
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310 | 75bb6589 | Liu Yu | initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; |
311 | d7585251 | pbrook | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
312 | d7585251 | pbrook | ram_size - initrd_base); |
313 | 1db09b84 | aurel32 | |
314 | 1db09b84 | aurel32 | if (initrd_size < 0) { |
315 | 1db09b84 | aurel32 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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316 | 1db09b84 | aurel32 | initrd_filename); |
317 | 1db09b84 | aurel32 | exit(1);
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318 | 1db09b84 | aurel32 | } |
319 | 1db09b84 | aurel32 | } |
320 | 1db09b84 | aurel32 | |
321 | 3b989d49 | Alexander Graf | boot_info = qemu_mallocz(sizeof(struct boot_info)); |
322 | 3b989d49 | Alexander Graf | |
323 | 1db09b84 | aurel32 | /* If we're loading a kernel directly, we must load the device tree too. */
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324 | 1db09b84 | aurel32 | if (kernel_filename) {
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325 | 3b989d49 | Alexander Graf | #ifndef CONFIG_FDT
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326 | 3b989d49 | Alexander Graf | cpu_abort(env, "Compiled without FDT support - can't load kernel\n");
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327 | 3b989d49 | Alexander Graf | #endif
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328 | 75bb6589 | Liu Yu | dt_base = (kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; |
329 | 04088adb | Liu Yu | if (mpc8544_load_device_tree(dt_base, ram_size,
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330 | 04088adb | Liu Yu | initrd_base, initrd_size, kernel_cmdline) < 0) {
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331 | 1db09b84 | aurel32 | fprintf(stderr, "couldn't load device tree\n");
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332 | 1db09b84 | aurel32 | exit(1);
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333 | 1db09b84 | aurel32 | } |
334 | 1db09b84 | aurel32 | |
335 | 3b989d49 | Alexander Graf | boot_info->entry = entry; |
336 | 3b989d49 | Alexander Graf | boot_info->dt_base = dt_base; |
337 | 1db09b84 | aurel32 | } |
338 | 3b989d49 | Alexander Graf | env->load_info = boot_info; |
339 | 1db09b84 | aurel32 | |
340 | 3b989d49 | Alexander Graf | if (kvm_enabled()) {
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341 | 1db09b84 | aurel32 | kvmppc_init(); |
342 | 3b989d49 | Alexander Graf | } |
343 | 1db09b84 | aurel32 | } |
344 | 1db09b84 | aurel32 | |
345 | f80f9ec9 | Anthony Liguori | static QEMUMachine mpc8544ds_machine = {
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346 | 1db09b84 | aurel32 | .name = "mpc8544ds",
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347 | 1db09b84 | aurel32 | .desc = "mpc8544ds",
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348 | 1db09b84 | aurel32 | .init = mpc8544ds_init, |
349 | 1db09b84 | aurel32 | }; |
350 | f80f9ec9 | Anthony Liguori | |
351 | f80f9ec9 | Anthony Liguori | static void mpc8544ds_machine_init(void) |
352 | f80f9ec9 | Anthony Liguori | { |
353 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&mpc8544ds_machine); |
354 | f80f9ec9 | Anthony Liguori | } |
355 | f80f9ec9 | Anthony Liguori | |
356 | f80f9ec9 | Anthony Liguori | machine_init(mpc8544ds_machine_init); |