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/*
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* QEMU USB OHCI Emulation
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* Copyright (c) 2004 Gianni Tedesco
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* Copyright (c) 2006 CodeSourcery
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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* TODO:
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* o Isochronous transfers
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* o Allocate bandwidth in frames properly
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* o Disable timers when nothing needs to be done, or remove timer usage
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* all together.
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* o Handle unrecoverable errors properly
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* o BIOS work to boot from USB storage
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "usb.h" |
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#include "pci.h" |
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#include "usb-ohci.h" |
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#include "sysbus.h" |
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#include "qdev-addr.h" |
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//#define DEBUG_OHCI
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/* Dump packet contents. */
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//#define DEBUG_PACKET
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//#define DEBUG_ISOCH
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/* This causes frames to occur 1000x slower */
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//#define OHCI_TIME_WARP 1
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#ifdef DEBUG_OHCI
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#define DPRINTF printf
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#else
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#define DPRINTF(...)
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#endif
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/* Number of Downstream Ports on the root hub. */
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#define OHCI_MAX_PORTS 15 |
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static int64_t usb_frame_time;
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static int64_t usb_bit_time;
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typedef struct OHCIPort { |
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USBPort port; |
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uint32_t ctrl; |
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} OHCIPort; |
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typedef struct { |
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USBBus bus; |
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qemu_irq irq; |
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int mem;
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int num_ports;
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const char *name; |
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QEMUTimer *eof_timer; |
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int64_t sof_time; |
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/* OHCI state */
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/* Control partition */
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uint32_t ctl, status; |
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uint32_t intr_status; |
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uint32_t intr; |
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/* memory pointer partition */
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uint32_t hcca; |
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uint32_t ctrl_head, ctrl_cur; |
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uint32_t bulk_head, bulk_cur; |
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uint32_t per_cur; |
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uint32_t done; |
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int done_count;
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/* Frame counter partition */
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uint32_t fsmps:15;
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uint32_t fit:1;
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uint32_t fi:14;
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uint32_t frt:1;
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uint16_t frame_number; |
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uint16_t padding; |
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uint32_t pstart; |
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uint32_t lst; |
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/* Root Hub partition */
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uint32_t rhdesc_a, rhdesc_b; |
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uint32_t rhstatus; |
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OHCIPort rhport[OHCI_MAX_PORTS]; |
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/* PXA27x Non-OHCI events */
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uint32_t hstatus; |
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uint32_t hmask; |
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uint32_t hreset; |
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uint32_t htest; |
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/* SM501 local memory offset */
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target_phys_addr_t localmem_base; |
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/* Active packets. */
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uint32_t old_ctl; |
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USBPacket usb_packet; |
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uint8_t usb_buf[8192];
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uint32_t async_td; |
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int async_complete;
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} OHCIState; |
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/* Host Controller Communications Area */
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struct ohci_hcca {
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uint32_t intr[32];
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uint16_t frame, pad; |
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uint32_t done; |
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}; |
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static void ohci_bus_stop(OHCIState *ohci); |
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/* Bitfields for the first word of an Endpoint Desciptor. */
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#define OHCI_ED_FA_SHIFT 0 |
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#define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) |
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#define OHCI_ED_EN_SHIFT 7 |
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#define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) |
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#define OHCI_ED_D_SHIFT 11 |
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#define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) |
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#define OHCI_ED_S (1<<13) |
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#define OHCI_ED_K (1<<14) |
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#define OHCI_ED_F (1<<15) |
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#define OHCI_ED_MPS_SHIFT 16 |
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#define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT) |
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/* Flags in the head field of an Endpoint Desciptor. */
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#define OHCI_ED_H 1 |
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#define OHCI_ED_C 2 |
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/* Bitfields for the first word of a Transfer Desciptor. */
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#define OHCI_TD_R (1<<18) |
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#define OHCI_TD_DP_SHIFT 19 |
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#define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) |
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#define OHCI_TD_DI_SHIFT 21 |
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#define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) |
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#define OHCI_TD_T0 (1<<24) |
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#define OHCI_TD_T1 (1<<24) |
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#define OHCI_TD_EC_SHIFT 26 |
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#define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) |
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#define OHCI_TD_CC_SHIFT 28 |
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#define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) |
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/* Bitfields for the first word of an Isochronous Transfer Desciptor. */
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/* CC & DI - same as in the General Transfer Desciptor */
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#define OHCI_TD_SF_SHIFT 0 |
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#define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT) |
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#define OHCI_TD_FC_SHIFT 24 |
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#define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT) |
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/* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
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#define OHCI_TD_PSW_CC_SHIFT 12 |
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#define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT) |
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#define OHCI_TD_PSW_SIZE_SHIFT 0 |
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#define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT) |
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#define OHCI_PAGE_MASK 0xfffff000 |
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#define OHCI_OFFSET_MASK 0xfff |
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#define OHCI_DPTR_MASK 0xfffffff0 |
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#define OHCI_BM(val, field) \
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(((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) |
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#define OHCI_SET_BM(val, field, newval) do { \ |
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val &= ~OHCI_##field##_MASK; \ |
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val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ |
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} while(0) |
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/* endpoint descriptor */
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struct ohci_ed {
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uint32_t flags; |
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uint32_t tail; |
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uint32_t head; |
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uint32_t next; |
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}; |
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/* General transfer descriptor */
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struct ohci_td {
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uint32_t flags; |
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uint32_t cbp; |
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uint32_t next; |
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uint32_t be; |
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}; |
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/* Isochronous transfer descriptor */
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struct ohci_iso_td {
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uint32_t flags; |
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uint32_t bp; |
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uint32_t next; |
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uint32_t be; |
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uint16_t offset[8];
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}; |
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#define USB_HZ 12000000 |
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/* OHCI Local stuff */
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#define OHCI_CTL_CBSR ((1<<0)|(1<<1)) |
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#define OHCI_CTL_PLE (1<<2) |
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#define OHCI_CTL_IE (1<<3) |
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#define OHCI_CTL_CLE (1<<4) |
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#define OHCI_CTL_BLE (1<<5) |
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#define OHCI_CTL_HCFS ((1<<6)|(1<<7)) |
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#define OHCI_USB_RESET 0x00 |
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#define OHCI_USB_RESUME 0x40 |
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#define OHCI_USB_OPERATIONAL 0x80 |
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#define OHCI_USB_SUSPEND 0xc0 |
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#define OHCI_CTL_IR (1<<8) |
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#define OHCI_CTL_RWC (1<<9) |
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#define OHCI_CTL_RWE (1<<10) |
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#define OHCI_STATUS_HCR (1<<0) |
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#define OHCI_STATUS_CLF (1<<1) |
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#define OHCI_STATUS_BLF (1<<2) |
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#define OHCI_STATUS_OCR (1<<3) |
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#define OHCI_STATUS_SOC ((1<<6)|(1<<7)) |
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#define OHCI_INTR_SO (1<<0) /* Scheduling overrun */ |
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#define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */ |
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#define OHCI_INTR_SF (1<<2) /* Start of frame */ |
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#define OHCI_INTR_RD (1<<3) /* Resume detect */ |
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#define OHCI_INTR_UE (1<<4) /* Unrecoverable error */ |
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#define OHCI_INTR_FNO (1<<5) /* Frame number overflow */ |
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#define OHCI_INTR_RHSC (1<<6) /* Root hub status change */ |
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#define OHCI_INTR_OC (1<<30) /* Ownership change */ |
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#define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */ |
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|
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#define OHCI_HCCA_SIZE 0x100 |
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#define OHCI_HCCA_MASK 0xffffff00 |
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#define OHCI_EDPTR_MASK 0xfffffff0 |
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#define OHCI_FMI_FI 0x00003fff |
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#define OHCI_FMI_FSMPS 0xffff0000 |
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#define OHCI_FMI_FIT 0x80000000 |
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#define OHCI_FR_RT (1<<31) |
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#define OHCI_LS_THRESH 0x628 |
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#define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ |
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#define OHCI_RHA_PSM (1<<8) |
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#define OHCI_RHA_NPS (1<<9) |
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#define OHCI_RHA_DT (1<<10) |
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#define OHCI_RHA_OCPM (1<<11) |
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#define OHCI_RHA_NOCP (1<<12) |
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#define OHCI_RHA_POTPGT_MASK 0xff000000 |
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|
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#define OHCI_RHS_LPS (1<<0) |
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#define OHCI_RHS_OCI (1<<1) |
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#define OHCI_RHS_DRWE (1<<15) |
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#define OHCI_RHS_LPSC (1<<16) |
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#define OHCI_RHS_OCIC (1<<17) |
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#define OHCI_RHS_CRWE (1<<31) |
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|
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#define OHCI_PORT_CCS (1<<0) |
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#define OHCI_PORT_PES (1<<1) |
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#define OHCI_PORT_PSS (1<<2) |
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#define OHCI_PORT_POCI (1<<3) |
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#define OHCI_PORT_PRS (1<<4) |
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#define OHCI_PORT_PPS (1<<8) |
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#define OHCI_PORT_LSDA (1<<9) |
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#define OHCI_PORT_CSC (1<<16) |
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#define OHCI_PORT_PESC (1<<17) |
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#define OHCI_PORT_PSSC (1<<18) |
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#define OHCI_PORT_OCIC (1<<19) |
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#define OHCI_PORT_PRSC (1<<20) |
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#define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
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|OHCI_PORT_OCIC|OHCI_PORT_PRSC) |
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#define OHCI_TD_DIR_SETUP 0x0 |
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#define OHCI_TD_DIR_OUT 0x1 |
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#define OHCI_TD_DIR_IN 0x2 |
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#define OHCI_TD_DIR_RESERVED 0x3 |
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|
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#define OHCI_CC_NOERROR 0x0 |
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#define OHCI_CC_CRC 0x1 |
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#define OHCI_CC_BITSTUFFING 0x2 |
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#define OHCI_CC_DATATOGGLEMISMATCH 0x3 |
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#define OHCI_CC_STALL 0x4 |
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#define OHCI_CC_DEVICENOTRESPONDING 0x5 |
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#define OHCI_CC_PIDCHECKFAILURE 0x6 |
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#define OHCI_CC_UNDEXPETEDPID 0x7 |
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#define OHCI_CC_DATAOVERRUN 0x8 |
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#define OHCI_CC_DATAUNDERRUN 0x9 |
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#define OHCI_CC_BUFFEROVERRUN 0xc |
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#define OHCI_CC_BUFFERUNDERRUN 0xd |
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|
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#define OHCI_HRESET_FSBIR (1 << 0) |
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|
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/* Update IRQ levels */
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static inline void ohci_intr_update(OHCIState *ohci) |
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{ |
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int level = 0; |
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if ((ohci->intr & OHCI_INTR_MIE) &&
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(ohci->intr_status & ohci->intr)) |
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level = 1;
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qemu_set_irq(ohci->irq, level); |
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} |
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/* Set an interrupt */
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static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) |
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{ |
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ohci->intr_status |= intr; |
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ohci_intr_update(ohci); |
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} |
323 |
|
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/* Attach or detach a device on a root hub port. */
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static void ohci_attach(USBPort *port1) |
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{ |
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OHCIState *s = port1->opaque; |
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OHCIPort *port = &s->rhport[port1->index]; |
329 |
|
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/* set connect status */
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port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; |
332 |
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/* update speed */
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if (port->port.dev->speed == USB_SPEED_LOW) {
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port->ctrl |= OHCI_PORT_LSDA; |
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} else {
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port->ctrl &= ~OHCI_PORT_LSDA; |
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} |
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|
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/* notify of remote-wakeup */
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if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
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ohci_set_interrupt(s, OHCI_INTR_RD); |
343 |
} |
344 |
|
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DPRINTF("usb-ohci: Attached port %d\n", port1->index);
|
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} |
347 |
|
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static void ohci_detach(USBPort *port1) |
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{ |
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OHCIState *s = port1->opaque; |
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OHCIPort *port = &s->rhport[port1->index]; |
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uint32_t old_state = port->ctrl; |
353 |
|
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/* set connect status */
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if (port->ctrl & OHCI_PORT_CCS) {
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port->ctrl &= ~OHCI_PORT_CCS; |
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port->ctrl |= OHCI_PORT_CSC; |
358 |
} |
359 |
/* disable port */
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if (port->ctrl & OHCI_PORT_PES) {
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port->ctrl &= ~OHCI_PORT_PES; |
362 |
port->ctrl |= OHCI_PORT_PESC; |
363 |
} |
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DPRINTF("usb-ohci: Detached port %d\n", port1->index);
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|
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if (old_state != port->ctrl)
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ohci_set_interrupt(s, OHCI_INTR_RHSC); |
368 |
} |
369 |
|
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static void ohci_wakeup(USBPort *port1) |
371 |
{ |
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OHCIState *s = port1->opaque; |
373 |
OHCIPort *port = &s->rhport[port1->index]; |
374 |
uint32_t intr = 0;
|
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if (port->ctrl & OHCI_PORT_PSS) {
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DPRINTF("usb-ohci: port %d: wakeup\n", port1->index);
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port->ctrl |= OHCI_PORT_PSSC; |
378 |
port->ctrl &= ~OHCI_PORT_PSS; |
379 |
intr = OHCI_INTR_RHSC; |
380 |
} |
381 |
/* Note that the controller can be suspended even if this port is not */
|
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if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
|
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DPRINTF("usb-ohci: remote-wakeup: SUSPEND->RESUME\n");
|
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/* This is the one state transition the controller can do by itself */
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s->ctl &= ~OHCI_CTL_HCFS; |
386 |
s->ctl |= OHCI_USB_RESUME; |
387 |
/* In suspend mode only ResumeDetected is possible, not RHSC:
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* see the OHCI spec 5.1.2.3.
|
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*/
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intr = OHCI_INTR_RD; |
391 |
} |
392 |
ohci_set_interrupt(s, intr); |
393 |
} |
394 |
|
395 |
/* Reset the controller */
|
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static void ohci_reset(void *opaque) |
397 |
{ |
398 |
OHCIState *ohci = opaque; |
399 |
OHCIPort *port; |
400 |
int i;
|
401 |
|
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ohci_bus_stop(ohci); |
403 |
ohci->ctl = 0;
|
404 |
ohci->old_ctl = 0;
|
405 |
ohci->status = 0;
|
406 |
ohci->intr_status = 0;
|
407 |
ohci->intr = OHCI_INTR_MIE; |
408 |
|
409 |
ohci->hcca = 0;
|
410 |
ohci->ctrl_head = ohci->ctrl_cur = 0;
|
411 |
ohci->bulk_head = ohci->bulk_cur = 0;
|
412 |
ohci->per_cur = 0;
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413 |
ohci->done = 0;
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ohci->done_count = 7;
|
415 |
|
416 |
/* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
|
417 |
* I took the value linux sets ...
|
418 |
*/
|
419 |
ohci->fsmps = 0x2778;
|
420 |
ohci->fi = 0x2edf;
|
421 |
ohci->fit = 0;
|
422 |
ohci->frt = 0;
|
423 |
ohci->frame_number = 0;
|
424 |
ohci->pstart = 0;
|
425 |
ohci->lst = OHCI_LS_THRESH; |
426 |
|
427 |
ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; |
428 |
ohci->rhdesc_b = 0x0; /* Impl. specific */ |
429 |
ohci->rhstatus = 0;
|
430 |
|
431 |
for (i = 0; i < ohci->num_ports; i++) |
432 |
{ |
433 |
port = &ohci->rhport[i]; |
434 |
port->ctrl = 0;
|
435 |
if (port->port.dev) {
|
436 |
usb_attach(&port->port, port->port.dev); |
437 |
} |
438 |
} |
439 |
if (ohci->async_td) {
|
440 |
usb_cancel_packet(&ohci->usb_packet); |
441 |
ohci->async_td = 0;
|
442 |
} |
443 |
DPRINTF("usb-ohci: Reset %s\n", ohci->name);
|
444 |
} |
445 |
|
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/* Get an array of dwords from main memory */
|
447 |
static inline int get_dwords(OHCIState *ohci, |
448 |
uint32_t addr, uint32_t *buf, int num)
|
449 |
{ |
450 |
int i;
|
451 |
|
452 |
addr += ohci->localmem_base; |
453 |
|
454 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
455 |
cpu_physical_memory_read(addr, buf, sizeof(*buf));
|
456 |
*buf = le32_to_cpu(*buf); |
457 |
} |
458 |
|
459 |
return 1; |
460 |
} |
461 |
|
462 |
/* Put an array of dwords in to main memory */
|
463 |
static inline int put_dwords(OHCIState *ohci, |
464 |
uint32_t addr, uint32_t *buf, int num)
|
465 |
{ |
466 |
int i;
|
467 |
|
468 |
addr += ohci->localmem_base; |
469 |
|
470 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
471 |
uint32_t tmp = cpu_to_le32(*buf); |
472 |
cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
|
473 |
} |
474 |
|
475 |
return 1; |
476 |
} |
477 |
|
478 |
/* Get an array of words from main memory */
|
479 |
static inline int get_words(OHCIState *ohci, |
480 |
uint32_t addr, uint16_t *buf, int num)
|
481 |
{ |
482 |
int i;
|
483 |
|
484 |
addr += ohci->localmem_base; |
485 |
|
486 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
487 |
cpu_physical_memory_read(addr, buf, sizeof(*buf));
|
488 |
*buf = le16_to_cpu(*buf); |
489 |
} |
490 |
|
491 |
return 1; |
492 |
} |
493 |
|
494 |
/* Put an array of words in to main memory */
|
495 |
static inline int put_words(OHCIState *ohci, |
496 |
uint32_t addr, uint16_t *buf, int num)
|
497 |
{ |
498 |
int i;
|
499 |
|
500 |
addr += ohci->localmem_base; |
501 |
|
502 |
for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { |
503 |
uint16_t tmp = cpu_to_le16(*buf); |
504 |
cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
|
505 |
} |
506 |
|
507 |
return 1; |
508 |
} |
509 |
|
510 |
static inline int ohci_read_ed(OHCIState *ohci, |
511 |
uint32_t addr, struct ohci_ed *ed)
|
512 |
{ |
513 |
return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
514 |
} |
515 |
|
516 |
static inline int ohci_read_td(OHCIState *ohci, |
517 |
uint32_t addr, struct ohci_td *td)
|
518 |
{ |
519 |
return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); |
520 |
} |
521 |
|
522 |
static inline int ohci_read_iso_td(OHCIState *ohci, |
523 |
uint32_t addr, struct ohci_iso_td *td)
|
524 |
{ |
525 |
return (get_dwords(ohci, addr, (uint32_t *)td, 4) && |
526 |
get_words(ohci, addr + 16, td->offset, 8)); |
527 |
} |
528 |
|
529 |
static inline int ohci_read_hcca(OHCIState *ohci, |
530 |
uint32_t addr, struct ohci_hcca *hcca)
|
531 |
{ |
532 |
cpu_physical_memory_read(addr + ohci->localmem_base, hcca, sizeof(*hcca));
|
533 |
return 1; |
534 |
} |
535 |
|
536 |
static inline int ohci_put_ed(OHCIState *ohci, |
537 |
uint32_t addr, struct ohci_ed *ed)
|
538 |
{ |
539 |
return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); |
540 |
} |
541 |
|
542 |
static inline int ohci_put_td(OHCIState *ohci, |
543 |
uint32_t addr, struct ohci_td *td)
|
544 |
{ |
545 |
return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); |
546 |
} |
547 |
|
548 |
static inline int ohci_put_iso_td(OHCIState *ohci, |
549 |
uint32_t addr, struct ohci_iso_td *td)
|
550 |
{ |
551 |
return (put_dwords(ohci, addr, (uint32_t *)td, 4) && |
552 |
put_words(ohci, addr + 16, td->offset, 8)); |
553 |
} |
554 |
|
555 |
static inline int ohci_put_hcca(OHCIState *ohci, |
556 |
uint32_t addr, struct ohci_hcca *hcca)
|
557 |
{ |
558 |
cpu_physical_memory_write(addr + ohci->localmem_base, hcca, sizeof(*hcca));
|
559 |
return 1; |
560 |
} |
561 |
|
562 |
/* Read/Write the contents of a TD from/to main memory. */
|
563 |
static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td, |
564 |
uint8_t *buf, int len, int write) |
565 |
{ |
566 |
uint32_t ptr; |
567 |
uint32_t n; |
568 |
|
569 |
ptr = td->cbp; |
570 |
n = 0x1000 - (ptr & 0xfff); |
571 |
if (n > len)
|
572 |
n = len; |
573 |
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write); |
574 |
if (n == len)
|
575 |
return;
|
576 |
ptr = td->be & ~0xfffu;
|
577 |
buf += n; |
578 |
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write); |
579 |
} |
580 |
|
581 |
/* Read/Write the contents of an ISO TD from/to main memory. */
|
582 |
static void ohci_copy_iso_td(OHCIState *ohci, |
583 |
uint32_t start_addr, uint32_t end_addr, |
584 |
uint8_t *buf, int len, int write) |
585 |
{ |
586 |
uint32_t ptr; |
587 |
uint32_t n; |
588 |
|
589 |
ptr = start_addr; |
590 |
n = 0x1000 - (ptr & 0xfff); |
591 |
if (n > len)
|
592 |
n = len; |
593 |
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write); |
594 |
if (n == len)
|
595 |
return;
|
596 |
ptr = end_addr & ~0xfffu;
|
597 |
buf += n; |
598 |
cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write); |
599 |
} |
600 |
|
601 |
static void ohci_process_lists(OHCIState *ohci, int completion); |
602 |
|
603 |
static void ohci_async_complete_packet(USBPort *port, USBPacket *packet) |
604 |
{ |
605 |
OHCIState *ohci = container_of(packet, OHCIState, usb_packet); |
606 |
#ifdef DEBUG_PACKET
|
607 |
DPRINTF("Async packet complete\n");
|
608 |
#endif
|
609 |
ohci->async_complete = 1;
|
610 |
ohci_process_lists(ohci, 1);
|
611 |
} |
612 |
|
613 |
#define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
|
614 |
|
615 |
static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, |
616 |
int completion)
|
617 |
{ |
618 |
int dir;
|
619 |
size_t len = 0;
|
620 |
#ifdef DEBUG_ISOCH
|
621 |
const char *str = NULL; |
622 |
#endif
|
623 |
int pid;
|
624 |
int ret;
|
625 |
int i;
|
626 |
USBDevice *dev; |
627 |
struct ohci_iso_td iso_td;
|
628 |
uint32_t addr; |
629 |
uint16_t starting_frame; |
630 |
int16_t relative_frame_number; |
631 |
int frame_count;
|
632 |
uint32_t start_offset, next_offset, end_offset = 0;
|
633 |
uint32_t start_addr, end_addr; |
634 |
|
635 |
addr = ed->head & OHCI_DPTR_MASK; |
636 |
|
637 |
if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
|
638 |
printf("usb-ohci: ISO_TD read error at %x\n", addr);
|
639 |
return 0; |
640 |
} |
641 |
|
642 |
starting_frame = OHCI_BM(iso_td.flags, TD_SF); |
643 |
frame_count = OHCI_BM(iso_td.flags, TD_FC); |
644 |
relative_frame_number = USUB(ohci->frame_number, starting_frame); |
645 |
|
646 |
#ifdef DEBUG_ISOCH
|
647 |
printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
|
648 |
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
|
649 |
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
|
650 |
"0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
|
651 |
"frame_number 0x%.8x starting_frame 0x%.8x\n"
|
652 |
"frame_count 0x%.8x relative %d\n"
|
653 |
"di 0x%.8x cc 0x%.8x\n",
|
654 |
ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK, |
655 |
iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, |
656 |
iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3], |
657 |
iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7], |
658 |
ohci->frame_number, starting_frame, |
659 |
frame_count, relative_frame_number, |
660 |
OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC)); |
661 |
#endif
|
662 |
|
663 |
if (relative_frame_number < 0) { |
664 |
DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
|
665 |
return 1; |
666 |
} else if (relative_frame_number > frame_count) { |
667 |
/* ISO TD expired - retire the TD to the Done Queue and continue with
|
668 |
the next ISO TD of the same ED */
|
669 |
DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
|
670 |
frame_count); |
671 |
OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
672 |
ed->head &= ~OHCI_DPTR_MASK; |
673 |
ed->head |= (iso_td.next & OHCI_DPTR_MASK); |
674 |
iso_td.next = ohci->done; |
675 |
ohci->done = addr; |
676 |
i = OHCI_BM(iso_td.flags, TD_DI); |
677 |
if (i < ohci->done_count)
|
678 |
ohci->done_count = i; |
679 |
ohci_put_iso_td(ohci, addr, &iso_td); |
680 |
return 0; |
681 |
} |
682 |
|
683 |
dir = OHCI_BM(ed->flags, ED_D); |
684 |
switch (dir) {
|
685 |
case OHCI_TD_DIR_IN:
|
686 |
#ifdef DEBUG_ISOCH
|
687 |
str = "in";
|
688 |
#endif
|
689 |
pid = USB_TOKEN_IN; |
690 |
break;
|
691 |
case OHCI_TD_DIR_OUT:
|
692 |
#ifdef DEBUG_ISOCH
|
693 |
str = "out";
|
694 |
#endif
|
695 |
pid = USB_TOKEN_OUT; |
696 |
break;
|
697 |
case OHCI_TD_DIR_SETUP:
|
698 |
#ifdef DEBUG_ISOCH
|
699 |
str = "setup";
|
700 |
#endif
|
701 |
pid = USB_TOKEN_SETUP; |
702 |
break;
|
703 |
default:
|
704 |
printf("usb-ohci: Bad direction %d\n", dir);
|
705 |
return 1; |
706 |
} |
707 |
|
708 |
if (!iso_td.bp || !iso_td.be) {
|
709 |
printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
|
710 |
return 1; |
711 |
} |
712 |
|
713 |
start_offset = iso_td.offset[relative_frame_number]; |
714 |
next_offset = iso_td.offset[relative_frame_number + 1];
|
715 |
|
716 |
if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || |
717 |
((relative_frame_number < frame_count) && |
718 |
!(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
|
719 |
printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
|
720 |
start_offset, next_offset); |
721 |
return 1; |
722 |
} |
723 |
|
724 |
if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
|
725 |
printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
|
726 |
start_offset, next_offset); |
727 |
return 1; |
728 |
} |
729 |
|
730 |
if ((start_offset & 0x1000) == 0) { |
731 |
start_addr = (iso_td.bp & OHCI_PAGE_MASK) | |
732 |
(start_offset & OHCI_OFFSET_MASK); |
733 |
} else {
|
734 |
start_addr = (iso_td.be & OHCI_PAGE_MASK) | |
735 |
(start_offset & OHCI_OFFSET_MASK); |
736 |
} |
737 |
|
738 |
if (relative_frame_number < frame_count) {
|
739 |
end_offset = next_offset - 1;
|
740 |
if ((end_offset & 0x1000) == 0) { |
741 |
end_addr = (iso_td.bp & OHCI_PAGE_MASK) | |
742 |
(end_offset & OHCI_OFFSET_MASK); |
743 |
} else {
|
744 |
end_addr = (iso_td.be & OHCI_PAGE_MASK) | |
745 |
(end_offset & OHCI_OFFSET_MASK); |
746 |
} |
747 |
} else {
|
748 |
/* Last packet in the ISO TD */
|
749 |
end_addr = iso_td.be; |
750 |
} |
751 |
|
752 |
if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
|
753 |
len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
|
754 |
- (start_addr & OHCI_OFFSET_MASK); |
755 |
} else {
|
756 |
len = end_addr - start_addr + 1;
|
757 |
} |
758 |
|
759 |
if (len && dir != OHCI_TD_DIR_IN) {
|
760 |
ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
|
761 |
} |
762 |
|
763 |
if (completion) {
|
764 |
ret = ohci->usb_packet.len; |
765 |
} else {
|
766 |
ret = USB_RET_NODEV; |
767 |
for (i = 0; i < ohci->num_ports; i++) { |
768 |
dev = ohci->rhport[i].port.dev; |
769 |
if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) |
770 |
continue;
|
771 |
ohci->usb_packet.pid = pid; |
772 |
ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA); |
773 |
ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN); |
774 |
ohci->usb_packet.data = ohci->usb_buf; |
775 |
ohci->usb_packet.len = len; |
776 |
ret = usb_handle_packet(dev, &ohci->usb_packet); |
777 |
if (ret != USB_RET_NODEV)
|
778 |
break;
|
779 |
} |
780 |
|
781 |
if (ret == USB_RET_ASYNC) {
|
782 |
return 1; |
783 |
} |
784 |
} |
785 |
|
786 |
#ifdef DEBUG_ISOCH
|
787 |
printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
|
788 |
start_offset, end_offset, start_addr, end_addr, str, len, ret); |
789 |
#endif
|
790 |
|
791 |
/* Writeback */
|
792 |
if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) { |
793 |
/* IN transfer succeeded */
|
794 |
ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
|
795 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
796 |
OHCI_CC_NOERROR); |
797 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret); |
798 |
} else if (dir == OHCI_TD_DIR_OUT && ret == len) { |
799 |
/* OUT transfer succeeded */
|
800 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
801 |
OHCI_CC_NOERROR); |
802 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
|
803 |
} else {
|
804 |
if (ret > (ssize_t) len) {
|
805 |
printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
|
806 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
807 |
OHCI_CC_DATAOVERRUN); |
808 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, |
809 |
len); |
810 |
} else if (ret >= 0) { |
811 |
printf("usb-ohci: DataUnderrun %d\n", ret);
|
812 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
813 |
OHCI_CC_DATAUNDERRUN); |
814 |
} else {
|
815 |
switch (ret) {
|
816 |
case USB_RET_NODEV:
|
817 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
818 |
OHCI_CC_DEVICENOTRESPONDING); |
819 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, |
820 |
0);
|
821 |
break;
|
822 |
case USB_RET_NAK:
|
823 |
case USB_RET_STALL:
|
824 |
printf("usb-ohci: got NAK/STALL %d\n", ret);
|
825 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
826 |
OHCI_CC_STALL); |
827 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, |
828 |
0);
|
829 |
break;
|
830 |
default:
|
831 |
printf("usb-ohci: Bad device response %d\n", ret);
|
832 |
OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, |
833 |
OHCI_CC_UNDEXPETEDPID); |
834 |
break;
|
835 |
} |
836 |
} |
837 |
} |
838 |
|
839 |
if (relative_frame_number == frame_count) {
|
840 |
/* Last data packet of ISO TD - retire the TD to the Done Queue */
|
841 |
OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR); |
842 |
ed->head &= ~OHCI_DPTR_MASK; |
843 |
ed->head |= (iso_td.next & OHCI_DPTR_MASK); |
844 |
iso_td.next = ohci->done; |
845 |
ohci->done = addr; |
846 |
i = OHCI_BM(iso_td.flags, TD_DI); |
847 |
if (i < ohci->done_count)
|
848 |
ohci->done_count = i; |
849 |
} |
850 |
ohci_put_iso_td(ohci, addr, &iso_td); |
851 |
return 1; |
852 |
} |
853 |
|
854 |
/* Service a transport descriptor.
|
855 |
Returns nonzero to terminate processing of this endpoint. */
|
856 |
|
857 |
static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) |
858 |
{ |
859 |
int dir;
|
860 |
size_t len = 0;
|
861 |
#ifdef DEBUG_PACKET
|
862 |
const char *str = NULL; |
863 |
#endif
|
864 |
int pid;
|
865 |
int ret;
|
866 |
int i;
|
867 |
USBDevice *dev; |
868 |
struct ohci_td td;
|
869 |
uint32_t addr; |
870 |
int flag_r;
|
871 |
int completion;
|
872 |
|
873 |
addr = ed->head & OHCI_DPTR_MASK; |
874 |
/* See if this TD has already been submitted to the device. */
|
875 |
completion = (addr == ohci->async_td); |
876 |
if (completion && !ohci->async_complete) {
|
877 |
#ifdef DEBUG_PACKET
|
878 |
DPRINTF("Skipping async TD\n");
|
879 |
#endif
|
880 |
return 1; |
881 |
} |
882 |
if (!ohci_read_td(ohci, addr, &td)) {
|
883 |
fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
|
884 |
return 0; |
885 |
} |
886 |
|
887 |
dir = OHCI_BM(ed->flags, ED_D); |
888 |
switch (dir) {
|
889 |
case OHCI_TD_DIR_OUT:
|
890 |
case OHCI_TD_DIR_IN:
|
891 |
/* Same value. */
|
892 |
break;
|
893 |
default:
|
894 |
dir = OHCI_BM(td.flags, TD_DP); |
895 |
break;
|
896 |
} |
897 |
|
898 |
switch (dir) {
|
899 |
case OHCI_TD_DIR_IN:
|
900 |
#ifdef DEBUG_PACKET
|
901 |
str = "in";
|
902 |
#endif
|
903 |
pid = USB_TOKEN_IN; |
904 |
break;
|
905 |
case OHCI_TD_DIR_OUT:
|
906 |
#ifdef DEBUG_PACKET
|
907 |
str = "out";
|
908 |
#endif
|
909 |
pid = USB_TOKEN_OUT; |
910 |
break;
|
911 |
case OHCI_TD_DIR_SETUP:
|
912 |
#ifdef DEBUG_PACKET
|
913 |
str = "setup";
|
914 |
#endif
|
915 |
pid = USB_TOKEN_SETUP; |
916 |
break;
|
917 |
default:
|
918 |
fprintf(stderr, "usb-ohci: Bad direction\n");
|
919 |
return 1; |
920 |
} |
921 |
if (td.cbp && td.be) {
|
922 |
if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { |
923 |
len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); |
924 |
} else {
|
925 |
len = (td.be - td.cbp) + 1;
|
926 |
} |
927 |
|
928 |
if (len && dir != OHCI_TD_DIR_IN && !completion) {
|
929 |
ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0);
|
930 |
} |
931 |
} |
932 |
|
933 |
flag_r = (td.flags & OHCI_TD_R) != 0;
|
934 |
#ifdef DEBUG_PACKET
|
935 |
DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n", |
936 |
addr, (int64_t)len, str, flag_r, td.cbp, td.be); |
937 |
|
938 |
if (len > 0 && dir != OHCI_TD_DIR_IN) { |
939 |
DPRINTF(" data:");
|
940 |
for (i = 0; i < len; i++) |
941 |
printf(" %.2x", ohci->usb_buf[i]);
|
942 |
DPRINTF("\n");
|
943 |
} |
944 |
#endif
|
945 |
if (completion) {
|
946 |
ret = ohci->usb_packet.len; |
947 |
ohci->async_td = 0;
|
948 |
ohci->async_complete = 0;
|
949 |
} else {
|
950 |
ret = USB_RET_NODEV; |
951 |
for (i = 0; i < ohci->num_ports; i++) { |
952 |
dev = ohci->rhport[i].port.dev; |
953 |
if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) |
954 |
continue;
|
955 |
|
956 |
if (ohci->async_td) {
|
957 |
/* ??? The hardware should allow one active packet per
|
958 |
endpoint. We only allow one active packet per controller.
|
959 |
This should be sufficient as long as devices respond in a
|
960 |
timely manner.
|
961 |
*/
|
962 |
#ifdef DEBUG_PACKET
|
963 |
DPRINTF("Too many pending packets\n");
|
964 |
#endif
|
965 |
return 1; |
966 |
} |
967 |
ohci->usb_packet.pid = pid; |
968 |
ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA); |
969 |
ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN); |
970 |
ohci->usb_packet.data = ohci->usb_buf; |
971 |
ohci->usb_packet.len = len; |
972 |
ret = usb_handle_packet(dev, &ohci->usb_packet); |
973 |
if (ret != USB_RET_NODEV)
|
974 |
break;
|
975 |
} |
976 |
#ifdef DEBUG_PACKET
|
977 |
DPRINTF("ret=%d\n", ret);
|
978 |
#endif
|
979 |
if (ret == USB_RET_ASYNC) {
|
980 |
ohci->async_td = addr; |
981 |
return 1; |
982 |
} |
983 |
} |
984 |
if (ret >= 0) { |
985 |
if (dir == OHCI_TD_DIR_IN) {
|
986 |
ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
|
987 |
#ifdef DEBUG_PACKET
|
988 |
DPRINTF(" data:");
|
989 |
for (i = 0; i < ret; i++) |
990 |
printf(" %.2x", ohci->usb_buf[i]);
|
991 |
DPRINTF("\n");
|
992 |
#endif
|
993 |
} else {
|
994 |
ret = len; |
995 |
} |
996 |
} |
997 |
|
998 |
/* Writeback */
|
999 |
if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { |
1000 |
/* Transmission succeeded. */
|
1001 |
if (ret == len) {
|
1002 |
td.cbp = 0;
|
1003 |
} else {
|
1004 |
td.cbp += ret; |
1005 |
if ((td.cbp & 0xfff) + ret > 0xfff) { |
1006 |
td.cbp &= 0xfff;
|
1007 |
td.cbp |= td.be & ~0xfff;
|
1008 |
} |
1009 |
} |
1010 |
td.flags |= OHCI_TD_T1; |
1011 |
td.flags ^= OHCI_TD_T0; |
1012 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); |
1013 |
OHCI_SET_BM(td.flags, TD_EC, 0);
|
1014 |
|
1015 |
ed->head &= ~OHCI_ED_C; |
1016 |
if (td.flags & OHCI_TD_T0)
|
1017 |
ed->head |= OHCI_ED_C; |
1018 |
} else {
|
1019 |
if (ret >= 0) { |
1020 |
DPRINTF("usb-ohci: Underrun\n");
|
1021 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); |
1022 |
} else {
|
1023 |
switch (ret) {
|
1024 |
case USB_RET_NODEV:
|
1025 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); |
1026 |
case USB_RET_NAK:
|
1027 |
DPRINTF("usb-ohci: got NAK\n");
|
1028 |
return 1; |
1029 |
case USB_RET_STALL:
|
1030 |
DPRINTF("usb-ohci: got STALL\n");
|
1031 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); |
1032 |
break;
|
1033 |
case USB_RET_BABBLE:
|
1034 |
DPRINTF("usb-ohci: got BABBLE\n");
|
1035 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); |
1036 |
break;
|
1037 |
default:
|
1038 |
fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
|
1039 |
OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); |
1040 |
OHCI_SET_BM(td.flags, TD_EC, 3);
|
1041 |
break;
|
1042 |
} |
1043 |
} |
1044 |
ed->head |= OHCI_ED_H; |
1045 |
} |
1046 |
|
1047 |
/* Retire this TD */
|
1048 |
ed->head &= ~OHCI_DPTR_MASK; |
1049 |
ed->head |= td.next & OHCI_DPTR_MASK; |
1050 |
td.next = ohci->done; |
1051 |
ohci->done = addr; |
1052 |
i = OHCI_BM(td.flags, TD_DI); |
1053 |
if (i < ohci->done_count)
|
1054 |
ohci->done_count = i; |
1055 |
ohci_put_td(ohci, addr, &td); |
1056 |
return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
|
1057 |
} |
1058 |
|
1059 |
/* Service an endpoint list. Returns nonzero if active TD were found. */
|
1060 |
static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) |
1061 |
{ |
1062 |
struct ohci_ed ed;
|
1063 |
uint32_t next_ed; |
1064 |
uint32_t cur; |
1065 |
int active;
|
1066 |
|
1067 |
active = 0;
|
1068 |
|
1069 |
if (head == 0) |
1070 |
return 0; |
1071 |
|
1072 |
for (cur = head; cur; cur = next_ed) {
|
1073 |
if (!ohci_read_ed(ohci, cur, &ed)) {
|
1074 |
fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
|
1075 |
return 0; |
1076 |
} |
1077 |
|
1078 |
next_ed = ed.next & OHCI_DPTR_MASK; |
1079 |
|
1080 |
if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
|
1081 |
uint32_t addr; |
1082 |
/* Cancel pending packets for ED that have been paused. */
|
1083 |
addr = ed.head & OHCI_DPTR_MASK; |
1084 |
if (ohci->async_td && addr == ohci->async_td) {
|
1085 |
usb_cancel_packet(&ohci->usb_packet); |
1086 |
ohci->async_td = 0;
|
1087 |
} |
1088 |
continue;
|
1089 |
} |
1090 |
|
1091 |
while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
|
1092 |
#ifdef DEBUG_PACKET
|
1093 |
DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
|
1094 |
"h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
|
1095 |
OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), |
1096 |
OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
|
1097 |
(ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, |
1098 |
OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
|
1099 |
(ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
|
1100 |
ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); |
1101 |
#endif
|
1102 |
active = 1;
|
1103 |
|
1104 |
if ((ed.flags & OHCI_ED_F) == 0) { |
1105 |
if (ohci_service_td(ohci, &ed))
|
1106 |
break;
|
1107 |
} else {
|
1108 |
/* Handle isochronous endpoints */
|
1109 |
if (ohci_service_iso_td(ohci, &ed, completion))
|
1110 |
break;
|
1111 |
} |
1112 |
} |
1113 |
|
1114 |
ohci_put_ed(ohci, cur, &ed); |
1115 |
} |
1116 |
|
1117 |
return active;
|
1118 |
} |
1119 |
|
1120 |
/* Generate a SOF event, and set a timer for EOF */
|
1121 |
static void ohci_sof(OHCIState *ohci) |
1122 |
{ |
1123 |
ohci->sof_time = qemu_get_clock_ns(vm_clock); |
1124 |
qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time); |
1125 |
ohci_set_interrupt(ohci, OHCI_INTR_SF); |
1126 |
} |
1127 |
|
1128 |
/* Process Control and Bulk lists. */
|
1129 |
static void ohci_process_lists(OHCIState *ohci, int completion) |
1130 |
{ |
1131 |
if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
|
1132 |
if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
|
1133 |
DPRINTF("usb-ohci: head %x, cur %x\n",
|
1134 |
ohci->ctrl_head, ohci->ctrl_cur); |
1135 |
} |
1136 |
if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
|
1137 |
ohci->ctrl_cur = 0;
|
1138 |
ohci->status &= ~OHCI_STATUS_CLF; |
1139 |
} |
1140 |
} |
1141 |
|
1142 |
if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
|
1143 |
if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
|
1144 |
ohci->bulk_cur = 0;
|
1145 |
ohci->status &= ~OHCI_STATUS_BLF; |
1146 |
} |
1147 |
} |
1148 |
} |
1149 |
|
1150 |
/* Do frame processing on frame boundary */
|
1151 |
static void ohci_frame_boundary(void *opaque) |
1152 |
{ |
1153 |
OHCIState *ohci = opaque; |
1154 |
struct ohci_hcca hcca;
|
1155 |
|
1156 |
ohci_read_hcca(ohci, ohci->hcca, &hcca); |
1157 |
|
1158 |
/* Process all the lists at the end of the frame */
|
1159 |
if (ohci->ctl & OHCI_CTL_PLE) {
|
1160 |
int n;
|
1161 |
|
1162 |
n = ohci->frame_number & 0x1f;
|
1163 |
ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
|
1164 |
} |
1165 |
|
1166 |
/* Cancel all pending packets if either of the lists has been disabled. */
|
1167 |
if (ohci->async_td &&
|
1168 |
ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { |
1169 |
usb_cancel_packet(&ohci->usb_packet); |
1170 |
ohci->async_td = 0;
|
1171 |
} |
1172 |
ohci->old_ctl = ohci->ctl; |
1173 |
ohci_process_lists(ohci, 0);
|
1174 |
|
1175 |
/* Frame boundary, so do EOF stuf here */
|
1176 |
ohci->frt = ohci->fit; |
1177 |
|
1178 |
/* Increment frame number and take care of endianness. */
|
1179 |
ohci->frame_number = (ohci->frame_number + 1) & 0xffff; |
1180 |
hcca.frame = cpu_to_le16(ohci->frame_number); |
1181 |
|
1182 |
if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { |
1183 |
if (!ohci->done)
|
1184 |
abort(); |
1185 |
if (ohci->intr & ohci->intr_status)
|
1186 |
ohci->done |= 1;
|
1187 |
hcca.done = cpu_to_le32(ohci->done); |
1188 |
ohci->done = 0;
|
1189 |
ohci->done_count = 7;
|
1190 |
ohci_set_interrupt(ohci, OHCI_INTR_WD); |
1191 |
} |
1192 |
|
1193 |
if (ohci->done_count != 7 && ohci->done_count != 0) |
1194 |
ohci->done_count--; |
1195 |
|
1196 |
/* Do SOF stuff here */
|
1197 |
ohci_sof(ohci); |
1198 |
|
1199 |
/* Writeback HCCA */
|
1200 |
ohci_put_hcca(ohci, ohci->hcca, &hcca); |
1201 |
} |
1202 |
|
1203 |
/* Start sending SOF tokens across the USB bus, lists are processed in
|
1204 |
* next frame
|
1205 |
*/
|
1206 |
static int ohci_bus_start(OHCIState *ohci) |
1207 |
{ |
1208 |
ohci->eof_timer = qemu_new_timer_ns(vm_clock, |
1209 |
ohci_frame_boundary, |
1210 |
ohci); |
1211 |
|
1212 |
if (ohci->eof_timer == NULL) { |
1213 |
fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name);
|
1214 |
/* TODO: Signal unrecoverable error */
|
1215 |
return 0; |
1216 |
} |
1217 |
|
1218 |
DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
|
1219 |
|
1220 |
ohci_sof(ohci); |
1221 |
|
1222 |
return 1; |
1223 |
} |
1224 |
|
1225 |
/* Stop sending SOF tokens on the bus */
|
1226 |
static void ohci_bus_stop(OHCIState *ohci) |
1227 |
{ |
1228 |
if (ohci->eof_timer)
|
1229 |
qemu_del_timer(ohci->eof_timer); |
1230 |
ohci->eof_timer = NULL;
|
1231 |
} |
1232 |
|
1233 |
/* Sets a flag in a port status register but only set it if the port is
|
1234 |
* connected, if not set ConnectStatusChange flag. If flag is enabled
|
1235 |
* return 1.
|
1236 |
*/
|
1237 |
static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) |
1238 |
{ |
1239 |
int ret = 1; |
1240 |
|
1241 |
/* writing a 0 has no effect */
|
1242 |
if (val == 0) |
1243 |
return 0; |
1244 |
|
1245 |
/* If CurrentConnectStatus is cleared we set
|
1246 |
* ConnectStatusChange
|
1247 |
*/
|
1248 |
if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
|
1249 |
ohci->rhport[i].ctrl |= OHCI_PORT_CSC; |
1250 |
if (ohci->rhstatus & OHCI_RHS_DRWE) {
|
1251 |
/* TODO: CSC is a wakeup event */
|
1252 |
} |
1253 |
return 0; |
1254 |
} |
1255 |
|
1256 |
if (ohci->rhport[i].ctrl & val)
|
1257 |
ret = 0;
|
1258 |
|
1259 |
/* set the bit */
|
1260 |
ohci->rhport[i].ctrl |= val; |
1261 |
|
1262 |
return ret;
|
1263 |
} |
1264 |
|
1265 |
/* Set the frame interval - frame interval toggle is manipulated by the hcd only */
|
1266 |
static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) |
1267 |
{ |
1268 |
val &= OHCI_FMI_FI; |
1269 |
|
1270 |
if (val != ohci->fi) {
|
1271 |
DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
|
1272 |
ohci->name, ohci->fi, ohci->fi); |
1273 |
} |
1274 |
|
1275 |
ohci->fi = val; |
1276 |
} |
1277 |
|
1278 |
static void ohci_port_power(OHCIState *ohci, int i, int p) |
1279 |
{ |
1280 |
if (p) {
|
1281 |
ohci->rhport[i].ctrl |= OHCI_PORT_PPS; |
1282 |
} else {
|
1283 |
ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| |
1284 |
OHCI_PORT_CCS| |
1285 |
OHCI_PORT_PSS| |
1286 |
OHCI_PORT_PRS); |
1287 |
} |
1288 |
} |
1289 |
|
1290 |
/* Set HcControlRegister */
|
1291 |
static void ohci_set_ctl(OHCIState *ohci, uint32_t val) |
1292 |
{ |
1293 |
uint32_t old_state; |
1294 |
uint32_t new_state; |
1295 |
|
1296 |
old_state = ohci->ctl & OHCI_CTL_HCFS; |
1297 |
ohci->ctl = val; |
1298 |
new_state = ohci->ctl & OHCI_CTL_HCFS; |
1299 |
|
1300 |
/* no state change */
|
1301 |
if (old_state == new_state)
|
1302 |
return;
|
1303 |
|
1304 |
switch (new_state) {
|
1305 |
case OHCI_USB_OPERATIONAL:
|
1306 |
ohci_bus_start(ohci); |
1307 |
break;
|
1308 |
case OHCI_USB_SUSPEND:
|
1309 |
ohci_bus_stop(ohci); |
1310 |
DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
|
1311 |
break;
|
1312 |
case OHCI_USB_RESUME:
|
1313 |
DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
|
1314 |
break;
|
1315 |
case OHCI_USB_RESET:
|
1316 |
ohci_reset(ohci); |
1317 |
DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
|
1318 |
break;
|
1319 |
} |
1320 |
} |
1321 |
|
1322 |
static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
|
1323 |
{ |
1324 |
uint16_t fr; |
1325 |
int64_t tks; |
1326 |
|
1327 |
if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
|
1328 |
return (ohci->frt << 31); |
1329 |
|
1330 |
/* Being in USB operational state guarnatees sof_time was
|
1331 |
* set already.
|
1332 |
*/
|
1333 |
tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time; |
1334 |
|
1335 |
/* avoid muldiv if possible */
|
1336 |
if (tks >= usb_frame_time)
|
1337 |
return (ohci->frt << 31); |
1338 |
|
1339 |
tks = muldiv64(1, tks, usb_bit_time);
|
1340 |
fr = (uint16_t)(ohci->fi - tks); |
1341 |
|
1342 |
return (ohci->frt << 31) | fr; |
1343 |
} |
1344 |
|
1345 |
|
1346 |
/* Set root hub status */
|
1347 |
static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) |
1348 |
{ |
1349 |
uint32_t old_state; |
1350 |
|
1351 |
old_state = ohci->rhstatus; |
1352 |
|
1353 |
/* write 1 to clear OCIC */
|
1354 |
if (val & OHCI_RHS_OCIC)
|
1355 |
ohci->rhstatus &= ~OHCI_RHS_OCIC; |
1356 |
|
1357 |
if (val & OHCI_RHS_LPS) {
|
1358 |
int i;
|
1359 |
|
1360 |
for (i = 0; i < ohci->num_ports; i++) |
1361 |
ohci_port_power(ohci, i, 0);
|
1362 |
DPRINTF("usb-ohci: powered down all ports\n");
|
1363 |
} |
1364 |
|
1365 |
if (val & OHCI_RHS_LPSC) {
|
1366 |
int i;
|
1367 |
|
1368 |
for (i = 0; i < ohci->num_ports; i++) |
1369 |
ohci_port_power(ohci, i, 1);
|
1370 |
DPRINTF("usb-ohci: powered up all ports\n");
|
1371 |
} |
1372 |
|
1373 |
if (val & OHCI_RHS_DRWE)
|
1374 |
ohci->rhstatus |= OHCI_RHS_DRWE; |
1375 |
|
1376 |
if (val & OHCI_RHS_CRWE)
|
1377 |
ohci->rhstatus &= ~OHCI_RHS_DRWE; |
1378 |
|
1379 |
if (old_state != ohci->rhstatus)
|
1380 |
ohci_set_interrupt(ohci, OHCI_INTR_RHSC); |
1381 |
} |
1382 |
|
1383 |
/* Set root hub port status */
|
1384 |
static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) |
1385 |
{ |
1386 |
uint32_t old_state; |
1387 |
OHCIPort *port; |
1388 |
|
1389 |
port = &ohci->rhport[portnum]; |
1390 |
old_state = port->ctrl; |
1391 |
|
1392 |
/* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
|
1393 |
if (val & OHCI_PORT_WTC)
|
1394 |
port->ctrl &= ~(val & OHCI_PORT_WTC); |
1395 |
|
1396 |
if (val & OHCI_PORT_CCS)
|
1397 |
port->ctrl &= ~OHCI_PORT_PES; |
1398 |
|
1399 |
ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); |
1400 |
|
1401 |
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
|
1402 |
DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
|
1403 |
} |
1404 |
|
1405 |
if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
|
1406 |
DPRINTF("usb-ohci: port %d: RESET\n", portnum);
|
1407 |
usb_send_msg(port->port.dev, USB_MSG_RESET); |
1408 |
port->ctrl &= ~OHCI_PORT_PRS; |
1409 |
/* ??? Should this also set OHCI_PORT_PESC. */
|
1410 |
port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; |
1411 |
} |
1412 |
|
1413 |
/* Invert order here to ensure in ambiguous case, device is
|
1414 |
* powered up...
|
1415 |
*/
|
1416 |
if (val & OHCI_PORT_LSDA)
|
1417 |
ohci_port_power(ohci, portnum, 0);
|
1418 |
if (val & OHCI_PORT_PPS)
|
1419 |
ohci_port_power(ohci, portnum, 1);
|
1420 |
|
1421 |
if (old_state != port->ctrl)
|
1422 |
ohci_set_interrupt(ohci, OHCI_INTR_RHSC); |
1423 |
|
1424 |
return;
|
1425 |
} |
1426 |
|
1427 |
static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr) |
1428 |
{ |
1429 |
OHCIState *ohci = ptr; |
1430 |
uint32_t retval; |
1431 |
|
1432 |
addr &= 0xff;
|
1433 |
|
1434 |
/* Only aligned reads are allowed on OHCI */
|
1435 |
if (addr & 3) { |
1436 |
fprintf(stderr, "usb-ohci: Mis-aligned read\n");
|
1437 |
return 0xffffffff; |
1438 |
} else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
1439 |
/* HcRhPortStatus */
|
1440 |
retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; |
1441 |
} else {
|
1442 |
switch (addr >> 2) { |
1443 |
case 0: /* HcRevision */ |
1444 |
retval = 0x10;
|
1445 |
break;
|
1446 |
|
1447 |
case 1: /* HcControl */ |
1448 |
retval = ohci->ctl; |
1449 |
break;
|
1450 |
|
1451 |
case 2: /* HcCommandStatus */ |
1452 |
retval = ohci->status; |
1453 |
break;
|
1454 |
|
1455 |
case 3: /* HcInterruptStatus */ |
1456 |
retval = ohci->intr_status; |
1457 |
break;
|
1458 |
|
1459 |
case 4: /* HcInterruptEnable */ |
1460 |
case 5: /* HcInterruptDisable */ |
1461 |
retval = ohci->intr; |
1462 |
break;
|
1463 |
|
1464 |
case 6: /* HcHCCA */ |
1465 |
retval = ohci->hcca; |
1466 |
break;
|
1467 |
|
1468 |
case 7: /* HcPeriodCurrentED */ |
1469 |
retval = ohci->per_cur; |
1470 |
break;
|
1471 |
|
1472 |
case 8: /* HcControlHeadED */ |
1473 |
retval = ohci->ctrl_head; |
1474 |
break;
|
1475 |
|
1476 |
case 9: /* HcControlCurrentED */ |
1477 |
retval = ohci->ctrl_cur; |
1478 |
break;
|
1479 |
|
1480 |
case 10: /* HcBulkHeadED */ |
1481 |
retval = ohci->bulk_head; |
1482 |
break;
|
1483 |
|
1484 |
case 11: /* HcBulkCurrentED */ |
1485 |
retval = ohci->bulk_cur; |
1486 |
break;
|
1487 |
|
1488 |
case 12: /* HcDoneHead */ |
1489 |
retval = ohci->done; |
1490 |
break;
|
1491 |
|
1492 |
case 13: /* HcFmInterretval */ |
1493 |
retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); |
1494 |
break;
|
1495 |
|
1496 |
case 14: /* HcFmRemaining */ |
1497 |
retval = ohci_get_frame_remaining(ohci); |
1498 |
break;
|
1499 |
|
1500 |
case 15: /* HcFmNumber */ |
1501 |
retval = ohci->frame_number; |
1502 |
break;
|
1503 |
|
1504 |
case 16: /* HcPeriodicStart */ |
1505 |
retval = ohci->pstart; |
1506 |
break;
|
1507 |
|
1508 |
case 17: /* HcLSThreshold */ |
1509 |
retval = ohci->lst; |
1510 |
break;
|
1511 |
|
1512 |
case 18: /* HcRhDescriptorA */ |
1513 |
retval = ohci->rhdesc_a; |
1514 |
break;
|
1515 |
|
1516 |
case 19: /* HcRhDescriptorB */ |
1517 |
retval = ohci->rhdesc_b; |
1518 |
break;
|
1519 |
|
1520 |
case 20: /* HcRhStatus */ |
1521 |
retval = ohci->rhstatus; |
1522 |
break;
|
1523 |
|
1524 |
/* PXA27x specific registers */
|
1525 |
case 24: /* HcStatus */ |
1526 |
retval = ohci->hstatus & ohci->hmask; |
1527 |
break;
|
1528 |
|
1529 |
case 25: /* HcHReset */ |
1530 |
retval = ohci->hreset; |
1531 |
break;
|
1532 |
|
1533 |
case 26: /* HcHInterruptEnable */ |
1534 |
retval = ohci->hmask; |
1535 |
break;
|
1536 |
|
1537 |
case 27: /* HcHInterruptTest */ |
1538 |
retval = ohci->htest; |
1539 |
break;
|
1540 |
|
1541 |
default:
|
1542 |
fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr); |
1543 |
retval = 0xffffffff;
|
1544 |
} |
1545 |
} |
1546 |
|
1547 |
return retval;
|
1548 |
} |
1549 |
|
1550 |
static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val) |
1551 |
{ |
1552 |
OHCIState *ohci = ptr; |
1553 |
|
1554 |
addr &= 0xff;
|
1555 |
|
1556 |
/* Only aligned reads are allowed on OHCI */
|
1557 |
if (addr & 3) { |
1558 |
fprintf(stderr, "usb-ohci: Mis-aligned write\n");
|
1559 |
return;
|
1560 |
} |
1561 |
|
1562 |
if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { |
1563 |
/* HcRhPortStatus */
|
1564 |
ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); |
1565 |
return;
|
1566 |
} |
1567 |
|
1568 |
switch (addr >> 2) { |
1569 |
case 1: /* HcControl */ |
1570 |
ohci_set_ctl(ohci, val); |
1571 |
break;
|
1572 |
|
1573 |
case 2: /* HcCommandStatus */ |
1574 |
/* SOC is read-only */
|
1575 |
val = (val & ~OHCI_STATUS_SOC); |
1576 |
|
1577 |
/* Bits written as '0' remain unchanged in the register */
|
1578 |
ohci->status |= val; |
1579 |
|
1580 |
if (ohci->status & OHCI_STATUS_HCR)
|
1581 |
ohci_reset(ohci); |
1582 |
break;
|
1583 |
|
1584 |
case 3: /* HcInterruptStatus */ |
1585 |
ohci->intr_status &= ~val; |
1586 |
ohci_intr_update(ohci); |
1587 |
break;
|
1588 |
|
1589 |
case 4: /* HcInterruptEnable */ |
1590 |
ohci->intr |= val; |
1591 |
ohci_intr_update(ohci); |
1592 |
break;
|
1593 |
|
1594 |
case 5: /* HcInterruptDisable */ |
1595 |
ohci->intr &= ~val; |
1596 |
ohci_intr_update(ohci); |
1597 |
break;
|
1598 |
|
1599 |
case 6: /* HcHCCA */ |
1600 |
ohci->hcca = val & OHCI_HCCA_MASK; |
1601 |
break;
|
1602 |
|
1603 |
case 7: /* HcPeriodCurrentED */ |
1604 |
/* Ignore writes to this read-only register, Linux does them */
|
1605 |
break;
|
1606 |
|
1607 |
case 8: /* HcControlHeadED */ |
1608 |
ohci->ctrl_head = val & OHCI_EDPTR_MASK; |
1609 |
break;
|
1610 |
|
1611 |
case 9: /* HcControlCurrentED */ |
1612 |
ohci->ctrl_cur = val & OHCI_EDPTR_MASK; |
1613 |
break;
|
1614 |
|
1615 |
case 10: /* HcBulkHeadED */ |
1616 |
ohci->bulk_head = val & OHCI_EDPTR_MASK; |
1617 |
break;
|
1618 |
|
1619 |
case 11: /* HcBulkCurrentED */ |
1620 |
ohci->bulk_cur = val & OHCI_EDPTR_MASK; |
1621 |
break;
|
1622 |
|
1623 |
case 13: /* HcFmInterval */ |
1624 |
ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
|
1625 |
ohci->fit = (val & OHCI_FMI_FIT) >> 31;
|
1626 |
ohci_set_frame_interval(ohci, val); |
1627 |
break;
|
1628 |
|
1629 |
case 15: /* HcFmNumber */ |
1630 |
break;
|
1631 |
|
1632 |
case 16: /* HcPeriodicStart */ |
1633 |
ohci->pstart = val & 0xffff;
|
1634 |
break;
|
1635 |
|
1636 |
case 17: /* HcLSThreshold */ |
1637 |
ohci->lst = val & 0xffff;
|
1638 |
break;
|
1639 |
|
1640 |
case 18: /* HcRhDescriptorA */ |
1641 |
ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; |
1642 |
ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; |
1643 |
break;
|
1644 |
|
1645 |
case 19: /* HcRhDescriptorB */ |
1646 |
break;
|
1647 |
|
1648 |
case 20: /* HcRhStatus */ |
1649 |
ohci_set_hub_status(ohci, val); |
1650 |
break;
|
1651 |
|
1652 |
/* PXA27x specific registers */
|
1653 |
case 24: /* HcStatus */ |
1654 |
ohci->hstatus &= ~(val & ohci->hmask); |
1655 |
|
1656 |
case 25: /* HcHReset */ |
1657 |
ohci->hreset = val & ~OHCI_HRESET_FSBIR; |
1658 |
if (val & OHCI_HRESET_FSBIR)
|
1659 |
ohci_reset(ohci); |
1660 |
break;
|
1661 |
|
1662 |
case 26: /* HcHInterruptEnable */ |
1663 |
ohci->hmask = val; |
1664 |
break;
|
1665 |
|
1666 |
case 27: /* HcHInterruptTest */ |
1667 |
ohci->htest = val; |
1668 |
break;
|
1669 |
|
1670 |
default:
|
1671 |
fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr); |
1672 |
break;
|
1673 |
} |
1674 |
} |
1675 |
|
1676 |
static void ohci_device_destroy(USBBus *bus, USBDevice *dev) |
1677 |
{ |
1678 |
OHCIState *ohci = container_of(bus, OHCIState, bus); |
1679 |
|
1680 |
if (ohci->async_td && ohci->usb_packet.owner == dev) {
|
1681 |
usb_cancel_packet(&ohci->usb_packet); |
1682 |
ohci->async_td = 0;
|
1683 |
} |
1684 |
} |
1685 |
|
1686 |
/* Only dword reads are defined on OHCI register space */
|
1687 |
static CPUReadMemoryFunc * const ohci_readfn[3]={ |
1688 |
ohci_mem_read, |
1689 |
ohci_mem_read, |
1690 |
ohci_mem_read |
1691 |
}; |
1692 |
|
1693 |
/* Only dword writes are defined on OHCI register space */
|
1694 |
static CPUWriteMemoryFunc * const ohci_writefn[3]={ |
1695 |
ohci_mem_write, |
1696 |
ohci_mem_write, |
1697 |
ohci_mem_write |
1698 |
}; |
1699 |
|
1700 |
static USBPortOps ohci_port_ops = {
|
1701 |
.attach = ohci_attach, |
1702 |
.detach = ohci_detach, |
1703 |
.wakeup = ohci_wakeup, |
1704 |
.complete = ohci_async_complete_packet, |
1705 |
}; |
1706 |
|
1707 |
static USBBusOps ohci_bus_ops = {
|
1708 |
.device_destroy = ohci_device_destroy, |
1709 |
}; |
1710 |
|
1711 |
static void usb_ohci_init(OHCIState *ohci, DeviceState *dev, |
1712 |
int num_ports, uint32_t localmem_base)
|
1713 |
{ |
1714 |
int i;
|
1715 |
|
1716 |
if (usb_frame_time == 0) { |
1717 |
#ifdef OHCI_TIME_WARP
|
1718 |
usb_frame_time = get_ticks_per_sec(); |
1719 |
usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000); |
1720 |
#else
|
1721 |
usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000); |
1722 |
if (get_ticks_per_sec() >= USB_HZ) {
|
1723 |
usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
|
1724 |
} else {
|
1725 |
usb_bit_time = 1;
|
1726 |
} |
1727 |
#endif
|
1728 |
DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n", |
1729 |
usb_frame_time, usb_bit_time); |
1730 |
} |
1731 |
|
1732 |
ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci, |
1733 |
DEVICE_LITTLE_ENDIAN); |
1734 |
ohci->localmem_base = localmem_base; |
1735 |
|
1736 |
ohci->name = dev->info->name; |
1737 |
|
1738 |
usb_bus_new(&ohci->bus, &ohci_bus_ops, dev); |
1739 |
ohci->num_ports = num_ports; |
1740 |
for (i = 0; i < num_ports; i++) { |
1741 |
usb_register_port(&ohci->bus, &ohci->rhport[i].port, ohci, i, &ohci_port_ops, |
1742 |
USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); |
1743 |
} |
1744 |
|
1745 |
ohci->async_td = 0;
|
1746 |
qemu_register_reset(ohci_reset, ohci); |
1747 |
} |
1748 |
|
1749 |
typedef struct { |
1750 |
PCIDevice pci_dev; |
1751 |
OHCIState state; |
1752 |
} OHCIPCIState; |
1753 |
|
1754 |
static int usb_ohci_initfn_pci(struct PCIDevice *dev) |
1755 |
{ |
1756 |
OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev); |
1757 |
int num_ports = 3; |
1758 |
|
1759 |
ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */ |
1760 |
/* TODO: RST# value should be 0. */
|
1761 |
ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ |
1762 |
|
1763 |
usb_ohci_init(&ohci->state, &dev->qdev, num_ports, 0);
|
1764 |
ohci->state.irq = ohci->pci_dev.irq[0];
|
1765 |
|
1766 |
/* TODO: avoid cast below by using dev */
|
1767 |
pci_register_bar_simple(&ohci->pci_dev, 0, 256, 0, ohci->state.mem); |
1768 |
return 0; |
1769 |
} |
1770 |
|
1771 |
void usb_ohci_init_pci(struct PCIBus *bus, int devfn) |
1772 |
{ |
1773 |
pci_create_simple(bus, devfn, "pci-ohci");
|
1774 |
} |
1775 |
|
1776 |
typedef struct { |
1777 |
SysBusDevice busdev; |
1778 |
OHCIState ohci; |
1779 |
uint32_t num_ports; |
1780 |
target_phys_addr_t dma_offset; |
1781 |
} OHCISysBusState; |
1782 |
|
1783 |
static int ohci_init_pxa(SysBusDevice *dev) |
1784 |
{ |
1785 |
OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev); |
1786 |
|
1787 |
usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset); |
1788 |
sysbus_init_irq(dev, &s->ohci.irq); |
1789 |
sysbus_init_mmio(dev, 0x1000, s->ohci.mem);
|
1790 |
|
1791 |
return 0; |
1792 |
} |
1793 |
|
1794 |
static PCIDeviceInfo ohci_pci_info = {
|
1795 |
.qdev.name = "pci-ohci",
|
1796 |
.qdev.desc = "Apple USB Controller",
|
1797 |
.qdev.size = sizeof(OHCIPCIState),
|
1798 |
.init = usb_ohci_initfn_pci, |
1799 |
.vendor_id = PCI_VENDOR_ID_APPLE, |
1800 |
.device_id = PCI_DEVICE_ID_APPLE_IPID_USB, |
1801 |
.class_id = PCI_CLASS_SERIAL_USB, |
1802 |
}; |
1803 |
|
1804 |
static SysBusDeviceInfo ohci_sysbus_info = {
|
1805 |
.init = ohci_init_pxa, |
1806 |
.qdev.name = "sysbus-ohci",
|
1807 |
.qdev.desc = "OHCI USB Controller",
|
1808 |
.qdev.size = sizeof(OHCISysBusState),
|
1809 |
.qdev.props = (Property[]) { |
1810 |
DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), |
1811 |
DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3), |
1812 |
DEFINE_PROP_END_OF_LIST(), |
1813 |
} |
1814 |
}; |
1815 |
|
1816 |
static void ohci_register(void) |
1817 |
{ |
1818 |
pci_qdev_register(&ohci_pci_info); |
1819 |
sysbus_register_withprop(&ohci_sysbus_info); |
1820 |
} |
1821 |
device_init(ohci_register); |