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1
/*
2
 *  MIPS emulation helpers for qemu.
3
 *
4
 *  Copyright (c) 2004-2005 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18
 */
19
#include <stdarg.h>
20
#include <stdlib.h>
21
#include <stdio.h>
22
#include <string.h>
23
#include <inttypes.h>
24
#include <signal.h>
25

    
26
#include "cpu.h"
27
#include "exec-all.h"
28

    
29
enum {
30
    TLBRET_DIRTY = -4,
31
    TLBRET_INVALID = -3,
32
    TLBRET_NOMATCH = -2,
33
    TLBRET_BADADDR = -1,
34
    TLBRET_MATCH = 0
35
};
36

    
37
#if !defined(CONFIG_USER_ONLY)
38

    
39
/* no MMU emulation */
40
int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
41
                        target_ulong address, int rw, int access_type)
42
{
43
    *physical = address;
44
    *prot = PAGE_READ | PAGE_WRITE;
45
    return TLBRET_MATCH;
46
}
47

    
48
/* fixed mapping MMU emulation */
49
int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
50
                           target_ulong address, int rw, int access_type)
51
{
52
    if (address <= (int32_t)0x7FFFFFFFUL) {
53
        if (!(env->CP0_Status & (1 << CP0St_ERL)))
54
            *physical = address + 0x40000000UL;
55
        else
56
            *physical = address;
57
    } else if (address <= (int32_t)0xBFFFFFFFUL)
58
        *physical = address & 0x1FFFFFFF;
59
    else
60
        *physical = address;
61

    
62
    *prot = PAGE_READ | PAGE_WRITE;
63
    return TLBRET_MATCH;
64
}
65

    
66
/* MIPS32/MIPS64 R4000-style MMU emulation */
67
int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
68
                     target_ulong address, int rw, int access_type)
69
{
70
    uint8_t ASID = env->CP0_EntryHi & 0xFF;
71
    int i;
72

    
73
    for (i = 0; i < env->tlb->tlb_in_use; i++) {
74
        r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
75
        /* 1k pages are not supported. */
76
        target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
77
        target_ulong tag = address & ~mask;
78
        target_ulong VPN = tlb->VPN & ~mask;
79
#if defined(TARGET_MIPS64)
80
        tag &= env->SEGMask;
81
#endif
82

    
83
        /* Check ASID, virtual page number & size */
84
        if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
85
            /* TLB match */
86
            int n = !!(address & mask & ~(mask >> 1));
87
            /* Check access rights */
88
            if (!(n ? tlb->V1 : tlb->V0))
89
                return TLBRET_INVALID;
90
            if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
91
                *physical = tlb->PFN[n] | (address & (mask >> 1));
92
                *prot = PAGE_READ;
93
                if (n ? tlb->D1 : tlb->D0)
94
                    *prot |= PAGE_WRITE;
95
                return TLBRET_MATCH;
96
            }
97
            return TLBRET_DIRTY;
98
        }
99
    }
100
    return TLBRET_NOMATCH;
101
}
102

    
103
static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
104
                                int *prot, target_ulong address,
105
                                int rw, int access_type)
106
{
107
    /* User mode can only access useg/xuseg */
108
    int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
109
    int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
110
    int kernel_mode = !user_mode && !supervisor_mode;
111
#if defined(TARGET_MIPS64)
112
    int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
113
    int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
114
    int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
115
#endif
116
    int ret = TLBRET_MATCH;
117

    
118
#if 0
119
    qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
120
#endif
121

    
122
    if (address <= (int32_t)0x7FFFFFFFUL) {
123
        /* useg */
124
        if (env->CP0_Status & (1 << CP0St_ERL)) {
125
            *physical = address & 0xFFFFFFFF;
126
            *prot = PAGE_READ | PAGE_WRITE;
127
        } else {
128
            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
129
        }
130
#if defined(TARGET_MIPS64)
131
    } else if (address < 0x4000000000000000ULL) {
132
        /* xuseg */
133
        if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
134
            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
135
        } else {
136
            ret = TLBRET_BADADDR;
137
        }
138
    } else if (address < 0x8000000000000000ULL) {
139
        /* xsseg */
140
        if ((supervisor_mode || kernel_mode) &&
141
            SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
142
            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
143
        } else {
144
            ret = TLBRET_BADADDR;
145
        }
146
    } else if (address < 0xC000000000000000ULL) {
147
        /* xkphys */
148
        if (kernel_mode && KX &&
149
            (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
150
            *physical = address & env->PAMask;
151
            *prot = PAGE_READ | PAGE_WRITE;
152
        } else {
153
            ret = TLBRET_BADADDR;
154
        }
155
    } else if (address < 0xFFFFFFFF80000000ULL) {
156
        /* xkseg */
157
        if (kernel_mode && KX &&
158
            address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
159
            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
160
        } else {
161
            ret = TLBRET_BADADDR;
162
        }
163
#endif
164
    } else if (address < (int32_t)0xA0000000UL) {
165
        /* kseg0 */
166
        if (kernel_mode) {
167
            *physical = address - (int32_t)0x80000000UL;
168
            *prot = PAGE_READ | PAGE_WRITE;
169
        } else {
170
            ret = TLBRET_BADADDR;
171
        }
172
    } else if (address < (int32_t)0xC0000000UL) {
173
        /* kseg1 */
174
        if (kernel_mode) {
175
            *physical = address - (int32_t)0xA0000000UL;
176
            *prot = PAGE_READ | PAGE_WRITE;
177
        } else {
178
            ret = TLBRET_BADADDR;
179
        }
180
    } else if (address < (int32_t)0xE0000000UL) {
181
        /* sseg (kseg2) */
182
        if (supervisor_mode || kernel_mode) {
183
            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
184
        } else {
185
            ret = TLBRET_BADADDR;
186
        }
187
    } else {
188
        /* kseg3 */
189
        /* XXX: debug segment is not emulated */
190
        if (kernel_mode) {
191
            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
192
        } else {
193
            ret = TLBRET_BADADDR;
194
        }
195
    }
196
#if 0
197
    qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
198
            address, rw, access_type, *physical, *prot, ret);
199
#endif
200

    
201
    return ret;
202
}
203
#endif
204

    
205
static void raise_mmu_exception(CPUState *env, target_ulong address,
206
                                int rw, int tlb_error)
207
{
208
    int exception = 0, error_code = 0;
209

    
210
    switch (tlb_error) {
211
    default:
212
    case TLBRET_BADADDR:
213
        /* Reference to kernel address from user mode or supervisor mode */
214
        /* Reference to supervisor address from user mode */
215
        if (rw)
216
            exception = EXCP_AdES;
217
        else
218
            exception = EXCP_AdEL;
219
        break;
220
    case TLBRET_NOMATCH:
221
        /* No TLB match for a mapped address */
222
        if (rw)
223
            exception = EXCP_TLBS;
224
        else
225
            exception = EXCP_TLBL;
226
        error_code = 1;
227
        break;
228
    case TLBRET_INVALID:
229
        /* TLB match with no valid bit */
230
        if (rw)
231
            exception = EXCP_TLBS;
232
        else
233
            exception = EXCP_TLBL;
234
        break;
235
    case TLBRET_DIRTY:
236
        /* TLB match but 'D' bit is cleared */
237
        exception = EXCP_LTLBL;
238
        break;
239

    
240
    }
241
    /* Raise exception */
242
    env->CP0_BadVAddr = address;
243
    env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
244
                       ((address >> 9) & 0x007ffff0);
245
    env->CP0_EntryHi =
246
        (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
247
#if defined(TARGET_MIPS64)
248
    env->CP0_EntryHi &= env->SEGMask;
249
    env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
250
                        ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
251
                        ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
252
#endif
253
    env->exception_index = exception;
254
    env->error_code = error_code;
255
}
256

    
257
#if !defined(CONFIG_USER_ONLY)
258
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
259
{
260
    target_phys_addr_t phys_addr;
261
    int prot;
262

    
263
    if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
264
        return -1;
265
    return phys_addr;
266
}
267
#endif
268

    
269
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
270
                               int mmu_idx, int is_softmmu)
271
{
272
#if !defined(CONFIG_USER_ONLY)
273
    target_phys_addr_t physical;
274
    int prot;
275
#endif
276
    int access_type;
277
    int ret = 0;
278

    
279
#if 0
280
    log_cpu_state(env, 0);
281
#endif
282
    qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
283
              __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
284

    
285
    rw &= 1;
286

    
287
    /* data access */
288
    /* XXX: put correct access by using cpu_restore_state()
289
       correctly */
290
    access_type = ACCESS_INT;
291
#if defined(CONFIG_USER_ONLY)
292
    ret = TLBRET_NOMATCH;
293
#else
294
    ret = get_physical_address(env, &physical, &prot,
295
                               address, rw, access_type);
296
    qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n",
297
              __func__, address, ret, physical, prot);
298
    if (ret == TLBRET_MATCH) {
299
       tlb_set_page(env, address & TARGET_PAGE_MASK,
300
                    physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
301
                    mmu_idx, TARGET_PAGE_SIZE);
302
       ret = 0;
303
    } else if (ret < 0)
304
#endif
305
    {
306
        raise_mmu_exception(env, address, rw, ret);
307
        ret = 1;
308
    }
309

    
310
    return ret;
311
}
312

    
313
#if !defined(CONFIG_USER_ONLY)
314
target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
315
{
316
    target_phys_addr_t physical;
317
    int prot;
318
    int access_type;
319
    int ret = 0;
320

    
321
    rw &= 1;
322

    
323
    /* data access */
324
    access_type = ACCESS_INT;
325
    ret = get_physical_address(env, &physical, &prot,
326
                               address, rw, access_type);
327
    if (ret != TLBRET_MATCH) {
328
        raise_mmu_exception(env, address, rw, ret);
329
        return -1LL;
330
    } else {
331
        return physical;
332
    }
333
}
334
#endif
335

    
336
static const char * const excp_names[EXCP_LAST + 1] = {
337
    [EXCP_RESET] = "reset",
338
    [EXCP_SRESET] = "soft reset",
339
    [EXCP_DSS] = "debug single step",
340
    [EXCP_DINT] = "debug interrupt",
341
    [EXCP_NMI] = "non-maskable interrupt",
342
    [EXCP_MCHECK] = "machine check",
343
    [EXCP_EXT_INTERRUPT] = "interrupt",
344
    [EXCP_DFWATCH] = "deferred watchpoint",
345
    [EXCP_DIB] = "debug instruction breakpoint",
346
    [EXCP_IWATCH] = "instruction fetch watchpoint",
347
    [EXCP_AdEL] = "address error load",
348
    [EXCP_AdES] = "address error store",
349
    [EXCP_TLBF] = "TLB refill",
350
    [EXCP_IBE] = "instruction bus error",
351
    [EXCP_DBp] = "debug breakpoint",
352
    [EXCP_SYSCALL] = "syscall",
353
    [EXCP_BREAK] = "break",
354
    [EXCP_CpU] = "coprocessor unusable",
355
    [EXCP_RI] = "reserved instruction",
356
    [EXCP_OVERFLOW] = "arithmetic overflow",
357
    [EXCP_TRAP] = "trap",
358
    [EXCP_FPE] = "floating point",
359
    [EXCP_DDBS] = "debug data break store",
360
    [EXCP_DWATCH] = "data watchpoint",
361
    [EXCP_LTLBL] = "TLB modify",
362
    [EXCP_TLBL] = "TLB load",
363
    [EXCP_TLBS] = "TLB store",
364
    [EXCP_DBE] = "data bus error",
365
    [EXCP_DDBL] = "debug data break load",
366
    [EXCP_THREAD] = "thread",
367
    [EXCP_MDMX] = "MDMX",
368
    [EXCP_C2E] = "precise coprocessor 2",
369
    [EXCP_CACHE] = "cache error",
370
};
371

    
372
#if !defined(CONFIG_USER_ONLY)
373
static target_ulong exception_resume_pc (CPUState *env)
374
{
375
    target_ulong bad_pc;
376
    target_ulong isa_mode;
377

    
378
    isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
379
    bad_pc = env->active_tc.PC | isa_mode;
380
    if (env->hflags & MIPS_HFLAG_BMASK) {
381
        /* If the exception was raised from a delay slot, come back to
382
           the jump.  */
383
        bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
384
    }
385

    
386
    return bad_pc;
387
}
388
#endif
389

    
390
void do_interrupt (CPUState *env)
391
{
392
#if !defined(CONFIG_USER_ONLY)
393
    target_ulong offset;
394
    int cause = -1;
395
    const char *name;
396

    
397
    if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
398
        if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
399
            name = "unknown";
400
        else
401
            name = excp_names[env->exception_index];
402

    
403
        qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
404
                 __func__, env->active_tc.PC, env->CP0_EPC, name);
405
    }
406
    if (env->exception_index == EXCP_EXT_INTERRUPT &&
407
        (env->hflags & MIPS_HFLAG_DM))
408
        env->exception_index = EXCP_DINT;
409
    offset = 0x180;
410
    switch (env->exception_index) {
411
    case EXCP_DSS:
412
        env->CP0_Debug |= 1 << CP0DB_DSS;
413
        /* Debug single step cannot be raised inside a delay slot and
414
           resume will always occur on the next instruction
415
           (but we assume the pc has always been updated during
416
           code translation). */
417
        env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
418
        goto enter_debug_mode;
419
    case EXCP_DINT:
420
        env->CP0_Debug |= 1 << CP0DB_DINT;
421
        goto set_DEPC;
422
    case EXCP_DIB:
423
        env->CP0_Debug |= 1 << CP0DB_DIB;
424
        goto set_DEPC;
425
    case EXCP_DBp:
426
        env->CP0_Debug |= 1 << CP0DB_DBp;
427
        goto set_DEPC;
428
    case EXCP_DDBS:
429
        env->CP0_Debug |= 1 << CP0DB_DDBS;
430
        goto set_DEPC;
431
    case EXCP_DDBL:
432
        env->CP0_Debug |= 1 << CP0DB_DDBL;
433
    set_DEPC:
434
        env->CP0_DEPC = exception_resume_pc(env);
435
        env->hflags &= ~MIPS_HFLAG_BMASK;
436
 enter_debug_mode:
437
        env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
438
        env->hflags &= ~(MIPS_HFLAG_KSU);
439
        /* EJTAG probe trap enable is not implemented... */
440
        if (!(env->CP0_Status & (1 << CP0St_EXL)))
441
            env->CP0_Cause &= ~(1 << CP0Ca_BD);
442
        env->active_tc.PC = (int32_t)0xBFC00480;
443
        /* Exception handlers are entered in 32-bit mode.  */
444
        env->hflags &= ~(MIPS_HFLAG_M16);
445
        break;
446
    case EXCP_RESET:
447
        cpu_reset(env);
448
        break;
449
    case EXCP_SRESET:
450
        env->CP0_Status |= (1 << CP0St_SR);
451
        memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
452
        goto set_error_EPC;
453
    case EXCP_NMI:
454
        env->CP0_Status |= (1 << CP0St_NMI);
455
 set_error_EPC:
456
        env->CP0_ErrorEPC = exception_resume_pc(env);
457
        env->hflags &= ~MIPS_HFLAG_BMASK;
458
        env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
459
        env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
460
        env->hflags &= ~(MIPS_HFLAG_KSU);
461
        if (!(env->CP0_Status & (1 << CP0St_EXL)))
462
            env->CP0_Cause &= ~(1 << CP0Ca_BD);
463
        env->active_tc.PC = (int32_t)0xBFC00000;
464
        /* Exception handlers are entered in 32-bit mode.  */
465
        env->hflags &= ~(MIPS_HFLAG_M16);
466
        break;
467
    case EXCP_EXT_INTERRUPT:
468
        cause = 0;
469
        if (env->CP0_Cause & (1 << CP0Ca_IV))
470
            offset = 0x200;
471
        goto set_EPC;
472
    case EXCP_LTLBL:
473
        cause = 1;
474
        goto set_EPC;
475
    case EXCP_TLBL:
476
        cause = 2;
477
        if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
478
#if defined(TARGET_MIPS64)
479
            int R = env->CP0_BadVAddr >> 62;
480
            int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
481
            int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
482
            int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
483

    
484
            if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
485
                offset = 0x080;
486
            else
487
#endif
488
                offset = 0x000;
489
        }
490
        goto set_EPC;
491
    case EXCP_TLBS:
492
        cause = 3;
493
        if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
494
#if defined(TARGET_MIPS64)
495
            int R = env->CP0_BadVAddr >> 62;
496
            int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
497
            int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
498
            int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
499

    
500
            if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
501
                offset = 0x080;
502
            else
503
#endif
504
                offset = 0x000;
505
        }
506
        goto set_EPC;
507
    case EXCP_AdEL:
508
        cause = 4;
509
        goto set_EPC;
510
    case EXCP_AdES:
511
        cause = 5;
512
        goto set_EPC;
513
    case EXCP_IBE:
514
        cause = 6;
515
        goto set_EPC;
516
    case EXCP_DBE:
517
        cause = 7;
518
        goto set_EPC;
519
    case EXCP_SYSCALL:
520
        cause = 8;
521
        goto set_EPC;
522
    case EXCP_BREAK:
523
        cause = 9;
524
        goto set_EPC;
525
    case EXCP_RI:
526
        cause = 10;
527
        goto set_EPC;
528
    case EXCP_CpU:
529
        cause = 11;
530
        env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
531
                         (env->error_code << CP0Ca_CE);
532
        goto set_EPC;
533
    case EXCP_OVERFLOW:
534
        cause = 12;
535
        goto set_EPC;
536
    case EXCP_TRAP:
537
        cause = 13;
538
        goto set_EPC;
539
    case EXCP_FPE:
540
        cause = 15;
541
        goto set_EPC;
542
    case EXCP_C2E:
543
        cause = 18;
544
        goto set_EPC;
545
    case EXCP_MDMX:
546
        cause = 22;
547
        goto set_EPC;
548
    case EXCP_DWATCH:
549
        cause = 23;
550
        /* XXX: TODO: manage defered watch exceptions */
551
        goto set_EPC;
552
    case EXCP_MCHECK:
553
        cause = 24;
554
        goto set_EPC;
555
    case EXCP_THREAD:
556
        cause = 25;
557
        goto set_EPC;
558
    case EXCP_CACHE:
559
        cause = 30;
560
        if (env->CP0_Status & (1 << CP0St_BEV)) {
561
            offset = 0x100;
562
        } else {
563
            offset = 0x20000100;
564
        }
565
 set_EPC:
566
        if (!(env->CP0_Status & (1 << CP0St_EXL))) {
567
            env->CP0_EPC = exception_resume_pc(env);
568
            if (env->hflags & MIPS_HFLAG_BMASK) {
569
                env->CP0_Cause |= (1 << CP0Ca_BD);
570
            } else {
571
                env->CP0_Cause &= ~(1 << CP0Ca_BD);
572
            }
573
            env->CP0_Status |= (1 << CP0St_EXL);
574
            env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
575
            env->hflags &= ~(MIPS_HFLAG_KSU);
576
        }
577
        env->hflags &= ~MIPS_HFLAG_BMASK;
578
        if (env->CP0_Status & (1 << CP0St_BEV)) {
579
            env->active_tc.PC = (int32_t)0xBFC00200;
580
        } else {
581
            env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
582
        }
583
        env->active_tc.PC += offset;
584
        /* Exception handlers are entered in 32-bit mode.  */
585
        env->hflags &= ~(MIPS_HFLAG_M16);
586
        env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
587
        break;
588
    default:
589
        qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
590
        printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
591
        exit(1);
592
    }
593
    if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
594
        qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
595
                "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
596
                __func__, env->active_tc.PC, env->CP0_EPC, cause,
597
                env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
598
                env->CP0_DEPC);
599
    }
600
#endif
601
    env->exception_index = EXCP_NONE;
602
}
603

    
604
#if !defined(CONFIG_USER_ONLY)
605
void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
606
{
607
    r4k_tlb_t *tlb;
608
    target_ulong addr;
609
    target_ulong end;
610
    uint8_t ASID = env->CP0_EntryHi & 0xFF;
611
    target_ulong mask;
612

    
613
    tlb = &env->tlb->mmu.r4k.tlb[idx];
614
    /* The qemu TLB is flushed when the ASID changes, so no need to
615
       flush these entries again.  */
616
    if (tlb->G == 0 && tlb->ASID != ASID) {
617
        return;
618
    }
619

    
620
    if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
621
        /* For tlbwr, we can shadow the discarded entry into
622
           a new (fake) TLB entry, as long as the guest can not
623
           tell that it's there.  */
624
        env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
625
        env->tlb->tlb_in_use++;
626
        return;
627
    }
628

    
629
    /* 1k pages are not supported. */
630
    mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
631
    if (tlb->V0) {
632
        addr = tlb->VPN & ~mask;
633
#if defined(TARGET_MIPS64)
634
        if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
635
            addr |= 0x3FFFFF0000000000ULL;
636
        }
637
#endif
638
        end = addr | (mask >> 1);
639
        while (addr < end) {
640
            tlb_flush_page (env, addr);
641
            addr += TARGET_PAGE_SIZE;
642
        }
643
    }
644
    if (tlb->V1) {
645
        addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
646
#if defined(TARGET_MIPS64)
647
        if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
648
            addr |= 0x3FFFFF0000000000ULL;
649
        }
650
#endif
651
        end = addr | mask;
652
        while (addr - 1 < end) {
653
            tlb_flush_page (env, addr);
654
            addr += TARGET_PAGE_SIZE;
655
        }
656
    }
657
}
658
#endif