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Revision d532b26c

IDd532b26c9dee0fb5b2186572f921b1e413963ec2

Added by Igor V. Kovalenko almost 12 years ago

sparc64: interrupt trap handling

cpu_check_irqs
- handle SOFTINT register TICK and STICK timer bits
- only check interrupt levels greater than PIL value
- handle preemption by higher level traps

cpu_exec
- handle CPU_INTERRUPT_HARD only if interrupts are enabled
- PIL 15 is not special level on sparcv9

Signed-off-by: Igor V. Kovalenko <>
Signed-off-by: Blue Swirl <>

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