Revision d532b26c
| b/cpu-exec.c | ||
|---|---|---|
| 449 | 449 |
next_tb = 0; |
| 450 | 450 |
} |
| 451 | 451 |
#elif defined(TARGET_SPARC) |
| 452 |
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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cpu_interrupts_enabled(env)) {
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int pil = env->interrupt_index & 15;
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int type = env->interrupt_index & 0xf0;
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if (((type == TT_EXTINT) && |
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(pil == 15 || pil > env->psrpil)) ||
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type != TT_EXTINT) {
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env->interrupt_request &= ~CPU_INTERRUPT_HARD;
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env->exception_index = env->interrupt_index; |
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do_interrupt(env); |
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env->interrupt_index = 0;
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next_tb = 0;
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}
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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if (cpu_interrupts_enabled(env) &&
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env->interrupt_index > 0) {
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int pil = env->interrupt_index & 0xf;
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int type = env->interrupt_index & 0xf0; |
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if (((type == TT_EXTINT) &&
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cpu_pil_allowed(env, pil)) ||
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type != TT_EXTINT) {
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env->exception_index = env->interrupt_index;
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do_interrupt(env);
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next_tb = 0;
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}
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}
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| 466 | 466 |
} else if (interrupt_request & CPU_INTERRUPT_TIMER) {
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| 467 | 467 |
//do_interrupt(0, 0, 0, 0, 0); |
| 468 | 468 |
env->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
| b/hw/sun4u.c | ||
|---|---|---|
| 232 | 232 |
|
| 233 | 233 |
void cpu_check_irqs(CPUState *env) |
| 234 | 234 |
{
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uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) | |
|
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((env->softint & SOFTINT_TIMER) << 14); |
|
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uint32_t pil = env->pil_in | |
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(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); |
|
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|
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/* check if TM or SM in SOFTINT are set |
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setting these also causes interrupt 14 */ |
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14; |
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} |
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if (!pil) {
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if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
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env->interrupt_index); |
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env->interrupt_index = 0; |
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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return; |
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} |
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if (cpu_interrupts_enabled(env)) {
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| 237 | 255 |
|
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if (pil && (env->interrupt_index == 0 || |
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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| 240 | 256 |
unsigned int i; |
| 241 | 257 |
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for (i = 15; i > 0; i--) {
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for (i = 15; i > env->psrpil; i--) {
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| 243 | 259 |
if (pil & (1 << i)) {
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| 244 | 260 |
int old_interrupt = env->interrupt_index; |
| 245 |
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env->interrupt_index = TT_EXTINT | i; |
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if (old_interrupt != env->interrupt_index) {
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CPUIRQ_DPRINTF("Set CPU IRQ %d\n", i);
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int new_interrupt = TT_EXTINT | i; |
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if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) {
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CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
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"current %x >= pending %x\n", |
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env->tl, cpu_tsptr(env)->tt, new_interrupt); |
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} else if (old_interrupt != new_interrupt) {
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env->interrupt_index = new_interrupt; |
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CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
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old_interrupt, new_interrupt); |
|
| 249 | 271 |
cpu_interrupt(env, CPU_INTERRUPT_HARD); |
| 250 | 272 |
} |
| 251 | 273 |
break; |
| 252 | 274 |
} |
| 253 | 275 |
} |
| 254 |
} else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
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CPUIRQ_DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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} else {
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CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
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"current interrupt %x\n",
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pil, env->pil_in, env->softint, env->interrupt_index);
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| 258 | 280 |
} |
| 259 | 281 |
} |
| 260 | 282 |
|
| b/target-sparc/cpu.h | ||
|---|---|---|
| 577 | 577 |
return 0; |
| 578 | 578 |
} |
| 579 | 579 |
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static inline int cpu_pil_allowed(CPUState *env1, int pil) |
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{
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#if !defined(TARGET_SPARC64) |
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/* level 15 is non-maskable on sparc v8 */ |
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return pil == 15 || pil > env1->psrpil; |
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#else |
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return pil > env1->psrpil; |
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#endif |
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} |
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| 580 | 590 |
static inline int cpu_fpu_enabled(CPUState *env1) |
| 581 | 591 |
{
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| 582 | 592 |
#if defined(CONFIG_USER_ONLY) |
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