Revision d532b26c hw/sun4u.c
| b/hw/sun4u.c | ||
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| 232 | 232 |
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| 233 | 233 |
void cpu_check_irqs(CPUState *env) |
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{
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uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) | |
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((env->softint & SOFTINT_TIMER) << 14); |
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uint32_t pil = env->pil_in | |
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(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); |
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/* check if TM or SM in SOFTINT are set |
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setting these also causes interrupt 14 */ |
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14; |
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} |
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if (!pil) {
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if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
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env->interrupt_index); |
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env->interrupt_index = 0; |
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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return; |
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} |
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if (cpu_interrupts_enabled(env)) {
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if (pil && (env->interrupt_index == 0 || |
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i; |
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for (i = 15; i > 0; i--) {
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for (i = 15; i > env->psrpil; i--) {
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if (pil & (1 << i)) {
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int old_interrupt = env->interrupt_index; |
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env->interrupt_index = TT_EXTINT | i; |
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if (old_interrupt != env->interrupt_index) {
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CPUIRQ_DPRINTF("Set CPU IRQ %d\n", i);
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int new_interrupt = TT_EXTINT | i; |
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if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) {
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CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
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"current %x >= pending %x\n", |
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env->tl, cpu_tsptr(env)->tt, new_interrupt); |
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} else if (old_interrupt != new_interrupt) {
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env->interrupt_index = new_interrupt; |
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CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
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old_interrupt, new_interrupt); |
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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break; |
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} |
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} |
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} else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
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CPUIRQ_DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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} else {
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CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
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"current interrupt %x\n",
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pil, env->pil_in, env->softint, env->interrupt_index);
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} |
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} |
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