Revision d537cf6c hw/arm_timer.c
| b/hw/arm_timer.c | ||
|---|---|---|
| 32 | 32 |
int raw_freq; |
| 33 | 33 |
int freq; |
| 34 | 34 |
int int_level; |
| 35 |
void *pic; |
|
| 36 |
int irq; |
|
| 35 |
qemu_irq irq; |
|
| 37 | 36 |
} arm_timer_state; |
| 38 | 37 |
|
| 39 | 38 |
/* Calculate the new expiry time of the given timer. */ |
| ... | ... | |
| 85 | 84 |
} |
| 86 | 85 |
/* Update interrupts. */ |
| 87 | 86 |
if (s->int_level && (s->control & TIMER_CTRL_IE)) {
|
| 88 |
pic_set_irq_new(s->pic, s->irq, 1);
|
|
| 87 |
qemu_irq_raise(s->irq);
|
|
| 89 | 88 |
} else {
|
| 90 |
pic_set_irq_new(s->pic, s->irq, 0);
|
|
| 89 |
qemu_irq_lower(s->irq);
|
|
| 91 | 90 |
} |
| 92 | 91 |
|
| 93 | 92 |
next = now; |
| ... | ... | |
| 215 | 214 |
arm_timer_update((arm_timer_state *)opaque, now); |
| 216 | 215 |
} |
| 217 | 216 |
|
| 218 |
static void *arm_timer_init(uint32_t freq, void *pic, int irq)
|
|
| 217 |
static void *arm_timer_init(uint32_t freq, qemu_irq irq)
|
|
| 219 | 218 |
{
|
| 220 | 219 |
arm_timer_state *s; |
| 221 | 220 |
|
| 222 | 221 |
s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state)); |
| 223 |
s->pic = pic; |
|
| 224 | 222 |
s->irq = irq; |
| 225 | 223 |
s->raw_freq = s->freq = 1000000; |
| 226 | 224 |
s->control = TIMER_CTRL_IE; |
| ... | ... | |
| 237 | 235 |
Integrator/CP timer modules. */ |
| 238 | 236 |
|
| 239 | 237 |
typedef struct {
|
| 240 |
/* Include a pseudo-PIC device to merge the two interrupt sources. */ |
|
| 241 |
arm_pic_handler handler; |
|
| 242 | 238 |
void *timer[2]; |
| 243 | 239 |
int level[2]; |
| 244 | 240 |
uint32_t base; |
| 245 |
/* The output PIC device. */ |
|
| 246 |
void *pic; |
|
| 247 |
int irq; |
|
| 241 |
qemu_irq irq; |
|
| 248 | 242 |
} sp804_state; |
| 249 | 243 |
|
| 244 |
/* Merge the IRQs from the two component devices. */ |
|
| 250 | 245 |
static void sp804_set_irq(void *opaque, int irq, int level) |
| 251 | 246 |
{
|
| 252 | 247 |
sp804_state *s = (sp804_state *)opaque; |
| 253 | 248 |
|
| 254 | 249 |
s->level[irq] = level; |
| 255 |
pic_set_irq_new(s->pic, s->irq, s->level[0] || s->level[1]);
|
|
| 250 |
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
|
|
| 256 | 251 |
} |
| 257 | 252 |
|
| 258 | 253 |
static uint32_t sp804_read(void *opaque, target_phys_addr_t offset) |
| ... | ... | |
| 293 | 288 |
sp804_write |
| 294 | 289 |
}; |
| 295 | 290 |
|
| 296 |
void sp804_init(uint32_t base, void *pic, int irq)
|
|
| 291 |
void sp804_init(uint32_t base, qemu_irq irq)
|
|
| 297 | 292 |
{
|
| 298 | 293 |
int iomemtype; |
| 299 | 294 |
sp804_state *s; |
| 295 |
qemu_irq *qi; |
|
| 300 | 296 |
|
| 301 | 297 |
s = (sp804_state *)qemu_mallocz(sizeof(sp804_state)); |
| 302 |
s->handler = sp804_set_irq;
|
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| 298 |
qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
|
|
| 303 | 299 |
s->base = base; |
| 304 |
s->pic = pic; |
|
| 305 | 300 |
s->irq = irq; |
| 306 | 301 |
/* ??? The timers are actually configurable between 32kHz and 1MHz, but |
| 307 | 302 |
we don't implement that. */ |
| 308 |
s->timer[0] = arm_timer_init(1000000, s, 0);
|
|
| 309 |
s->timer[1] = arm_timer_init(1000000, s, 1);
|
|
| 303 |
s->timer[0] = arm_timer_init(1000000, qi[0]);
|
|
| 304 |
s->timer[1] = arm_timer_init(1000000, qi[1]);
|
|
| 310 | 305 |
iomemtype = cpu_register_io_memory(0, sp804_readfn, |
| 311 | 306 |
sp804_writefn, s); |
| 312 | 307 |
cpu_register_physical_memory(base, 0x00000fff, iomemtype); |
| ... | ... | |
| 362 | 357 |
icp_pit_write |
| 363 | 358 |
}; |
| 364 | 359 |
|
| 365 |
void icp_pit_init(uint32_t base, void *pic, int irq)
|
|
| 360 |
void icp_pit_init(uint32_t base, qemu_irq *pic, int irq)
|
|
| 366 | 361 |
{
|
| 367 | 362 |
int iomemtype; |
| 368 | 363 |
icp_pit_state *s; |
| ... | ... | |
| 370 | 365 |
s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state)); |
| 371 | 366 |
s->base = base; |
| 372 | 367 |
/* Timer 0 runs at the system clock speed (40MHz). */ |
| 373 |
s->timer[0] = arm_timer_init(40000000, pic, irq);
|
|
| 368 |
s->timer[0] = arm_timer_init(40000000, pic[irq]);
|
|
| 374 | 369 |
/* The other two timers run at 1MHz. */ |
| 375 |
s->timer[1] = arm_timer_init(1000000, pic, irq + 1);
|
|
| 376 |
s->timer[2] = arm_timer_init(1000000, pic, irq + 2);
|
|
| 370 |
s->timer[1] = arm_timer_init(1000000, pic[irq + 1]);
|
|
| 371 |
s->timer[2] = arm_timer_init(1000000, pic[irq + 2]);
|
|
| 377 | 372 |
|
| 378 | 373 |
iomemtype = cpu_register_io_memory(0, icp_pit_readfn, |
| 379 | 374 |
icp_pit_writefn, s); |
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