Revision d537cf6c hw/fdc.c
| b/hw/fdc.c | ||
|---|---|---|
| 368 | 368 |
/* Controller's identification */ |
| 369 | 369 |
uint8_t version; |
| 370 | 370 |
/* HW */ |
| 371 |
int irq_lvl;
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| 371 |
qemu_irq irq;
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| 372 | 372 |
int dma_chann; |
| 373 | 373 |
uint32_t io_base; |
| 374 | 374 |
/* Controller state */ |
| ... | ... | |
| 485 | 485 |
fdctrl_write_mem, |
| 486 | 486 |
}; |
| 487 | 487 |
|
| 488 |
fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped,
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| 488 |
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
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|
| 489 | 489 |
uint32_t io_base, |
| 490 | 490 |
BlockDriverState **fds) |
| 491 | 491 |
{
|
| ... | ... | |
| 501 | 501 |
fdctrl_result_timer, fdctrl); |
| 502 | 502 |
|
| 503 | 503 |
fdctrl->version = 0x90; /* Intel 82078 controller */ |
| 504 |
fdctrl->irq_lvl = irq_lvl;
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| 504 |
fdctrl->irq = irq;
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| 505 | 505 |
fdctrl->dma_chann = dma_chann; |
| 506 | 506 |
fdctrl->io_base = io_base; |
| 507 | 507 |
fdctrl->config = 0x60; /* Implicit seek, polling & FIFO enabled */ |
| ... | ... | |
| 542 | 542 |
static void fdctrl_reset_irq (fdctrl_t *fdctrl) |
| 543 | 543 |
{
|
| 544 | 544 |
FLOPPY_DPRINTF("Reset interrupt\n");
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| 545 |
pic_set_irq(fdctrl->irq_lvl, 0);
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| 545 |
qemu_set_irq(fdctrl->irq, 0);
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| 546 | 546 |
fdctrl->state &= ~FD_CTRL_INTR; |
| 547 | 547 |
} |
| 548 | 548 |
|
| ... | ... | |
| 557 | 557 |
} |
| 558 | 558 |
#endif |
| 559 | 559 |
if (~(fdctrl->state & FD_CTRL_INTR)) {
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| 560 |
pic_set_irq(fdctrl->irq_lvl, 1);
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| 560 |
qemu_set_irq(fdctrl->irq, 1);
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| 561 | 561 |
fdctrl->state |= FD_CTRL_INTR; |
| 562 | 562 |
} |
| 563 | 563 |
FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", status);
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