Revision d537cf6c hw/i8259.c
| b/hw/i8259.c | ||
|---|---|---|
| 54 | 54 |
/* 0 is master pic, 1 is slave pic */ |
| 55 | 55 |
/* XXX: better separation between the two pics */ |
| 56 | 56 |
PicState pics[2]; |
| 57 |
IRQRequestFunc *irq_request;
|
|
| 57 |
qemu_irq parent_irq;
|
|
| 58 | 58 |
void *irq_request_opaque; |
| 59 | 59 |
/* IOAPIC callback support */ |
| 60 | 60 |
SetIRQFunc *alt_irq_func; |
| ... | ... | |
| 160 | 160 |
} |
| 161 | 161 |
printf("pic: cpu_interrupt\n");
|
| 162 | 162 |
#endif |
| 163 |
s->irq_request(s->irq_request_opaque, 1);
|
|
| 163 |
qemu_irq_raise(s->parent_irq);
|
|
| 164 | 164 |
} |
| 165 | 165 |
|
| 166 | 166 |
/* all targets should do this rather than acking the IRQ in the cpu */ |
| 167 | 167 |
#if defined(TARGET_MIPS) |
| 168 | 168 |
else {
|
| 169 |
s->irq_request(s->irq_request_opaque, 0);
|
|
| 169 |
qemu_irq_lower(s->parent_irq);
|
|
| 170 | 170 |
} |
| 171 | 171 |
#endif |
| 172 | 172 |
} |
| ... | ... | |
| 175 | 175 |
int64_t irq_time[16]; |
| 176 | 176 |
#endif |
| 177 | 177 |
|
| 178 |
void pic_set_irq_new(void *opaque, int irq, int level)
|
|
| 178 |
void i8259_set_irq(void *opaque, int irq, int level)
|
|
| 179 | 179 |
{
|
| 180 | 180 |
PicState2 *s = opaque; |
| 181 | 181 |
|
| 182 | 182 |
#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) |
| 183 | 183 |
if (level != irq_level[irq]) {
|
| 184 | 184 |
#if defined(DEBUG_PIC) |
| 185 |
printf("pic_set_irq: irq=%d level=%d\n", irq, level);
|
|
| 185 |
printf("i8259_set_irq: irq=%d level=%d\n", irq, level);
|
|
| 186 | 186 |
#endif |
| 187 | 187 |
irq_level[irq] = level; |
| 188 | 188 |
#ifdef DEBUG_IRQ_COUNT |
| ... | ... | |
| 203 | 203 |
pic_update_irq(s); |
| 204 | 204 |
} |
| 205 | 205 |
|
| 206 |
/* obsolete function */ |
|
| 207 |
void pic_set_irq(int irq, int level) |
|
| 208 |
{
|
|
| 209 |
pic_set_irq_new(isa_pic, irq, level); |
|
| 210 |
} |
|
| 211 |
|
|
| 212 | 206 |
/* acknowledge interrupt 'irq' */ |
| 213 | 207 |
static inline void pic_intack(PicState *s, int irq) |
| 214 | 208 |
{
|
| ... | ... | |
| 297 | 291 |
/* init */ |
| 298 | 292 |
pic_reset(s); |
| 299 | 293 |
/* deassert a pending interrupt */ |
| 300 |
s->pics_state->irq_request(s->pics_state->irq_request_opaque, 0);
|
|
| 294 |
qemu_irq_lower(s->pics_state->parent_irq);
|
|
| 301 | 295 |
s->init_state = 1; |
| 302 | 296 |
s->init4 = val & 1; |
| 303 | 297 |
s->single_mode = val & 2; |
| ... | ... | |
| 546 | 540 |
#endif |
| 547 | 541 |
} |
| 548 | 542 |
|
| 549 |
PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque)
|
|
| 543 |
qemu_irq *i8259_init(qemu_irq parent_irq)
|
|
| 550 | 544 |
{
|
| 551 | 545 |
PicState2 *s; |
| 546 |
|
|
| 552 | 547 |
s = qemu_mallocz(sizeof(PicState2)); |
| 553 | 548 |
if (!s) |
| 554 | 549 |
return NULL; |
| ... | ... | |
| 556 | 551 |
pic_init1(0xa0, 0x4d1, &s->pics[1]); |
| 557 | 552 |
s->pics[0].elcr_mask = 0xf8; |
| 558 | 553 |
s->pics[1].elcr_mask = 0xde; |
| 559 |
s->irq_request = irq_request; |
|
| 560 |
s->irq_request_opaque = irq_request_opaque; |
|
| 554 |
s->parent_irq = parent_irq; |
|
| 561 | 555 |
s->pics[0].pics_state = s; |
| 562 | 556 |
s->pics[1].pics_state = s; |
| 563 |
return s; |
|
| 557 |
isa_pic = s; |
|
| 558 |
return qemu_allocate_irqs(i8259_set_irq, s, 16); |
|
| 564 | 559 |
} |
| 565 | 560 |
|
| 566 | 561 |
void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func, |
Also available in: Unified diff