Revision d537cf6c hw/ide.c
| b/hw/ide.c | ||
|---|---|---|
| 300 | 300 |
int mult_sectors; |
| 301 | 301 |
int identify_set; |
| 302 | 302 |
uint16_t identify_data[256]; |
| 303 |
SetIRQFunc *set_irq; |
|
| 304 |
void *irq_opaque; |
|
| 305 |
int irq; |
|
| 303 |
qemu_irq irq; |
|
| 306 | 304 |
PCIDevice *pci_dev; |
| 307 | 305 |
struct BMDMAState *bmdma; |
| 308 | 306 |
int drive_serial; |
| ... | ... | |
| 575 | 573 |
if (bm) {
|
| 576 | 574 |
bm->status |= BM_STATUS_INT; |
| 577 | 575 |
} |
| 578 |
s->set_irq(s->irq_opaque, s->irq, 1);
|
|
| 576 |
qemu_irq_raise(s->irq);
|
|
| 579 | 577 |
} |
| 580 | 578 |
} |
| 581 | 579 |
|
| ... | ... | |
| 1889 | 1887 |
ret = 0; |
| 1890 | 1888 |
else |
| 1891 | 1889 |
ret = s->status; |
| 1892 |
s->set_irq(s->irq_opaque, s->irq, 0);
|
|
| 1890 |
qemu_irq_lower(s->irq);
|
|
| 1893 | 1891 |
break; |
| 1894 | 1892 |
} |
| 1895 | 1893 |
#ifdef DEBUG_IDE |
| ... | ... | |
| 2084 | 2082 |
|
| 2085 | 2083 |
static void ide_init2(IDEState *ide_state, |
| 2086 | 2084 |
BlockDriverState *hd0, BlockDriverState *hd1, |
| 2087 |
SetIRQFunc *set_irq, void *irq_opaque, int irq)
|
|
| 2085 |
qemu_irq irq)
|
|
| 2088 | 2086 |
{
|
| 2089 | 2087 |
IDEState *s; |
| 2090 | 2088 |
static int drive_serial = 1; |
| ... | ... | |
| 2155 | 2153 |
} |
| 2156 | 2154 |
} |
| 2157 | 2155 |
s->drive_serial = drive_serial++; |
| 2158 |
s->set_irq = set_irq; |
|
| 2159 |
s->irq_opaque = irq_opaque; |
|
| 2160 | 2156 |
s->irq = irq; |
| 2161 | 2157 |
s->sector_write_timer = qemu_new_timer(vm_clock, |
| 2162 | 2158 |
ide_sector_write_timer_cb, s); |
| ... | ... | |
| 2183 | 2179 |
/***********************************************************/ |
| 2184 | 2180 |
/* ISA IDE definitions */ |
| 2185 | 2181 |
|
| 2186 |
void isa_ide_init(int iobase, int iobase2, int irq,
|
|
| 2182 |
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
|
|
| 2187 | 2183 |
BlockDriverState *hd0, BlockDriverState *hd1) |
| 2188 | 2184 |
{
|
| 2189 | 2185 |
IDEState *ide_state; |
| ... | ... | |
| 2192 | 2188 |
if (!ide_state) |
| 2193 | 2189 |
return; |
| 2194 | 2190 |
|
| 2195 |
ide_init2(ide_state, hd0, hd1, pic_set_irq_new, isa_pic, irq);
|
|
| 2191 |
ide_init2(ide_state, hd0, hd1, irq); |
|
| 2196 | 2192 |
ide_init_ioport(ide_state, iobase, iobase2); |
| 2197 | 2193 |
} |
| 2198 | 2194 |
|
| ... | ... | |
| 2399 | 2395 |
!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) || |
| 2400 | 2396 |
((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) && |
| 2401 | 2397 |
!(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1)); |
| 2402 |
pci_set_irq((PCIDevice *)d, 0, pci_level);
|
|
| 2398 |
qemu_set_irq(d->dev.irq[0], pci_level);
|
|
| 2403 | 2399 |
} |
| 2404 | 2400 |
|
| 2405 | 2401 |
/* the PCI irq level is the logical OR of the two channels */ |
| ... | ... | |
| 2423 | 2419 |
PCIIDEState *d; |
| 2424 | 2420 |
uint8_t *pci_conf; |
| 2425 | 2421 |
int i; |
| 2422 |
qemu_irq *irq; |
|
| 2426 | 2423 |
|
| 2427 | 2424 |
d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE", |
| 2428 | 2425 |
sizeof(PCIIDEState), |
| ... | ... | |
| 2462 | 2459 |
|
| 2463 | 2460 |
for(i = 0; i < 4; i++) |
| 2464 | 2461 |
d->ide_if[i].pci_dev = (PCIDevice *)d; |
| 2465 |
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], |
|
| 2466 |
cmd646_set_irq, d, 0);
|
|
| 2467 |
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3],
|
|
| 2468 |
cmd646_set_irq, d, 1);
|
|
| 2462 |
|
|
| 2463 |
irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
|
|
| 2464 |
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], irq[0]);
|
|
| 2465 |
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);
|
|
| 2469 | 2466 |
} |
| 2470 | 2467 |
|
| 2471 | 2468 |
static void pci_ide_save(QEMUFile* f, void *opaque) |
| ... | ... | |
| 2592 | 2589 |
|
| 2593 | 2590 |
/* hd_table must contain 4 block drivers */ |
| 2594 | 2591 |
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ |
| 2595 |
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn) |
|
| 2592 |
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
|
| 2593 |
qemu_irq *pic) |
|
| 2596 | 2594 |
{
|
| 2597 | 2595 |
PCIIDEState *d; |
| 2598 | 2596 |
uint8_t *pci_conf; |
| ... | ... | |
| 2619 | 2617 |
pci_register_io_region((PCIDevice *)d, 4, 0x10, |
| 2620 | 2618 |
PCI_ADDRESS_SPACE_IO, bmdma_map); |
| 2621 | 2619 |
|
| 2622 |
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], |
|
| 2623 |
pic_set_irq_new, isa_pic, 14); |
|
| 2624 |
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], |
|
| 2625 |
pic_set_irq_new, isa_pic, 15); |
|
| 2620 |
ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]); |
|
| 2621 |
ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]); |
|
| 2626 | 2622 |
ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6); |
| 2627 | 2623 |
ide_init_ioport(&d->ide_if[2], 0x170, 0x376); |
| 2628 | 2624 |
|
| ... | ... | |
| 2741 | 2737 |
/* hd_table must contain 4 block drivers */ |
| 2742 | 2738 |
/* PowerMac uses memory mapped registers, not I/O. Return the memory |
| 2743 | 2739 |
I/O index to access the ide. */ |
| 2744 |
int pmac_ide_init (BlockDriverState **hd_table, |
|
| 2745 |
SetIRQFunc *set_irq, void *irq_opaque, int irq) |
|
| 2740 |
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq) |
|
| 2746 | 2741 |
{
|
| 2747 | 2742 |
IDEState *ide_if; |
| 2748 | 2743 |
int pmac_ide_memory; |
| 2749 | 2744 |
|
| 2750 | 2745 |
ide_if = qemu_mallocz(sizeof(IDEState) * 2); |
| 2751 |
ide_init2(&ide_if[0], hd_table[0], hd_table[1], |
|
| 2752 |
set_irq, irq_opaque, irq); |
|
| 2746 |
ide_init2(&ide_if[0], hd_table[0], hd_table[1], irq); |
|
| 2753 | 2747 |
|
| 2754 | 2748 |
pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read, |
| 2755 | 2749 |
pmac_ide_write, &ide_if[0]); |
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