Revision d537cf6c hw/integratorcp.c
| b/hw/integratorcp.c | ||
|---|---|---|
| 267 | 267 |
|
| 268 | 268 |
typedef struct icp_pic_state |
| 269 | 269 |
{
|
| 270 |
arm_pic_handler handler; |
|
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uint32_t base; |
| 272 | 271 |
uint32_t level; |
| 273 | 272 |
uint32_t irq_enabled; |
| 274 | 273 |
uint32_t fiq_enabled; |
| 275 |
void *parent; |
|
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int parent_irq; |
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int parent_fiq; |
|
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qemu_irq parent_irq; |
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qemu_irq parent_fiq; |
|
| 278 | 276 |
} icp_pic_state; |
| 279 | 277 |
|
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static void icp_pic_update(icp_pic_state *s) |
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{
|
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uint32_t flags; |
| 283 | 281 |
|
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if (s->parent_irq != -1) {
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flags = (s->level & s->irq_enabled); |
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pic_set_irq_new(s->parent, s->parent_irq, flags != 0); |
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} |
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if (s->parent_fiq != -1) {
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flags = (s->level & s->fiq_enabled); |
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pic_set_irq_new(s->parent, s->parent_fiq, flags != 0); |
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} |
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flags = (s->level & s->irq_enabled); |
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qemu_set_irq(s->parent_irq, flags != 0); |
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flags = (s->level & s->fiq_enabled); |
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qemu_set_irq(s->parent_fiq, flags != 0); |
|
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} |
| 293 | 287 |
|
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static void icp_pic_set_irq(void *opaque, int irq, int level) |
| ... | ... | |
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break; |
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case 4: /* INT_SOFTSET */ |
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if (value & 1) |
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pic_set_irq_new(s, 0, 1);
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icp_pic_set_irq(s, 0, 1);
|
|
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break; |
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case 5: /* INT_SOFTCLR */ |
| 351 | 345 |
if (value & 1) |
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pic_set_irq_new(s, 0, 0);
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icp_pic_set_irq(s, 0, 0);
|
|
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break; |
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case 10: /* FRQ_ENABLESET */ |
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s->fiq_enabled |= value; |
| ... | ... | |
| 380 | 374 |
icp_pic_write |
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}; |
| 382 | 376 |
|
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static icp_pic_state *icp_pic_init(uint32_t base, void *parent,
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int parent_irq, int parent_fiq)
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static qemu_irq *icp_pic_init(uint32_t base,
|
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qemu_irq parent_irq, qemu_irq parent_fiq)
|
|
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{
|
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icp_pic_state *s; |
| 387 | 381 |
int iomemtype; |
| 382 |
qemu_irq *qi; |
|
| 388 | 383 |
|
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s = (icp_pic_state *)qemu_mallocz(sizeof(icp_pic_state)); |
| 390 | 385 |
if (!s) |
| 391 | 386 |
return NULL; |
| 392 |
s->handler = icp_pic_set_irq;
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qi = qemu_allocate_irqs(icp_pic_set_irq, s, 32);
|
|
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s->base = base; |
| 394 |
s->parent = parent; |
|
| 395 | 389 |
s->parent_irq = parent_irq; |
| 396 | 390 |
s->parent_fiq = parent_fiq; |
| 397 | 391 |
iomemtype = cpu_register_io_memory(0, icp_pic_readfn, |
| 398 | 392 |
icp_pic_writefn, s); |
| 399 | 393 |
cpu_register_physical_memory(base, 0x007fffff, iomemtype); |
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/* ??? Save/restore. */ |
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return s;
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return qi;
|
|
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} |
| 403 | 397 |
|
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/* CP control registers. */ |
| ... | ... | |
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{
|
| 476 | 470 |
CPUState *env; |
| 477 | 471 |
uint32_t bios_offset; |
| 478 |
icp_pic_state *pic;
|
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void *cpu_pic;
|
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qemu_irq *pic;
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qemu_irq *cpu_pic;
|
|
| 480 | 474 |
|
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env = cpu_init(); |
| 482 | 476 |
if (!cpu_model) |
| ... | ... | |
| 492 | 486 |
|
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integratorcm_init(ram_size >> 20, bios_offset); |
| 494 | 488 |
cpu_pic = arm_pic_init_cpu(env); |
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pic = icp_pic_init(0x14000000, cpu_pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ); |
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icp_pic_init(0xca000000, pic, 26, -1); |
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pic = icp_pic_init(0x14000000, cpu_pic[ARM_PIC_CPU_IRQ], |
|
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cpu_pic[ARM_PIC_CPU_FIQ]); |
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icp_pic_init(0xca000000, pic[26], NULL); |
|
| 497 | 492 |
icp_pit_init(0x13000000, pic, 5); |
| 498 |
pl011_init(0x16000000, pic, 1, serial_hds[0]);
|
|
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pl011_init(0x17000000, pic, 2, serial_hds[1]);
|
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pl011_init(0x16000000, pic[1], serial_hds[0]);
|
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pl011_init(0x17000000, pic[2], serial_hds[1]);
|
|
| 500 | 495 |
icp_control_init(0xcb000000); |
| 501 |
pl050_init(0x18000000, pic, 3, 0);
|
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pl050_init(0x19000000, pic, 4, 1);
|
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pl181_init(0x1c000000, sd_bdrv, pic, 23, 24);
|
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pl050_init(0x18000000, pic[3], 0);
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pl050_init(0x19000000, pic[4], 1);
|
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pl181_init(0x1c000000, sd_bdrv, pic[23], pic[24]);
|
|
| 504 | 499 |
if (nd_table[0].vlan) {
|
| 505 | 500 |
if (nd_table[0].model == NULL |
| 506 | 501 |
|| strcmp(nd_table[0].model, "smc91c111") == 0) {
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smc91c111_init(&nd_table[0], 0xc8000000, pic, 27);
|
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smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
|
|
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} else {
|
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
| 510 | 505 |
exit (1); |
| 511 | 506 |
} |
| 512 | 507 |
} |
| 513 |
pl110_init(ds, 0xc0000000, pic, 22, 0);
|
|
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pl110_init(ds, 0xc0000000, pic[22], 0);
|
|
| 514 | 509 |
|
| 515 | 510 |
arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline, |
| 516 | 511 |
initrd_filename, 0x113); |
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