Revision d537cf6c hw/m48t59.c
b/hw/m48t59.c | ||
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41 | 41 |
/* Model parameters */ |
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int type; // 8 = m48t08, 59 = m48t59 |
43 | 43 |
/* Hardware parameters */ |
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int IRQ;
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qemu_irq IRQ;
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45 | 45 |
int mem_index; |
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uint32_t mem_base; |
47 | 47 |
uint32_t io_base; |
... | ... | |
100 | 100 |
uint64_t next_time; |
101 | 101 |
m48t59_t *NVRAM = opaque; |
102 | 102 |
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pic_set_irq(NVRAM->IRQ, 1);
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qemu_set_irq(NVRAM->IRQ, 1);
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104 | 104 |
if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
105 | 105 |
(NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
106 | 106 |
(NVRAM->buffer[0x1FF3] & 0x80) == 0 && |
... | ... | |
137 | 137 |
next_time = 1 + mktime(&tm_now); |
138 | 138 |
} |
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qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000); |
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pic_set_irq(NVRAM->IRQ, 0);
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qemu_set_irq(NVRAM->IRQ, 0);
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141 | 141 |
} |
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143 | 143 |
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... | ... | |
173 | 173 |
/* May it be a hw CPU Reset instead ? */ |
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qemu_system_reset_request(); |
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} else { |
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pic_set_irq(NVRAM->IRQ, 1);
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pic_set_irq(NVRAM->IRQ, 0);
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qemu_set_irq(NVRAM->IRQ, 1);
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qemu_set_irq(NVRAM->IRQ, 0);
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178 | 178 |
} |
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} |
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... | ... | |
576 | 576 |
}; |
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578 | 578 |
/* Initialisation routine */ |
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m48t59_t *m48t59_init (int IRQ, target_ulong mem_base,
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m48t59_t *m48t59_init (qemu_irq IRQ, target_ulong mem_base,
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580 | 580 |
uint32_t io_base, uint16_t size, |
581 | 581 |
int type) |
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{ |
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