Revision d537cf6c hw/mips_int.c
b/hw/mips_int.c | ||
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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void cpu_mips_irq_request(void *opaque, int irq, int level) |
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static void cpu_mips_irq_request(void *opaque, int irq, int level)
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21 | 21 |
{ |
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CPUState *env = (CPUState *)opaque; |
23 | 23 |
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... | ... | |
31 | 31 |
} |
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cpu_mips_update_irq(env); |
33 | 33 |
} |
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void cpu_mips_irq_init_cpu(CPUState *env) |
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{ |
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qemu_irq *qi; |
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int i; |
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qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8); |
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for (i = 0; i < 8; i++) { |
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env->irq[i] = qi[i]; |
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} |
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} |
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