Revision d537cf6c hw/mips_timer.c

b/hw/mips_timer.c
63 63 
    cpu_mips_update_count(env, cpu_mips_get_count(env));
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    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))
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        env->CP0_Cause &= ~(1 << CP0Ca_TI);
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    cpu_mips_irq_request(env, 7, 0);
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    qemu_irq_lower(env->irq[7]);
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}
68 68 

  		





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static void mips_timer_cb (void *opaque)


  		





  ......




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    cpu_mips_update_count(env, cpu_mips_get_count(env));


  		





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    if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))


  		





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        env->CP0_Cause |= 1 << CP0Ca_TI;


  		





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    cpu_mips_irq_request(env, 7, 1);


  		





  
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    qemu_irq_raise(env->irq[7]);


  		





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}


  		





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void cpu_mips_clock_init (CPUState *env)


  		












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