Revision d537cf6c hw/piix_pci.c
| b/hw/piix_pci.c | ||
|---|---|---|
| 40 | 40 |
return s->config_reg; |
| 41 | 41 |
} |
| 42 | 42 |
|
| 43 |
static void piix3_set_irq(void *pic, int irq_num, int level);
|
|
| 43 |
static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);
|
|
| 44 | 44 |
|
| 45 | 45 |
/* return the global irq number corresponding to a given device irq |
| 46 | 46 |
pin. We could also use the bus number to have a more precise |
| ... | ... | |
| 155 | 155 |
return 0; |
| 156 | 156 |
} |
| 157 | 157 |
|
| 158 |
PCIBus *i440fx_init(PCIDevice **pi440fx_state) |
|
| 158 |
PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
|
|
| 159 | 159 |
{
|
| 160 | 160 |
PCIBus *b; |
| 161 | 161 |
PCIDevice *d; |
| 162 | 162 |
I440FXState *s; |
| 163 | 163 |
|
| 164 | 164 |
s = qemu_mallocz(sizeof(I440FXState)); |
| 165 |
b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, NULL, 0, 4);
|
|
| 165 |
b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);
|
|
| 166 | 166 |
s->bus = b; |
| 167 | 167 |
|
| 168 | 168 |
register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s); |
| ... | ... | |
| 204 | 204 |
|
| 205 | 205 |
static int pci_irq_levels[4]; |
| 206 | 206 |
|
| 207 |
static void piix3_set_irq(void *pic, int irq_num, int level)
|
|
| 207 |
static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)
|
|
| 208 | 208 |
{
|
| 209 | 209 |
int i, pic_irq, pic_level; |
| 210 | 210 |
|
| ... | ... | |
| 221 | 221 |
if (pic_irq == piix3_dev->config[0x60 + i]) |
| 222 | 222 |
pic_level |= pci_irq_levels[i]; |
| 223 | 223 |
} |
| 224 |
pic_set_irq(pic_irq, pic_level);
|
|
| 224 |
qemu_set_irq(pic[pic_irq], pic_level);
|
|
| 225 | 225 |
} |
| 226 | 226 |
} |
| 227 | 227 |
|
Also available in: Unified diff