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    int read_count;

    int read_trigger;

    CharDriverState *chr;

} pl011_state;

#define PL011_INT_TX 0x20

    uint32_t flags;

    flags = s->int_level & s->int_enabled;

}

static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)

   pl011_write

};

                CharDriverState *chr)

{

    int iomemtype;

                                       pl011_writefn, s);

    cpu_register_physical_memory(base, 0x00000fff, iomemtype);

    s->base = base;

    s->irq = irq;

    s->chr = chr;

    s->read_trigger = 1;