Revision d537cf6c hw/pl190.c
| b/hw/pl190.c | ||
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| 17 | 17 |
#define PL190_NUM_PRIO 17 |
| 18 | 18 |
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typedef struct {
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arm_pic_handler handler; |
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uint32_t base; |
| 22 | 21 |
DisplayState *ds; |
| 23 | 22 |
uint32_t level; |
| ... | ... | |
| 33 | 32 |
/* Current priority level. */ |
| 34 | 33 |
int priority; |
| 35 | 34 |
int prev_prio[PL190_NUM_PRIO]; |
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void *parent; |
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int irq; |
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int fiq; |
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qemu_irq irq; |
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qemu_irq fiq; |
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} pl190_state; |
| 40 | 38 |
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static const unsigned char pl190_id[] = |
| ... | ... | |
| 53 | 51 |
int set; |
| 54 | 52 |
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set = (level & s->prio_mask[s->priority]) != 0; |
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pic_set_irq_new(s->parent, s->irq, set);
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qemu_set_irq(s->irq, set);
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set = ((s->level | s->soft_level) & s->fiq_select) != 0; |
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pic_set_irq_new(s->parent, s->fiq, set);
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qemu_set_irq(s->fiq, set);
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} |
| 60 | 58 |
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static void pl190_set_irq(void *opaque, int irq, int level) |
| ... | ... | |
| 232 | 230 |
pl190_update_vectors(s); |
| 233 | 231 |
} |
| 234 | 232 |
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void *pl190_init(uint32_t base, void *parent, int irq, int fiq)
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qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq)
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{
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pl190_state *s; |
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qemu_irq *qi; |
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int iomemtype; |
| 239 | 238 |
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s = (pl190_state *)qemu_mallocz(sizeof(pl190_state)); |
| 241 | 240 |
iomemtype = cpu_register_io_memory(0, pl190_readfn, |
| 242 | 241 |
pl190_writefn, s); |
| 243 | 242 |
cpu_register_physical_memory(base, 0x00000fff, iomemtype); |
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s->handler = pl190_set_irq;
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qi = qemu_allocate_irqs(pl190_set_irq, s, 16);
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s->base = base; |
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s->parent = parent; |
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s->irq = irq; |
| 248 | 246 |
s->fiq = fiq; |
| 249 | 247 |
pl190_reset(s); |
| 250 | 248 |
/* ??? Save/restore. */ |
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return s;
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return qi;
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} |
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