Revision d537cf6c hw/ppc_prep.c
| b/hw/ppc_prep.c | ||
|---|---|---|
| 96 | 96 |
return 0; |
| 97 | 97 |
} |
| 98 | 98 |
|
| 99 |
static void pic_irq_request (void *opaque, int level) |
|
| 100 |
{
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|
| 101 |
ppc_set_irq(opaque, PPC_INTERRUPT_EXT, level); |
|
| 102 |
} |
|
| 103 |
|
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| 104 | 99 |
/* PCI intack register */ |
| 105 | 100 |
/* Read-only register (?) */ |
| 106 | 101 |
static void _PPC_intack_write (void *opaque, |
| ... | ... | |
| 532 | 527 |
uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
| 533 | 528 |
ppc_def_t *def; |
| 534 | 529 |
PCIBus *pci_bus; |
| 530 |
qemu_irq *i8259; |
|
| 535 | 531 |
|
| 536 | 532 |
sysctrl = qemu_mallocz(sizeof(sysctrl_t)); |
| 537 | 533 |
if (sysctrl == NULL) |
| ... | ... | |
| 552 | 548 |
cpu_abort(env, "Unable to find PowerPC CPU definition\n"); |
| 553 | 549 |
} |
| 554 | 550 |
cpu_ppc_register(env, def); |
| 551 |
cpu_ppc_irq_init_cpu(env); |
|
| 555 | 552 |
/* Set time-base frequency to 100 Mhz */ |
| 556 | 553 |
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
| 557 | 554 |
|
| ... | ... | |
| 602 | 599 |
} |
| 603 | 600 |
|
| 604 | 601 |
isa_mem_base = 0xc0000000; |
| 605 |
pci_bus = pci_prep_init(); |
|
| 602 |
i8259 = i8259_init(first_cpu->irq[PPC_INTERRUPT_EXT]); |
|
| 603 |
pci_bus = pci_prep_init(i8259); |
|
| 606 | 604 |
// pci_bus = i440fx_init(); |
| 607 | 605 |
/* Register 8 MB of ISA IO space (needed for non-contiguous map) */ |
| 608 | 606 |
PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read, |
| ... | ... | |
| 612 | 610 |
/* init basic PC hardware */ |
| 613 | 611 |
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, |
| 614 | 612 |
vga_ram_size, 0, 0); |
| 615 |
rtc_init(0x70, 8); |
|
| 616 | 613 |
// openpic = openpic_init(0x00000000, 0xF0000000, 1); |
| 617 |
isa_pic = pic_init(pic_irq_request, first_cpu);
|
|
| 618 |
// pit = pit_init(0x40, 0);
|
|
| 614 |
// pit = pit_init(0x40, i8259[0]);
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| 615 |
rtc_init(0x70, i8259[8]);
|
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| 619 | 616 |
|
| 620 |
serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
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| 617 |
serial_init(0x3f8, i8259[4], serial_hds[0]);
|
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| 621 | 618 |
nb_nics1 = nb_nics; |
| 622 | 619 |
if (nb_nics1 > NE2000_NB_MAX) |
| 623 | 620 |
nb_nics1 = NE2000_NB_MAX; |
| 624 | 621 |
for(i = 0; i < nb_nics1; i++) {
|
| 625 | 622 |
if (nd_table[0].model == NULL |
| 626 | 623 |
|| strcmp(nd_table[0].model, "ne2k_isa") == 0) {
|
| 627 |
isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
|
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| 624 |
isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
|
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| 628 | 625 |
} else {
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| 629 | 626 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
| 630 | 627 |
exit (1); |
| ... | ... | |
| 632 | 629 |
} |
| 633 | 630 |
|
| 634 | 631 |
for(i = 0; i < 2; i++) {
|
| 635 |
isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
|
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isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
|
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| 636 | 633 |
bs_table[2 * i], bs_table[2 * i + 1]); |
| 637 | 634 |
} |
| 638 |
kbd_init();
|
|
| 635 |
i8042_init(i8259[1], i8259[12], 0x60);
|
|
| 639 | 636 |
DMA_init(1); |
| 640 | 637 |
// AUD_init(); |
| 641 | 638 |
// SB16_init(); |
| 642 | 639 |
|
| 643 |
fdctrl_init(6, 2, 0, 0x3f0, fd_table);
|
|
| 640 |
fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table);
|
|
| 644 | 641 |
|
| 645 | 642 |
/* Register speaker port */ |
| 646 | 643 |
register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); |
| ... | ... | |
| 667 | 664 |
usb_ohci_init_pci(pci_bus, 3, -1); |
| 668 | 665 |
} |
| 669 | 666 |
|
| 670 |
nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
|
|
| 667 |
nvram = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
|
|
| 671 | 668 |
if (nvram == NULL) |
| 672 | 669 |
return; |
| 673 | 670 |
sysctrl->nvram = nvram; |
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