Revision d537cf6c hw/sparc32_dma.c
| b/hw/sparc32_dma.c | ||
|---|---|---|
| 37 | 37 |
#ifdef DEBUG_DMA |
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#define DPRINTF(fmt, args...) \ |
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do { printf("DMA: " fmt , ##args); } while (0)
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#define pic_set_irq_new(ctl, irq, level) \ |
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do { printf("DMA: set_irq(%d): %d\n", (irq), (level)); \
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pic_set_irq_new((ctl), (irq),(level));} while (0) |
|
| 43 | 40 |
#else |
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#define DPRINTF(fmt, args...) |
| 45 | 42 |
#endif |
| ... | ... | |
| 58 | 55 |
|
| 59 | 56 |
struct DMAState {
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uint32_t dmaregs[DMA_REGS]; |
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int espirq, leirq; |
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void *iommu, *esp_opaque, *lance_opaque, *intctl; |
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qemu_irq espirq, leirq; |
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void *iommu, *esp_opaque, *lance_opaque; |
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qemu_irq *pic; |
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| 63 | 61 |
}; |
| 64 | 62 |
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void ledma_set_irq(void *opaque, int isr) |
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{
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DMAState *s = opaque; |
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pic_set_irq_new(s->intctl, s->leirq, isr); |
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} |
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/* Note: on sparc, the lance 16 bit bus is swapped */ |
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void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
| 74 | 65 |
uint8_t *buf, int len, int do_bswap) |
| ... | ... | |
| 125 | 116 |
{
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DMAState *s = opaque; |
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DPRINTF("Raise ESP IRQ\n");
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|
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s->dmaregs[0] |= DMA_INTR; |
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pic_set_irq_new(s->intctl, s->espirq, 1);
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qemu_irq_raise(s->espirq);
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} |
| 131 | 123 |
|
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void espdma_clear_irq(void *opaque) |
| ... | ... | |
| 134 | 126 |
DMAState *s = opaque; |
| 135 | 127 |
|
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s->dmaregs[0] &= ~DMA_INTR; |
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pic_set_irq_new(s->intctl, s->espirq, 0); |
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DPRINTF("Lower ESP IRQ\n");
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qemu_irq_lower(s->espirq); |
|
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} |
| 139 | 132 |
|
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void espdma_memory_read(void *opaque, uint8_t *buf, int len) |
| ... | ... | |
| 179 | 172 |
DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->dmaregs[saddr], val);
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switch (saddr) {
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case 0: |
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if (!(val & DMA_INTREN)) |
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pic_set_irq_new(s->intctl, s->espirq, 0); |
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if (!(val & DMA_INTREN)) {
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DPRINTF("Lower ESP IRQ\n");
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qemu_irq_lower(s->espirq); |
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} |
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if (val & DMA_RESET) {
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esp_reset(s->esp_opaque); |
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} else if (val & 0x40) {
|
| ... | ... | |
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s->dmaregs[0] |= DMA_LOADED; |
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break; |
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case 4: |
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if (!(val & DMA_INTREN)) |
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pic_set_irq_new(s->intctl, s->leirq, 0); |
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/* ??? Should this mask out the lance IRQ? The NIC may re-assert |
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this IRQ unexpectedly. */ |
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if (!(val & DMA_INTREN)) {
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DPRINTF("Lower Lance IRQ\n");
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qemu_irq_lower(s->leirq); |
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} |
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if (val & DMA_RESET) |
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pcnet_h_reset(s->lance_opaque); |
| 201 | 200 |
val &= 0x0fffffff; |
| ... | ... | |
| 250 | 249 |
return 0; |
| 251 | 250 |
} |
| 252 | 251 |
|
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void *sparc32_dma_init(uint32_t daddr, int espirq, int leirq, void *iommu, void *intctl) |
|
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void *sparc32_dma_init(uint32_t daddr, qemu_irq espirq, qemu_irq leirq, |
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void *iommu) |
|
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{
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DMAState *s; |
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int dma_io_memory; |
| ... | ... | |
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s->espirq = espirq; |
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s->leirq = leirq; |
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s->iommu = iommu; |
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s->intctl = intctl; |
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|
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dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s); |
| 268 | 267 |
cpu_register_physical_memory(daddr, 16 * 2, dma_io_memory); |
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