Revision d537cf6c hw/versatilepb.c
| b/hw/versatilepb.c | ||
|---|---|---|
| 14 | 14 |
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| 15 | 15 |
typedef struct vpb_sic_state |
| 16 | 16 |
{
|
| 17 |
arm_pic_handler handler; |
|
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uint32_t base; |
| 19 | 18 |
uint32_t level; |
| 20 | 19 |
uint32_t mask; |
| 21 | 20 |
uint32_t pic_enable; |
| 22 |
void *parent;
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|
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qemu_irq *parent;
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|
| 23 | 22 |
int irq; |
| 24 | 23 |
} vpb_sic_state; |
| 25 | 24 |
|
| ... | ... | |
| 28 | 27 |
uint32_t flags; |
| 29 | 28 |
|
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flags = s->level & s->mask; |
| 31 |
pic_set_irq_new(s->parent, s->irq, flags != 0);
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|
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qemu_set_irq(s->parent[s->irq], flags != 0);
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|
| 32 | 31 |
} |
| 33 | 32 |
|
| 34 | 33 |
static void vpb_sic_update_pic(vpb_sic_state *s) |
| ... | ... | |
| 40 | 39 |
mask = 1u << i; |
| 41 | 40 |
if (!(s->pic_enable & mask)) |
| 42 | 41 |
continue; |
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pic_set_irq_new(s->parent, i, (s->level & mask) != 0);
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|
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qemu_set_irq(s->parent[i], (s->level & mask) != 0);
|
|
| 44 | 43 |
} |
| 45 | 44 |
} |
| 46 | 45 |
|
| ... | ... | |
| 52 | 51 |
else |
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s->level &= ~(1u << irq); |
| 54 | 53 |
if (s->pic_enable & (1u << irq)) |
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pic_set_irq_new(s->parent, irq, level);
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qemu_set_irq(s->parent[irq], level);
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|
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vpb_sic_update(s); |
| 57 | 56 |
} |
| 58 | 57 |
|
| ... | ... | |
| 126 | 125 |
vpb_sic_write |
| 127 | 126 |
}; |
| 128 | 127 |
|
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static vpb_sic_state *vpb_sic_init(uint32_t base, void *parent, int irq)
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static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
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|
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{
|
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vpb_sic_state *s; |
| 131 |
qemu_irq *qi; |
|
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int iomemtype; |
| 133 | 133 |
|
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s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state)); |
| 135 | 135 |
if (!s) |
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return NULL; |
| 137 |
s->handler = vpb_sic_set_irq;
|
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qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
|
|
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s->base = base; |
| 139 | 139 |
s->parent = parent; |
| 140 | 140 |
s->irq = irq; |
| ... | ... | |
| 142 | 142 |
vpb_sic_writefn, s); |
| 143 | 143 |
cpu_register_physical_memory(base, 0x00000fff, iomemtype); |
| 144 | 144 |
/* ??? Save/restore. */ |
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return s;
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return qi;
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} |
| 147 | 147 |
|
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/* Board init. */ |
| ... | ... | |
| 158 | 158 |
int board_id) |
| 159 | 159 |
{
|
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CPUState *env; |
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void *pic;
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void *sic;
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qemu_irq *pic;
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qemu_irq *sic;
|
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| 163 | 163 |
void *scsi_hba; |
| 164 | 164 |
PCIBus *pci_bus; |
| 165 | 165 |
NICInfo *nd; |
| ... | ... | |
| 176 | 176 |
|
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arm_sysctl_init(0x10000000, 0x41007004); |
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pic = arm_pic_init_cpu(env); |
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pic = pl190_init(0x10140000, pic, ARM_PIC_CPU_IRQ, ARM_PIC_CPU_FIQ);
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pic = pl190_init(0x10140000, pic[0], pic[1]);
|
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sic = vpb_sic_init(0x10003000, pic, 31); |
| 181 |
pl050_init(0x10006000, sic, 3, 0);
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pl050_init(0x10007000, sic, 4, 1);
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pl050_init(0x10006000, sic[3], 0);
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pl050_init(0x10007000, sic[4], 1);
|
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| 183 | 183 |
|
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pci_bus = pci_vpb_init(sic, 27, 0); |
| 185 | 185 |
/* The Versatile PCI bridge does not provide access to PCI IO space, |
| ... | ... | |
| 189 | 189 |
if (!nd->model) |
| 190 | 190 |
nd->model = done_smc ? "rtl8139" : "smc91c111"; |
| 191 | 191 |
if (strcmp(nd->model, "smc91c111") == 0) {
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smc91c111_init(nd, 0x10010000, sic, 25);
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smc91c111_init(nd, 0x10010000, sic[25]);
|
|
| 193 | 193 |
} else {
|
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pci_nic_init(pci_bus, nd, -1); |
| 195 | 195 |
} |
| ... | ... | |
| 204 | 204 |
} |
| 205 | 205 |
} |
| 206 | 206 |
|
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pl011_init(0x101f1000, pic, 12, serial_hds[0]);
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pl011_init(0x101f2000, pic, 13, serial_hds[1]);
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pl011_init(0x101f3000, pic, 14, serial_hds[2]);
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pl011_init(0x10009000, sic, 6, serial_hds[3]);
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pl011_init(0x101f1000, pic[12], serial_hds[0]);
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pl011_init(0x101f2000, pic[13], serial_hds[1]);
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pl011_init(0x101f3000, pic[14], serial_hds[2]);
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pl011_init(0x10009000, sic[6], serial_hds[3]);
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| 211 | 211 |
|
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pl080_init(0x10130000, pic, 17, 8);
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sp804_init(0x101e2000, pic, 4);
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sp804_init(0x101e3000, pic, 5);
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pl080_init(0x10130000, pic[17], 8);
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sp804_init(0x101e2000, pic[4]);
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sp804_init(0x101e3000, pic[5]);
|
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| 215 | 215 |
|
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/* The versatile/PB actually has a modified Color LCD controller |
| 217 | 217 |
that includes hardware cursor support from the PL111. */ |
| 218 |
pl110_init(ds, 0x10120000, pic, 16, 1);
|
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pl110_init(ds, 0x10120000, pic[16], 1);
|
|
| 219 | 219 |
|
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pl181_init(0x10005000, sd_bdrv, sic, 22, 1);
|
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pl181_init(0x10005000, sd_bdrv, sic[22], sic[1]);
|
|
| 221 | 221 |
#if 0 |
| 222 | 222 |
/* Disabled because there's no way of specifying a block device. */ |
| 223 | 223 |
pl181_init(0x1000b000, NULL, sic, 23, 2); |
Also available in: Unified diff