Archipelago » qemu

int qemu_register_machine(QEMUMachine *m);

typedef void SetIRQFunc(void *opaque, int irq_num, int level);

#if defined(TARGET_PPC)

void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));

void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));

#endif

/* ISA bus */

extern target_phys_addr_t isa_mem_base;

    /* ??? This is a PC-specific hack, and should be removed.  */

    int irq_index;

    /* Current IRQ levels.  Used internally by the generic PCI code.  */

    int irq_state[4];

};

                            uint32_t size, int type, 

                            PCIMapIORegionFunc *map_func);

uint32_t pci_default_read_config(PCIDevice *d, 

                                 uint32_t address, int len);

void pci_default_write_config(PCIDevice *d, 

void pci_device_save(PCIDevice *s, QEMUFile *f);

int pci_device_load(PCIDevice *s, QEMUFile *f);

typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);

PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,

void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);

void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);

                        pci_map_irq_fn map_irq, const char *name);

/* prep_pci.c */

/* grackle_pci.c */

/* unin_pci.c */

/* apb_pci.c */

PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,

/* piix_pci.c */

void i440fx_set_smm(PCIDevice *d, int val);

int piix3_init(PCIBus *bus, int devfn);

void i440fx_init_memory_mappings(PCIDevice *d);

int piix4_init(PCIBus *bus, int devfn);

/* openpic.c */

enum {

    OPENPIC_EVT_INT = 0, /* IRQ                       */

    OPENPIC_EVT_CINT,    /* critical IRQ              */

    OPENPIC_EVT_DEBUG,   /* Inconditional debug event */

    OPENPIC_EVT_RESET,   /* Core reset event          */

};

/* heathrow_pic.c */

/* gt64xxx.c */

#ifdef HAS_AUDIO

struct soundhw {

    int enabled;

    int isa;

    union {

        int (*init_pci) (PCIBus *bus, AudioState *s);

    } init;

};

extern BlockDriverState *bs_table[MAX_DISKS + 1];

extern BlockDriverState *sd_bdrv;

                  BlockDriverState *hd0, BlockDriverState *hd1);

void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,

                         int secondary_ide_enabled);

/* cdrom.c */

int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);

int es1370_init (PCIBus *bus, AudioState *s);

/* sb16.c */

/* adlib.c */

/* gus.c */

/* dma.c */

typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);

typedef struct fdctrl_t fdctrl_t;

                       uint32_t io_base,

                       BlockDriverState **fds);

int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);

/* ne2000.c */

void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);

/* rtl8139.c */

void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);

void pcnet_h_reset(void *opaque);

/* vmmouse.c */

void *vmmouse_init(void *m);

/* pckbd.c */

/* mc146818rtc.c */

typedef struct RTCState RTCState;

void rtc_set_memory(RTCState *s, int addr, int val);

void rtc_set_date(RTCState *s, const struct tm *tm);

/* serial.c */

typedef struct SerialState SerialState;

                             int ioregister);

uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);

void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);

/* parallel.c */

typedef struct ParallelState ParallelState;

/* i8259.c */

extern PicState2 *isa_pic;

void pic_set_irq(int irq, int level);

void pic_set_irq_new(void *opaque, int irq, int level);

void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,

                          void *alt_irq_opaque);

int pic_read_irq(PicState2 *s);

typedef struct PITState PITState;

void pit_set_gate(PITState *pit, int channel, int val);

int pit_get_gate(PITState *pit, int channel);

int pit_get_initial_count(PITState *pit, int channel);

/* pcspk.c */

void pcspk_init(PITState *);

#include "hw/smbus.h"

extern QEMUMachine mips_malta_machine;

/* mips_int */

/* mips_timer.c */

extern void cpu_mips_clock_init(CPUState *);

#ifdef TARGET_PPC

/* PowerPC hardware exceptions management helpers */

void ppc_openpic_irq (void *opaque, int n_IRQ, int level);

int ppc_hw_interrupt (CPUState *env);

ppc_tb_t *cpu_ppc_tb_init (CPUState *env, uint32_t freq);

/* slavio_intctl.c */

void pic_set_irq_cpu(void *opaque, int irq, int level, unsigned int cpu);

void *slavio_intctl_init(uint32_t addr, uint32_t addrg,

void slavio_intctl_set_cpu(void *opaque, unsigned int cpu, CPUState *env);

void slavio_pic_info(void *opaque);

void slavio_irq_info(void *opaque);

/* loader.c */

int get_image_size(const char *filename);

                       void *intctl);

/* slavio_serial.c */

/* slavio_misc.c */

void slavio_set_power_fail(void *opaque, int power_failing);

/* esp.c */

void esp_reset(void *opaque);

/* sparc32_dma.c */

void ledma_set_irq(void *opaque, int isr);

void ledma_memory_read(void *opaque, target_phys_addr_t addr, 

                       uint8_t *buf, int len, int do_bswap);

/* cuda.c */

extern ADBBusState adb_bus;

#include "hw/usb.h"

void ps2_mouse_fake_event(void *opaque);

/* smc91c111.c */

/* pl110.c */

/* pl011.c */

/* pl050.c */

/* pl080.c */

/* pl181.c */

void pl181_init(uint32_t base, BlockDriverState *bd,

/* pl190.c */

/* arm-timer.c */

/* arm_sysctl.c */

void arm_sysctl_init(uint32_t base, uint32_t sys_id);

/* arm_gic.c */

/* arm_boot.c */